Rainbow Electronics ATR0621 User Manual

Features

•

16 Channel GPS Correlator

– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm
– Tracking Sensitivity: –150 dBm

•

Utilizes the ARM7TDMI® ARM® Thumb® Processor Core

– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Embedded ICE (In-circuit Emulator)

•

128 Kbyte Internal RAM

•

384 Kbyte Internal ROM with u-blox GPS Firmware

•

Fully Programmable External Bus Interface (EBI)

– Maximum External Address Space of 8 Mbytes
– Up to 4 Chip Selects
– Software Programmable 8-bit/16-bit External Data Bus

•

6-channel Peripheral Data Controller (PDC)

•

8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 2 External Interrupts

•

32 User-programmable I/O Lines

•

1 USB Device Port

– Universal Serial Bus (USB) V2.0 Full-speed Device Specification Compliant
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints

•

2 USARTs

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

•

Master/Slave SPI Interface

– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects

•

Programmable Watchdog Timer

•

Advanced Power Management Controller (APMC)

– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock

•

Real Time Clock (RTC)

•

2.3V to 3.6V or 1.8V Supply Voltage

•

Includes Power Supervisor

•

1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance

•

1 Kbyte Battery Backup Memory

•

9 mm × 9 mm 100-pin BGA Package (LFBGA100)

GPS Baseband
Processor

ATR0621

Summary

Preliminary

Electrostatic sensitive device.
Observe precautions for handling.

Rev. 4890AS–GPS–09/05

Note: This is a summary document. A complete document
is available under NDA. For more information, please con­tact your local Atmel sales office.

1. Description

The GPS baseband processor ATR0621 includes a 16-channel GPS correlator and is based
on the ARM7TDMI

This processor has a high-performance 32-bit RISC architecture and very low power con­sumption. In addition, a large number of internally banked registers result in very fast
exception handling, making the device ideal for real-time control applications. The ATR0621
has a USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full­speed device specification. The ATR0621 has a direct connection to off-chip memory, includ­ing Flash, through the External Bus Interface (EBI).

The ATR0621 includes full GPS firmware, licensed from u-blox AG, which performs the basic
GPS operation, including tracking, acquisition, navigation and position data output. For normal
PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM.
In order to be able to store configuration settings, connecting a serial EEPROM is supported.
For customer-specific applications, a Software Development Kit is available.

The ATR0621 is manufactured using the Atmel high-density CMOS technology. By combining
the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a
wide range of peripheral functions on a monolithic chip, the ATR0621 provides a highly-flexi­ble and cost-effective solution for GPS applications.

®

processor core.

2

ATR0621 [Preliminary]

4890AS–GPS–09/05

Figure 1-1. Block Diagram

NSHDN

NSLEEP

XT_IN

XT_OUT

RTC

SRAM

ATR0621 [Preliminary]

GPS

Accelerator

RF_ON

CLK23

P15/ANTON

P0/NANTSHORT

P14/NAADET1
P25/NAADET0

P20/TIMEPULSE

P29/GPSMODE12
P27/GPSMODE11
P26/GPSMODE10

P24/GPSMODE8
P23/GPSMODE7
P19/GPSMODE6
P17/GPSMODE5
P13/GPSMODE3
P12/GPSMODE2

P1/GPSMODE0

P9/EXTINT0

P2/BOOT_MODE

P30/AGCOUT0

P8/STATUSLED

P16/NEEPROM

P11/EM_A21
P28/EM_A20

P10/EM_A0/NLB

P7/NUB/NWR1

P6/NOE/NRD

P5/NWE/NWR0

P4/nCS0
P3/nCS1

SIGLO0

ment

Power

Manage-

Advanced

Controller

SDM

Generator

B

RID

APB

E

G

PIO2

Controller

Special

Function

PIO2

Interrupt

Advanced

Controller

Watchdog

GPS

Timer

USB USART1 USART2 SPI

Correlators

Counter

PIO2

USB

SIGHI0

P21/TXD2
P22/RXD2

P18/TXD1
P31/RXD1

USB_DP
USB_DM

Transceiver

4890AS–GPS–09/05

EM_A19

EM_A1

EM_DA15

EM_DA0

DBG_EN

NTRST

TDI
TDO
TCK
TMS

NRESET

Memory

Off-Chip

Interface to

ICE

Embedded

JTAG

Con-

Reset

troller

(EBI)

ARM7TDMI

PDC2

ASB

ROM

SRAM

Power

Supply

384K

128K

Manager

VBAT18
VBAT
LDOBAT_IN

LDO_OUT
LDO_IN
LDO_EN

3

2. Architectural Overview

2.1 Description

The ATR0621 architecture consists of two main buses, the Advanced System Bus (ASB) and
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter­faces the processor with the on-chip 32-bit memories and the external memories and devices
by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip
peripherals and is optimized for low power consumption. The AMBA Bridge provides an inter­face between the ASB and the APB.

An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip
USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most
importantly, the PDC2 removes the processor interrupt handling overhead and significantly
reduces the number of clock cycles required for a data transfer. It can transfer up to 64K con­tiguous bytes without reprogramming the starting address. As a result, the performance of the
microcontroller is increased and the power consumption reduced.

The ATR0621 peripherals are designed to be easily programmable with a minimum number of
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address
space.) The peripheral base address is the lowest address of its memory space. The periph­eral register set is composed of control, mode, data, status, and interrupt registers.

To maximize the efficiency of bit manipulation, frequently written registers are mapped into
three memory locations. The first address is used to set the individual register bits, the second
resets the bits, and the third address reads the value stored in the register. A bit can be set or
reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”
has no effect. Individual bits can thus be modified without having to use costly read-modify­write and complex bit-manipulation instructions.

All of the external signals of the on-chip peripherals are under the control of the Parallel I/O
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin
or generate an interrupt on a signal change. After reset, the user must carefully program the
PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.

The ARM7TDMI
The processor's internal architecture and the ARM
described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are
described in detail in the ATR0621 full datasheet. The electrical and mechanical characteris­tics are also documented in the ATR0621 full datasheet.

The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of
the ATR0621.

Features of the ROM firmware are described in software documentation available from u-blox
AG.

®

processor operates in little-endian mode on the ATR0621 GPS Baseband.

®

and Thumb® instruction sets are

4

ATR0621 [Preliminary]

4890AS–GPS–09/05

ATR0621 [Preliminary]

3. Pin Configuration

3.1 Pinout

Figure 3-1. Pinout LFBGA100 (Top View)

ABCDEFGHJK

10

9
8
7
6
5
4

3
2
1

Table 3-1. ATR0621 Pinout

Pull Resistor

Pin Name LFBGA100 Pin Type

CLK23 G9 IN

DBG_EN H4 IN PD

EM_A1 A6 OUT
EM_A2 A5 OUT
EM_A3 A4 OUT
EM_A4 A2 OUT
EM_A5 A3 OUT
EM_A6 B5 OUT
EM_A7 B4 OUT
EM_A8 B2 OUT

EM_A9 D4 OUT
EM_A10 C2 OUT
EM_A11 D6 OUT
EM_A12 D7 OUT
EM_A13 C3 OUT
EM_A14 C1 OUT
EM_A15 D5 OUT
EM_A16 C6 OUT
EM_A17 F8 OUT

Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset

2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29

3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup­ply of 3.0V to 3.6V is required.

(Reset Value)

ATR0621

(1)

Firmware Label PIO Bank A PIO Bank B

4890AS–GPS–09/05

5

Table 3-1. ATR0621 Pinout (Continued)

Pull Resistor

Pin Name LFBGA100 Pin Type

EM_A18 B3 OUT
EM_A19 C5 OUT
EM_DA0 B6 I/O PD
EM_DA1 B10 I/O PD
EM_DA2 C7 I/O PD
EM_DA3 C10 I/O PD
EM_DA4 D10 I/O PD
EM_DA5 E7 I/O PD
EM_DA6 E9 I/O PD
EM_DA7 B7 I/O PD
EM_DA8 B8 I/O PD

EM_DA9 A9 I/O PD
EM_DA10 C8 I/O PD
EM_DA11 B9 I/O PD
EM_DA12 D8 I/O PD
EM_DA13 C9 I/O PD
EM_DA14 D9 I/O PD
EM_DA15 E8 I/O PD

GND A1 IN
GND A10 IN
GND K1 IN
GND K10 IN

LDOBAT_IN K8 IN

LDO_EN H7 IN

LDO_IN K7 IN

LDO_OUT H6 OUT

NRESET C4 I/O Open Drain PU

NSHDN G7 OUT

NSLEEP J6 OUT

NTRST K2 IN PD

P0 K9 I/O PD NANTSHORT
P1 G3 I/O Configurable (PD) GPSMODE0 AGCOUT1
P2 G4 I/O Configurable (PD) BOOT_MODE “0” CLK32K
P3 H5 I/O OH NCS1 NCS1 “0”
P4 A7 I/O OH NCS0 NCS0 “0”
P5 B1 I/O OH NWE/NWR0 NWE/NWR0 “0”

Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset

2. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24,
P25, P26, P27 and P29

3. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, sup­ply of 3.0V to 3.6V is required.

(Reset Value)

(1)

Firmware Label PIO Bank A PIO Bank B

6

ATR0621 [Preliminary]

4890AS–GPS–09/05