Rainbow Electronics ATR0620 User Manual
Features
•
Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Embedded ICE (In-circuit Emulation)
•
128 Kbytes Internal RAM
•
Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64 MB
– Up to Four Chip Selects
– Software Programmable 8-/16-bit External Data Bus
•
16-channel GPS Correlator
– Accuracy: TBD
– Time to First Fix: TBD
•
8-channel Peripheral Data Controller (PDC)
•
8-level Priority, Individually Maskable, Vectored Interrupt Controller
– Three External Interrupts
•
20 Programmable I/O Lines
•
Three USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
•
Master/Slave SPI Interface
– Two Dedicated Peripheral Data Controller (PDC) Channels
– 8- to 16-bit Programmable Data Length
– Four External Slave Chip Selects
•
Programmable Watchdog Timer
•
Power Management Controller (PMC)
– CPU and Peripherals Can Be Deactivated Individually
•
Clock Manager (CLM)
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
•
PWM Controller
– Two PWM Signals
•
Real Time Clock (RTC)
– Time in GPS Format and 15-bit Fractional Part of a Second
– Programmable Interrupt
– Timer with a 8-bit Fractional Part of a Second and Parallel Load
•
2.3V to 3.6V or 1.8V Supply Voltage
•
Includes Power Supervisor
•
Battery Backup Memory
•
9 mm × 9 mm 100-pin BGA Package
GPS Baseband
Processor
ATR0620
Summary
Preliminary
Rev. 4574CS–GPS–05/05
1. Description
The GPS baseband processor ATR0620 includes a 16-channel GPS correlator and is based on
the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit
instruction set and very low power consumption. In addition, a large number of internally banked
registers result in very fast exception handling, making the device ideal for real-time control
applications.
The ATR0620 has a direct connection to off-chip memory, including flash, through the External
Bus Interface (EBI).
The ATR0620 is manufactured using Atmel’s high-density CMOS technology. By combining the
ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide
range of peripheral functions on a monolithic chip, the ATR0620 provides a highly flexible and
cost-effective solution for GPS applications.
2
ATR0620 [Preliminary]
4574CS–GPS–05/05
Figure 1-1. Block Diagram
nSHDN
nSLEEP
CLK32768
RF_ON
RTC
Power
ATR0620 [Preliminary]
P29/GPSMODE10
GPS
Accelerator
PIO2
GPS
Correlators
Manage-
ment
SRAM
Controller
P27/GPSMODE7
P26/GPSMODE5
P25/GPSMODE3
P24/GPSMODE2
P23/GPSMODE4
P20/TIMEPULSE
P19/GPSMODE9
P17/GPSMODE1
P14/GPSMODE0
P13/GPSMODE11
P12/GPSMODE8
P1/GPSMODE6
SIGLO
SIGHI
P11/EXTINT2
P9/EXTINT0
P16/NWD_OVF
P30/BOOT_MODE0
P28/EM_A20
P10/EM_A0/NLB
P8/PDSR8
P7/NUB/NWR1
P6/NOE/NRD
P5/NWE/NWR0
P4/nCS0
P3/nCS1
P2/BOOT_MODE1
EM_A19
EM_A1
EM_DA15
EM_DA0
PWM
Generator
Clock
Manager
(CLM)
CLK23
APB
PIO2
Controller
P21/TXD2
P22/RXD2
Special
Function
PIO2
Interrupt
Controller
Advanced
Watchdog
(EBI)
Interface to
Off-Chip Memory
B
RID
E
G
USART0 USART1 USART2 SPI
PDC2
PIO2
P18/TXD1
P31/RXD1
P15/TXD0
P0/RXD0
4574CS–GPS–05/05
DBG_EN
TEST_MODE
nTRST
TDO
TCK
TMS
nRESET
288K
ASB
ROM
ICE
Embedded
ARM7TDMI
128K
SRAM
TDI
JTAG
Con-
Reset
VBAT18_O
VBAT
VBAT18_I
Power
Supply
Manager
troller
LDOBAT_IN
LDO_OUT
LDO_IN
LDO_EN
3
Table 1-1. Pin Configuration
Serial
Number BGA 100 CPGA 144 Pin Name
1 B6 C8 EM_DA0 (1) (1) (1) (1) (1)
2 B10 D13 EM_DA1 (1) (1) (1) (1) (1)
3 C7 B10 EM_DA2 (1) (1) (1) (1) (1)
4 C10 C15 EM_DA3 (1) (1) (1) (1) (1)
5 D10 F13 EM_DA4 (1) (1) (1) (1) (1)
6 E7 E15 EM_DA5 (1) (1) (1) (1) (1)
7 E9 F15 EM_DA6 (1) (1) (1) (1) (1)
8 B7 C9 EM_DA7 (1) (1) (1) (1) (1)
9 B8 B11 EM_DA8 (1) (1) (1) (1) (1)
10 A9 A14 EM_DA9 (1) (1) (1) (1) (1)
11 C8 B12 EM_DA10 (1) (1) (1) (1) (1)
12 B9 B13 EM_DA11 (1) (1) (1) (1) (1)
13 D8 E13 EM_DA12 (1) (1) (1) (1) (1)
14 C9 C14 EM_DA13 (1) (1) (1) (1) (1)
15 D9 D15 EM_DA14 (1) (1) (1) (1) (1)
16 E8 G14 EM_DA15 (1) (1) (1) (1) (1)
17 K5 N9 P15 TXD0 (1) TXD0 (1) MSOUT
18 K9 P14 P0 RXD0 RXD0 (1) (1) (1)
19 J5 Q10 P14 GPSMODE4 SCK0 SCK0 (1) GPS_MON5
20 K4 Q7 P18 TXD1 (1) TXD1 (1) NUB/NWR1
21 H9 N15 P31 RXD1 RXD1 (1) (1) (1)
22 J4 P8 P17 GPSMODE5 SCK1 SCK1 (1) GPS_MON6
23 F9 H14 SIGHI (1) (1) (1) (1) (1)
24 E10 G13 SIGLO (1) (1) (1) (1) (1)
25 J9 N14 XT_IN (1) (1) (1) (1) (1)
26 J10 P15 XT_OUT (1) (1) (1) (1) (1)
27 J6 Q11 nSLEEP (1) (1) (1) (1) (1)
28 G9 J13 CLK23 (1) (1) (1) (1) (1)
29 G5 N8 P30 BOOT_MODE0 (1) NWD_OVF (1) GPS_MON0
30 G4 P7 P2 BOOT_MODE1 (1) 1PPS (1) GPS_MON1
31 J1 P2 TMS (1) (1) (1) (1) (1)
32 J3 P6 TCK (1) (1) (1) (1) (1)
33 J2 P4 TDI (1) (1) (1) (1) (1)
34 K2 Q3 nTRST (1) (1) (1) (1) (1)
35 K3 N6 TDO (1) (1) (1) (1) (1)
36 F4 N1 TEST_MODE (1) (1) (1) (1) (1)
37 H4 N7 DBG_EN (1) (1) (1) (1) (1)
38 K6 N10 RF_ON (1) (1) (1) (1) (1)
39 C4 B3 nRESET (1) (1) (1) (1) (1)
40 G7 L14 nSHDN (1) (1) (1) (1) (1)
41 A6 B8 EM_A1 (1) (1) (1) (1) (1)
42 A5 A6 EM_A2 (1) (1) (1) (1) (1)
43 A4 A5 EM_A3 (1) (1) (1) (1) (1)
44 A2 C3 EM_A4 (1) (1) (1) (1) (1)
45 A3 C5 EM_A5
Firmware
Label
Note: 1. No selection option for PIO.
PIO Bank A PIO Bank B
IOIO
4
ATR0620 [Preliminary]
4574CS–GPS–05/05
ATR0620 [Preliminary]
Table 1-1. Pin Configuration (Continued)
Serial
Number BGA 100 CPGA 144 Pin Name
46 B5 B7 EM_A6 (1) (1) (1) (1) (1)
47 B4 A3 EM_A7 (1) (1) (1) (1) (1)
48 B2 B1 EM_A8 (1) (1) (1) (1) (1)
49 D4 F2 EM_A9 (1) (1) (1) (1) (1)
50 C2 F3 EM_A10 (1) (1) (1) (1) (1)
51 D6 A9 EM_A11 (1) (1) (1) (1) (1)
52 D7 C10 EM_A12 (1) (1) (1) (1) (1)
53 C3 C1 EM_A13 (1) (1) (1) (1) (1)
54 C1 E2 EM_A14 (1) (1) (1) (1) (1)
55 D5 A4 EM_A15 (1) (1) (1) (1) (1)
56 C6 C7 EM_A16 (1) (1) (1) (1) (1)
57 F8 H13 EM_A17 (1) (1) (1) (1) (1)
58 B3 C4 EM_A18 (1) (1) (1) (1) (1)
59 C5 C6 EM_A19 (1) (1) (1) (1) (1)
60 E5 Q1 VDD18_R (1) (1) (1) (1) (1)
61 E6 A1 VDD18_B (1) (1) (1) (1) (1)
62 F7 K15 VDD18_L2 (1) (1) (1) (1) (1)
63 F6 A15 VDD18_L1 (1) (1) (1) (1) (1)
64 J7 P13 VBAT (1) (1) (1) (1) (1)
65 A1 D3 GND_R (1) (1) (1) (1) (1)
66 A10 C12 GND_B (1) (1) (1) (1) (1)
67 K1 N4 GND_T (1) (1) (1) (1) (1)
68 F10 J15 GND_L (1) (1) (1) (1) (1)
69 K10 M13 GND_BAT (1) (1) (1) (1) (1)
70 H1 N2 P24 GPSMODE8 MOSI MOSI (1) GPS_MON2
71 D1 G3 P25 GPSMODE9 MISO MISO (1) GPS_MON3
72 H3 P5 P23 GPSMODE7 SCK SCK (1) MCLK_OUT
73 G8 M15 P26 GPSMODE10 NSS NPCS0 (1) GPS_MON4
74 J8 N13 P9 GPSMODE1 EXTINT0 (1) (1) EM_A0/NLB
75 H7 N12 LDO_EN (1) (1) (1) (1) (1)
76 H6 Q13 LDO_OUT (1) (1) (1) (1) (1)
77 H5 P9 P3 (OH) nCS1 (1) nCS1 (1) AGCOUT0
78 A7 B9 P4 (OH) nCS0 (1) nCS0 (1) (1)
79 B1 D2 P5 (OH) NWE/NWR0 (1) NWE/NWR0 (1) (1)
80 A8 A13 P6 (OH) NOE/NRD (1) NOE/NRD (1) (1)
81 K7 P12 LDO_IN (1) (1) (1) (1) (1)
82 D2 G1 P7 (OH) NUB/NWR1 (1) NUB/NWR1 (1) (1)
83 E4 H2 P10 (OH) EM_A0/NLB (1) EM_A0/NLB (1) MCLK_OUT
84 H10 L13 P11 EM_A21 EXTINT2 (1) (1) EM_A21
85 G2 L3 P8 OUT (RFU) (1) AGCOUT0 (1) GPS_MON10
86 E1 H3 P16 NWD_OVF SIGHI2 (1) (1) NWD_OVF
87 F1 J2 P19 GPSMODE6 SIGLO2 (1) (1) EM_A20
88 G3 M3 P1 GPSMODE0 (1) AGCOUT1 (1) GPS_MON7
89 K8 Q14 LDOBAT_IN (1) (1) (1) (1) (1)
90 F2 K3 P21 TXD2 (1) TXD2 (1) EM_A22
91 H8 M14 P22 RXD2 RXD2 (1) (1) EM_A23
Firmware
Label
Note: 1. No selection option for PIO.
PIO Bank A PIO Bank B
IOIO
4574CS–GPS–05/05
5
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