Rainbow Electronics ATR0600 User Manual

Features

• Very Low Power Design (≈ 50 mW)

• Single IF Concept

• 2-bit ADC on Chip

• Small QFN Package (28 Pins)

• Highly Integrated, Few External Components

• UHF6 Technology

GPS

Electrostatic sensitive device. Observe precautions for handling.

Description

With the growing importance of mobile communication, location awareness is a key feature for more and more products and services. Due to its small size and minimal power consumption, the GPS front-end IC ATR0600 is an ideal solution for mobile applications and navigation systems.

Figure 1. Block Diagram

1575.42 MHz

Ant

LNA

SAW

RFIN

RFNIN

VS3

VCO

1478.6

MHz

96.76 MHz LC-BP

NBPI

BPI

NBP

VGA amp

BP-Filter

PFD XTO

REF

Power control

VDIG

Dig. IF at 4.35 MHz

SIGH

SIGL

23.104 MHz

AGCO

Front-end IC

ATR0600

Preliminary

VS1

VS2

VS5

VS7

XTO

23.104 MHz

NXTO

Rev. 4536F–GPS–10/03

Pin Configuration

Figure 2. Pinning QFN28

NBP

BPI

NBPI

VS1

n.c. n.c.

. n

14 13 12 11 10 9 8

15 16 17 18 19 20 21

22 23 24 25 26 27 28

C G

. c

VS5

XTO

NXTO

VS7

AGCO

Pin Description

Pin Symbol Type Function Protection Level

1 AGCO O Signal level output ESD3 2 NX OB Complementary to X ESD3 3 VS7 P ECL - blocks supply ESD2 4 NXTO IB Complementary to XTO ESD3 5 XTO IB Quartz input ESD3 6 VS5 P XTO supply ESD2 7 X OB Quartz intermediate output ESD3 8 n.c. – Not connected –

9 P2 I Power-up quartz oscillator ESD3 10 P1 I Power-up RF part ESD3 11 VS3 P Reference supply ESD2 12 RFIN IB RF input 1.575 GHz ESD3 13 RFNIN IB Complementary to RFIN ESD3 14 n.c. – Not connected – 15 BP IB Open-collector output of mixer ESD3 16 NBP IB Complementary to BP ESD3 17 BPI IB IF - filter input ESD3 18 NBPI IB Complementary to BPI ESD3 19 VS1 P VCO + mixer + VGA supply ESD2 20 n.c. – Not connected – 21 n.c. – Not connected – 22 GC I Gain control input ESD3 23 VS2 P Subsampling unit supply ESD2 24 REF O Defining low threshold voltage ESD3 25 SIGL O Digital interface subsampled output high threshold voltage refered to REF1 ESD3 26 SIGH O Digital interface subsampled output low threshold voltage refered to REF2 ESD3 27 VDIG P Digital interface supply voltage 1.8 V ESD2 28 SC O Digital interface clock output ESD3

ATR0600 [Preliminary]

4536F–GPS–10/03

ATR0600 [Preliminary]

Functional Description

The specification of GPS receivers for personal mobile applications strongly differs from stand-alone GPS receiver specifications. One reason is the presence of strong blocking signals from mobile transmitters which might cause unacceptable levels of degradation in the carrier-to-noise ratio of a GPS system if not sufficiently suppressed. The other reason is the requirements for very low power consumption.

The ATR0600 GPS receiver IC has been especially designed for GPS applications in mobile phones. From this system point of view, it incorporates highest isolation between GPS and cellular antennas, as well as low power consumption. The ATR0600 contains a low-power single IF design and integrates a complete frequency synthesizer. It is fully functional over a supply-voltage range of 2.7 V to 3.3 V and is housed in a 28-pin QLN package.

The GPS receiver's input signal is a Direct Sequence Spread Spectrum (DSSS) signal at 1575.42 MHz with a 1.023 Mbps Bi-Phase-Shift-Keying (BPSK) modulated spreading code. As the input signal power at the antenna is approximately -140 dBm, the desired signal is below the thermal noise floor.

LNA/Mixer Stage The ATR0600 receives the L1 GPS signal via an external LNA. The LNA bandwidth

should be as narrow as possible to avoid interferences from out-of-band signals (especially from those of the 1800 GSM band).

Combined with the antenna the LNA provides a first filtering of the GPS signal. The LNA in addition should have a power shutdown feature. The shutdown signal will be generated inside the digital section of the GPS receiver. The output of the LNA drives an external SAW filter, which provides the image rejection for the mixer and the isolation of the 1800-MHz GSM band. The output of the SAW filter drives a highly linear mixer which down-converts the GPS signal to an IF of 97.76 MHz.

IF Stage The mixer directly drives an external LC-bandpath filter. In order to provide the ultimate

selectivity of the GPS frequency before the A/D conversion of the receiver part, the signal path of the ATR0600 combines an external filter and a second integrated filter. We recommend to design the external filter as a 2-pole filter with quality factor Q > 25.

VGA Amplifier Stage The output of the LC-filter drives an on-chip Variable Gain-Controlled amplifier (VGA)

which is combined with an integrated IF-bandpath filter to perform additional filtering of GSM jamming signals. The AGC stage provides the additional gain needed to optimally load the signal range of the following analog/digital converter. The AGC control loop can be selected either on-chip close loop or open loop mode. Connecting the AGC_OUT output directly to the AGC_CNTRL input activates the internal control loop.

In that case, the VGA control signal is passed to the VGA via an integrated buffer stage including all necessary filtering (low-pass filter). The external control loop is closed by the baseband IC ATR0620.

A/D Converter Stage The output of the VGA drives the integrated 1.5-bit analog-to-digital converter stage,

which comprises two comparators and two output drivers in order to provide sign and magnitude output bits to the baseband IC ATR0620. The comparator LOW- and HIGHthresholds (in Figure 1 on page 1 for SIGH and SIGL) are adjustable via external resistor. The OR gate closes the internal AGC control loop.

Power Save Setting Stage

The integrated power-control stage is controlled by the baseband IC ATR0620 via P1 and P2. The input signals control the shutdown of the reference crystal oscillator (P2) or the shutdown of the whole RF section (P1).

4536F–GPS–10/03

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Value Unit

Supply voltage V Input voltage V Junction temperature T Storage temperature range T

stg

3.7 V

125 °C

-40 to +125 °C

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient R

thJA

125 K/W

Recommended Operating Conditions

Parameters Symbol Value Unit

Supply voltage V

Temperature range Temp -40 to +85 °C Input frequency f Reference frequency f

in, mixer

ref

External IF filter (see Figure 13 on page 9) Supply voltage digital interface, pin 27 V

2.7 to 3.3 V

1575.42 MHz

23.104 MHz

1.65 to 2.0 V

Electrical Characteristics

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1Common

3, 6,

1.1 Supply current P1 = P2 = VPU

11,

19, 23

1.2 Supply current XTO

1.3

Supply current digital interface

P1 = VPU P2 = VPU

P1 = P2 = VPU

off on

27 I

3, 6,

1.4

Supply current (power down)

P1 = P2 = VPU

OFF

11, 19,

23, 27

1.5 Total gain

RFIN, RNIN matched, to 50 W, V

= 2.2 V

1 G 95 dB B

1.6 Noise figure N

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

XTO

S, pd

18 mA A

2mAA

250 µA A

20 µA A

6.9 dB C

ATR0600 [Preliminary]

4536F–GPS–10/03

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