Rainbow Electronics ATmega8L User Manual

Features

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• High-performance, Low-power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories

– 8K bytes of In-System Self-Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Byte Internal SRAM – Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and MLF package

6 Channels 10-bit Accuracy 2 Channels 8-bit Accuracy

– 6-channel ADC in PDIP package

4 Channels 10-bit Accuracy 2 Channels 8-bit Accuracy

– Byte-oriented 2-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down and

Standby

• I/O and Packages

– 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad MLF

• Operating Voltages

– 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8)

• Speed Grades

– 0 - 8 MHz (ATmega8L) – 0 - 16 MHz (ATmega8)

• Power Consumption

– Active: TBD – Idle Mode: TBD – Power-down Mode: TBD

8-bit Microcontroller

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

ATmega8 ATmega8L

Advance Information

Summary

ava il a ble on ou r w e b site at www.atmel.com.

s a summary docum ent. A complete document is

Rev. 2486AS - 08/01

Pin Configurations

PDIP

(RESET) PC6

(XCK/T0) PD4

(XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7

(INT1) PD3

(XCK/T0) PD4

GND VCC GND

VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7

(RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3

VCC GND

(T1) PD5 (AIN0) PD6 (AIN1) PD7

(ICP) PB0

TQFP Top View

1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8 9 10 11 12 13 14

PD2 (INT0)

PD1 (TXD)

32313029282726

9101112131415

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PC4 (ADC4/SDA)

PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) AGND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A)

PC3 (ADC3)

PC2 (ADC2)

PC1 (ADC1)

PC0 (ADC0)

ADC7

AGND

AREF

ADC6

AVCC

PB5 (SCK)

(T1) PD5

(ICP) PB0

(AIN0) PD6

(AIN1) PD7

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

MLF Top View

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

32313029282726

(INT1) PD3

(XCK/T0) PD4

(XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7

ATmega8

GND VCC GND VCC

1 2 3 4 5 6 7 8

9101112131415

(T1) PD5

(AIN0) PD6

(ICP) PB0

(AIN1) PD7

(MISO) PB4

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

24 23 22 21 20 19 18 17

PC1 (ADC1) PC0 (ADC0) ADC7 AGND AREF ADC6 AVCC PB5 (SCK)

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ATmega8

Overview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

Block Diagram Figure 1. Block Diagram

XTAL1

RESET

VCC

PC0 - PC6 PB0 - PB7

XTAL2

GND

AGND

AREF

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

MUX &

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

AVR CPU

ADC

INTERFACE

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

ALU

STATUS

PORTB DRIVERS/BUFFERS

PORTB DIGITAL INTERFACE

TWI

TIMERS/

COUNTERS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

INTERRUPT

UNIT

EEPROM

OSCILLATOR

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PROGRAMMING

LOGIC

SPI

COMP.

INTERFACE

USART

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general-purpose I/O lines, 32 general purpose working registers, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented 2-wire Serial Interface, a 6-channel ADC (8 channels in TQFP and MLF packages) where 4 (6) channels have 10-bit accuracy and 2 channels have 8-bit accuracy, a programmable Watchdog Timer with internal oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction Mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The Flash program memory can be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash Memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.

The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-circuit emulators, and evaluation kits.

Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port B (PB7..PB0)/XTAL1 /XTAL2 /TOSC1 /TOSC2

ATmega8

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator amplifier.

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ATmega8

If the Internal Calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated on page 54.

Port C (PC6..PC0) / RESET

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

If the RSTDISBL fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 34. Shorter pulses are not guaranteed to generate a reset.

The various special features of Port C are elaborated on page 57.

Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8 as listed on page 59.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 34. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally

connected to V nected to V

, even if the ADC is not used. If the ADC is used, it should be con-

through a low-pass filter.

AREF AREF is the analog reference pin for the A/D Converter.

ADC7..6 (TQFP and MLF Package Only)

In the TQFP and MLF package, ADC7..6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.

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