Rainbow Electronics ATmega8L User Manual

Features

Not

This i

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories

– 8K bytes of In-System Self-Programmable Flash

Endurance: 1,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program
True Read-While-Write Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K Byte Internal SRAM
– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and MLF package

6 Channels 10-bit Accuracy
2 Channels 8-bit Accuracy

– 6-channel ADC in PDIP package

4 Channels 10-bit Accuracy
2 Channels 8-bit Accuracy

– Byte-oriented 2-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down and

Standby

• I/O and Packages

– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad MLF

• Operating Voltages

– 2.7 - 5.5V (ATmega8L)
– 4.5 - 5.5V (ATmega8)

• Speed Grades

– 0 - 8 MHz (ATmega8L)
– 0 - 16 MHz (ATmega8)

• Power Consumption

– Active: TBD
– Idle Mode: TBD
– Power-down Mode: TBD

®

8-bit Microcontroller

8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash

ATmega8
ATmega8L

Advance
Information

Summary

e:

ava il a ble on ou r w e b site at www.atmel.com.

s a summary docum ent. A complete document is

Rev. 2486AS - 08/01

1

Pin Configurations

PDIP

(RESET) PC6

(XCK/T0) PD4

(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

(INT1) PD3

(XCK/T0) PD4

GND
VCC
GND

VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3

VCC
GND

(T1) PD5
(AIN0) PD6
(AIN1) PD7

(ICP) PB0

TQFP Top View

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8
9
10
11
12
13
14

PD2 (INT0)

PD1 (TXD)

32313029282726

9101112131415

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PC4 (ADC4/SDA)

PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
AGND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)

PC3 (ADC3)

PC2 (ADC2)

25

24

PC1 (ADC1)

23

PC0 (ADC0)

22

ADC7

21

AGND

20

AREF

19

ADC6

18

AVCC

17

PB5 (SCK)

16

(T1) PD5

(ICP) PB0

(AIN0) PD6

(AIN1) PD7

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

(MISO) PB4

MLF Top View

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

32313029282726

(INT1) PD3

(XCK/T0) PD4

(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

2

ATmega8

GND
VCC
GND
VCC

1
2
3
4
5
6
7
8

9101112131415

(T1) PD5

(AIN0) PD6

(ICP) PB0

(AIN1) PD7

25

16

(MISO) PB4

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

24
23
22
21
20
19
18
17

PC1 (ADC1)
PC0 (ADC0)
ADC7
AGND
AREF
ADC6
AVCC
PB5 (SCK)

2486AS–08/01

ATmega8

Overview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega8
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed.

Block Diagram Figure 1. Block Diagram

XTAL1

RESET

VCC

PC0 - PC6 PB0 - PB7

XTAL2

GND

AGND

AREF

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

MUX &

ADC

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

AVR CPU

ADC

INTERFACE

STACK

POINTER

SRAM

GENERAL
PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PORTB DRIVERS/BUFFERS

PORTB DIGITAL INTERFACE

TWI

TIMERS/

COUNTERS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

INTERRUPT

UNIT

EEPROM

OSCILLATOR

OSCILLATOR

2486AS–08/01

PROGRAMMING

LOGIC

+

-

SPI

COMP.

INTERFACE

USART

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7

3

The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.

The ATmega8 provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23
general-purpose I/O lines, 32 general purpose working registers, three flexible
timer/counters with compare modes, internal and external interrupts, a serial program­mable USART, a byte oriented 2-wire Serial Interface, a 6-channel ADC (8 channels in
TQFP and MLF packages) where 4 (6) channels have 10-bit accuracy and 2 channels
have 8-bit accuracy, a programmable Watchdog Timer with internal oscillator, an SPI
serial port, and five software selectable power saving modes. The Idle mode stops the
CPU while allowing the SRAM, timer/counters, SPI port, and interrupt system to con­tinue functioning. The Power-down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next interrupt or hardware reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to main­tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction
Mode stops the CPU and all I/O modules except asynchronous timer and ADC, to mini­mize switching noise during ADC conversions. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low-power consumption.

The device is manufactured using Atmel’s high density nonvolatile memory technology.
The Flash program memory can be reprogrammed In-System through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an on-chip boot pro­gram running on the AVR core. The boot program can use any interface to download the
application program in the Application Flash Memory. Software in the Boot Flash Sec­tion will continue to run while the Application Flash Section is updated, providing true
Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Pro­grammable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller
that provides a highly-flexible and cost-effective solution to many embedded control
applications.

The ATmega8 AVR is supported with a full suite of program and system development
tools, including C compilers, macro assemblers, program debugger/simulators, In-circuit
emulators, and evaluation kits.

Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port B (PB7..PB0)/XTAL1 /XTAL2 /TOSC1 /TOSC2

4

ATmega8

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the invert­ing oscillator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the
inverting oscillator amplifier.

2486AS–08/01

ATmega8

If the Internal Calibrated RC oscillator is used as chip clock source, PB7..6 is used as
TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated on page 54.

Port C (PC6..PC0) / RESET

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

If the RSTDISBL fuse is unprogrammed, PC6 is used as a Reset input. A low level on
this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in Table 15 on page 34. Shorter
pulses are not guaranteed to generate a reset.

The various special features of Port C are elaborated on page 57.

Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8 as listed on
page 59.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener­ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 34. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally

connected to V
nected to V

, even if the ADC is not used. If the ADC is used, it should be con-

CC

through a low-pass filter.

CC

AREF AREF is the analog reference pin for the A/D Converter.

ADC7..6 (TQFP and MLF Package Only)

In the TQFP and MLF package, ADC7..6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.

2486AS–08/01

5

Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F (0x5F) SREG I T H S V N Z C 7

0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 10

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 S P3 SP2 SP1 SP0 10

0x3C (0x5C) Reserved

0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 45, 63

0x3A (0x5A) GIFR INTF1 INTF0

0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1

0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1

0x37 (0x57) SP MCR SPMIE RWWSB – RWWSRE BLBSET PGWRT P GERS SPMEN 201

0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN

0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 29, 62

0x34 (0x54) MCUCSR

0x33 (0x53) TCCR0

0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 68

0x31 (0x51)

0x30 (0x50) SFIOR - - - ADHSM ACME PUD PSR2 PSR10 53, 70, 116, 181

0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 92

0x2E (0x4E) TCCR1B ICNC1 ICE S1

0x2D (0x4D) TCNT1H Timer/Counter1 - Counter Register High Byte 96

0x2C (0x4C) TCNT1L Timer/Counter1 - Counter Register Low Byte 96

0x2B (0x4B) OCR1AH

0x2A (0x4A) OCR1AL

0x29 (0x49) OCR1BH

0x28 (0x48) OCR1BL

0x27 (0x47) ICR1H Timer/Counter1 - Input Capture Register High Byte 96

0x26 (0x46) ICR1L Timer/Counter1 - Input Capture Register Low Byte 96

0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 109

0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 111

0x23 (0x43) OCR2

0x22 (0x42) ASSR - - - - AS2 TCN2UB OCR2UB TCR2UB 112

0x21 (0x41) WDTCR

(1)

0x20

(0x40)

0x1F (0x3F) EEARH - - - - - - - EEAR8 17

0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 17

0x1D (0x3D) EEDR EEPROM Data Register 17

0x1C (0x3C) EECR - - - - EERIE EEMWE EEWE EERE 17

0x1B (0x3B) Reserved

0x1A (0x3A) Reserved

0x19 (0x39) Reserved

0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 61

0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 61

0x16 (0x36) PINB PINB7 PINB6 P INB5 PINB4 PINB3 PINB2 PINB1 PINB0 61

0x15 (0x35) PORTC

0x14 (0x34) DDRC - DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 61

0x13 (0x33) PINC - PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 61

0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 61

0x11 (0x31) DDRD DDD 7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 61

0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 61

0x0F (0x2F) SPDR SPI Data Register 123

0x0E (0x2E) SPSR SPIF WCOL - - - - -SPI2X 122

0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 121

0x0C (0x2C) UDR USART I/O Data Register 144

0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 145

0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 146

0x09 (0x29) UBRRL USART Baud Rate Register Low Byte 148

0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 181

0x07 (0x27) ADM UX REFS1 REFS0 ADLAR - M UX3 MUX2 MUX1 MUX0 193

0x06 (0x26) ADCSR ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 195

0x05 (0x25) ADCH ADC Data Register High Byte 196

0x04 (0x24) ADCL ADC Data Register Low Byte 196

0x03 (0x23) TWDR 2-wire Serial Interface Data Register 161

0x02 (0x22) TWAR TW A6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 162

0x01 (0x21) TWSR TWS7

OSCCAL Oscillator Calibration Register 27

UBRRH URSEL - - - UBRR[11: 8] 148

(1)

UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 147

- - - - WDRF BORF EXTRF PORF 37

- - - - - CS02 CS01 CS00 67

- - - WDCE WDE WDP2 WDP1 WDP0 39

- PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 61

TWS6 TWS5 TWS4 TWS3

– – – – - -63

- WGM13 WGM12 CS12 CS11 CS10 95

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter2 Output Compare Register

-

– TOIE0 68, 97, 114

– TOV0 68, 97, 115

– TWIE 160

TWPS1 TWPS0

96

96

96

96

112

161

6

ATmega8

2486AS–08/01

ATmega8

Register Summary (Continued)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x00 (0x20) TWBR 2-wire Serial Interface Bit Rate Register 160

Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.

2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.

2486AS–08/01

7

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V ,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V ,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • KZ,N,V1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr)

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr )

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← k None 3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← Z None 3

CALL k Direct Subroutine Call PC ← k None 4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

<< 1 Z,C 2
<< 1 Z,C 2

8

ATmega8

2486AS–08/01

ATmega8

Instruction Set Summary (Continued)

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1 / 2

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word

LDI Rd, K Load Immediate Rd ← K None 1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← P None 1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd A rithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

Rd+1:Rd ← Rr+1:Rr

None 1

2486AS–08/01

9

Instruction Set Summary (Continued)

CLH Clear Half Carry Flag in SREG H ← 0 H 1

MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A

10

ATmega8

2486AS–08/01

ATmega8

Ordering Information

Speed (MHz) Power Supply Ordering Code Package Operation Range

2.7 - 5.5 8 ATmega8L-8AC
ATmega8L-8PC
ATmega8L-8MC

ATmega8L-8AC
ATmega8L-8PI
ATmega8L-8MI

4.5 - 5.5 16 ATmega8-16AI
ATmega8-16PC
ATmega8-16MC

ATmega8-16AI
ATmega8-16PI
ATmega8-16MI

32A
28P3
32M1-A

32A
28P3
32M1-A

32A
28P3
32M1-A

32A
28P3
32M1-A

Commercial

(0°C to 70°C)

Industrial

°C to 85°C)

(-40

Commercial

°C to 70°C)

(0

Industrial

(-40

°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF)

2486AS–08/01

11

Packaging Information

32A

32-lead, Thin (1.0mm) Plastic Quad Flatpack
(TQFP), 7x7mm body, 2.0mm footprint, 0.8mm pitch.
Dimensions in Millimeters and (Inches)*
JEDEC STADARD MS-026 ABA

PIN 1 ID

0.45 (0.018)

0.30 (0.012)

0.80 (0.0315) BSC

0.20 (0.008)

0.09 (0.004)

9.25 (0.364)

8.75 (0.344)

PIN 1

7.10 (0.280)

6.90 (0.272)

0º~7º

SQ

9.25 (0.364)

8.75 (0.344)

1.20 (0.047) MAX

12

ATmega8

0.75 (0.030)

0.45 (0.018)

*Controlling dimensions: Millimeters

0.15 (0.006)

0.05 (0.002)

2486AS–08/01

28P3

ATmega8

28-lead, Plastic Dual Inline
Package (PDIP), 0.300" Wide, (0.288" body width)
Dimensions in Millimeters and (Inches)*

34.80(1.370)

34.54(1.360)

7.49(0.295)

7.11(0.280)

4.57(0.180)MAX

3.56(0.140)

3.05(0.120)

2.54(0.100)BSC

0.38(0.015)

0.56(0.022)

0.38(0.015)

1.65(0.065)

1.27(0.050)

8.26(0.325)

7.62(0.300)

0º~ 15º REF

10.20(0.400)MAX

2486AS–08/01

*Controlling dimension: Inches

REV. A 04/11/2001

13

32M1-A

PIN #1 ID

D

D1

1

2
3

E1

E

0

TOP VIEW

P

D2

PIN 1 ID

P

b

BOTTOM VIEW

NOTE 1. JEDEC STANDARD MO-220, Fig 2 (Anvil Singulation), VHHD-2

e

1

2
3

E2

L

A2

A

SIDE VIEW

SYMBOL

A

A1

A2

A3

b

D1 4.75 BSC

D2

E 5.00 BSC

E1 4.75 BSC

E2 1.25 - 3.25

e 0.50 BSC

L 0.30 0.40 0.50

P

0

A3

A1

C

0.08

COMMON DIMENSIONS

(*Unit of Measure = mm)

MIN

0.80 0.90 1.00

0.00 0.02 0.05

- 0.65 1.00

0.20 REF

0.18 0.23 0.30

5.00 BSCD

1.25 - 3.25

- - 0.60

- - 12º

NOM

MAX

NOTE

14

2325 Orchard Parkway

R

R

San Jose, CA 95131

ATmega8

TITLE

32M1-A, 32-pad, 5x5x1.0mm body, Lead Pitch 0.50mm

06/27/01

Mirco Lead Frame package (MLF)

DRAWING NO. REV

32M1-A

A

2486AS–08/01

Atmel Headquarters Atmel Product Operations

Corporate Headquarters

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© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
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®

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Other terms and product names may be the trademarks of others.

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2486AS–08/01