Rainbow Electronics ATmega8HVD User Manual

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 124 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 4 MIPS Throughput at 4 MHz

• Nonvolatile Program and Data Memories

– 4K/8K Bytes of In-System Self-Programmable Flash (ATmega4HVD/8HVD) – 256 Bytes EEPROM – 512 Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data Retention: 20 years at 85°C /100 years at 25°C – Programming Lock for Software Security

• Battery Management Features

– One Cell Batteries – Short-circuit Protection (Discharge) – Over-current Protection (Charge and Discharge) – External Protection Input – High Voltage Outputs to Drive N-Channel Charge/Discharge FETs – Operation with 1 FET or 2 FETs supported

Charge FET is optional

– Battery authentication features (Availab le only under NDA)

• Peripheral Features

– Two 8/16-bit Timer/Counters with Separate Prescaler and two output compare

units – 10-bit ADC with One External Input – Two High-voltage open-drain I/O pins – Programmable Watchdog Timer

• Special Microcontroller Features

– debugWIRE On-chip Debug System – In-System Programmable – Power-on Reset – On-chip Voltage Reference with built-in Temperature Sensor – On-chip Voltage Regulator – External and Internal Interrupt Sources – Sleep Modes:

Idle, ADC Noise Reduction, Power-save, and Power-off

• Package

– 18-pad DRDFN/ MLF

• Operating Voltage (VFET): 2.1 - 6.0V

• Operating Voltage (V

• Maximum Withstand Voltage (VFET): 12V

• Maximum Withstand Voltage (High-voltage pins): 5V

• Temperature Range: -20°C to 85°C

• Speed Grade: 1 - 4 MHz

):2.0 - 2.4V

8-bit Microcontroller

(1)

8-bit

Microcontroller with 4K/8K Bytes In-System Programmable Flash

ATmega4HVD ATmega8HVD

Preliminary

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1. Pin Configurations

Figure 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD.

Top view

Bottom view

B10

Table 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD.

123 4 5 6 7 8 9 10

PB1

DNC BATT GND PV1

OD OC VFET VREG NI

(SCK/

SGND/T0)

DNC VCC

PB0

(ADC0)

(MISO/CKOUT/T1)

PB2

PC1 (MOSI/INT1/ EXT_PROT)

GND

PC0

(INT0/ICP0/XTAL)

RESET

ATmega4HVD/8HVD

8052B–AVR–09/08

1.1 Pin Descriptions

1.1.1 VFET

1.1.2 VCC

1.1.3 VREG

1.1.4 GND

1.1.5 Port B (PB2:PB0)

ATmega4HVD/8HVD

Input to the internal voltage regulator.

Pin for connection of external decoupling capaci tor. VCC is internally connected t o the voltage regulator output VREG.

Output from the internal voltage regulator . Int er n ally co nnected to VCC.

Ground

Port B is a low-voltage 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

1.1.6 Port C (PC1:PC0)

1.1.7 OC

1.1.8 OD

1.1.9 NI

1.1.10 PV1

1.1.11 BATT

1.1.12 RESET

/dw

Port B also serves the functions of various special features of the ATmega4HVD/8HVD.

Port C is a High-voltage open-drain 2 bit bi-directional I/O port. Port C also serves the functions of various special features of the ATmega4HVD/8HVD.

High voltage output to drive Charge FET (optional).

High voltage output to drive Discharge FET.

Negative input from the battery protection resistor.

Input from battery cell to ADC.

Input for detecting when a charger is connected.

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Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE communication pin.

2. Overview

PORTC (2)

SRAMFlash

CPU

EEPROM

GND

OC OD

FET

Control

Voltage

ADC

Voltage

Reference

GND

VCC

RESET/dW

Power

Supervision

POR & RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator Circuits /

Clock

Generation

PC1:0

8/16-bit T/C1

8/16-bit T/C0

PORTB (3)

PB2:0

SPI

Voltage

Regulator

Charger

Detect

VFET VREG

BATT

PV1

DATA BUS

Battery

Protection

Security Module

Voltage Regulator Monitor Interface

PB2 (CKOUT)

Oscillator Sampling

Interface

Program

Logic

debugWIRE

PC1 (External Protection Input)

PB0 (ADC0)

The ATmega4HVD/8HVD is a monitoring and protection circuit for 1-cell Li-ion applications with focus on high security/authentication, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The External Protection Input can be used to implement other battery protection mechanisms using external components, e.g. protection against chargers with too high charge voltage can be easily implemented with a few low cost passive components. The feature set makes the ATmega4HVD/8HVD a key component in any system focusing on high security, battery protection, high system utilization and low cost.

Figure 2-1. Block Diagram

An integrated, low-dropout linear regulator that can handle input voltages as low as 2.1V, ensures that the stored energy can be fully exploited. The regulator capabilities, combined with a extremely low power consumption in the powe r saving modes, greatly enhances th e cell energy utilization compared to existing solutions.

The chip utilizes Atmel's Deep Under-voltage Recovery (DUVR) mode that supports precharging of deeply discharged battery cells without using a separate Pre-charge FET. An enhanced start-up scheme allows the chip to operate correctly even with only Discharge FET connected. This makes it possible to further reduce system cost for applications that do not require Charge Over-current protection.

The ATmega4HVD/8HVD contains a 10-bit ADC for cell voltage measurem ents. The ADC is also used to monitor the on-chip temperature. Temp erature is measured by the integrate d

ATmega4HVD/8HVD

Voltage Reference, which contains a built-in temperature sensor. ATmega4HVD/8HVD con-

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ATmega4HVD/8HVD

tains a high-voltage tolerant, open-drain IO pin that supports serial communication. Programming can be done in-system using the 4 General Purpose IO ports that support SPI programming

The MCU includes 4K/8K bytes of In-System Programmable Flash with Self-programming capabilities, 256 bytes EEPROM, 512 bytes SRAM, 32 general purpose working registers, 4 general purpose I/O lines, debug WIRE f or On- chip debug ging and SPI f or In- system Progr amming, two flexible Timer/Counters with Input Capture, internal and external interrupts, a 10-bit ADC for measuring the cell voltage and on-chip temperature, a prog rammable Watchdog Timer with wake-up capabilities, and software selectable power saving modes.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The device is manufactured using Atmel’s high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the prog ram memory to be re programmed In-Syst em, by a conventional non-volatile memory programmer or by an On-chip Boot program running on the AVR core.

The ATmega4HVD/8HVD AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip Debugger.

The ATmega4HVD/8HVD is a low-power CMOS 8-bit microcontroller based on the AVR architecture. It is part of the AVR Smart Battery family that provid es secure authenticat ion, highly accurate monitoring and autonomous protection for Lithium-ion battery cells.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples th at brief ly sho w h ow to use var ious pa rt s of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not a ll C compiler vendors inclu de bit definitions in the header files and interrupt handling in C is compiler depende nt. Ple ase confirm with the C compiler documentation for more details.

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For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instru0ctions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

6. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

Watchdog

Timer

I/O Module 2

I/O Module1

I/O Module n

6.1 Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 6-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

ATmega4HVD/8HVD

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ATmega4HVD/8HVD

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calcula tions. One of the these addr ess pointer s can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is up dated to reflect information abou t the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (be fore subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supporte d in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupt s have a separa te Interrup t Vector in t he Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector addr es s, th e hig he r th e pr ior i ty.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega4HVD/8HVD has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

6.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

6.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

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The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

6.3.1 SREG – AVR Status Register

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instru ctions, as describ ed in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Registe r File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

ITHSVNZCSREG

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithm etic or logic operation. See th e “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

ATmega4HVD/8HVD

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6.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

ATmega4HVD/8HVD

7 0 Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data m emory addre ss, ma pping them directly into the first 32 locat ions of th e us er Da ta Sp ace. Altho ugh no t be ing physic ally im plemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

6.4.1 The X-register, Y-regis ter, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3.

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6.5 Stack Pointer

Figure 6-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed disp lacement, automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrup ts ar e en abled. Th e Sta ck Pointe r mu st be set to point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with th e POP instruct ion, and it is incre mented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data spa ce in some implement ations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

6.5.1 SPH and SPL – Stack pointer High and Low Register

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000010

11111111

ATmega4HVD/8HVD

8052B–AVR–09/08

6.6 Instruction Execution Timing

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk the chip. No internal clock division is used.

Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

clk

CPU

ATmega4HVD/8HVD

, directly generated from the selected clock source for

CPU

T1 T2 T3 T4

Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an

ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 6-5. Single Cycle ALU Operation

6.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These inte rrupts and the sepa rate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 51. The list also determines the priority levels of the different interrupt s. The lower the addr ess the higher is the priority level. RESET has the highest priority.

8052B–AVR–09/08

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrup t is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrup t routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be use d to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

ATmega4HVD/8HVD

8052B–AVR–09/08

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

6.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the progr am vector address for th e actual interrupt hand ling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

ATmega4HVD/8HVD

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

8052B–AVR–09/08

7. AVR Memories

7.1 Overview

This section describes the different memories in the ATmega4HVD/8HVD. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega4HVD/8HVD features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega4HVD/8HVD contains 4/8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 2K/4K x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega4HVD/8HVD Program Counter (PC) is 11/12 bits wide, thus addressing the 2K/4K program memory locations. ”Memory Programming” on page 129 contains a detailed descrip- tion on Flash data serial downloading.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution

Timing” on page 11.

Figure 7-1. Program Memory Map

Program Memory, organized as 2K/4K x 16 bits

0x0000

0x7FF/0xFFF

ATmega4HVD/8HVD

8052B–AVR–09/08

7.3 SRAM Data Memory

Figure 7-2 shows how the ATmega4HVD/8HVD SRAM Memory is organized.

The ATmega4HVD/8HVD is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 512 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 location s of Extended I/O memory, and the next 512 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indir ect with Post-increment. In the Re gister File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address

given by the Y- or Z-register.

ATmega4HVD/8HVD

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the ATmega4HVD/8HVD are all accessible through all these addressing modes. The Register File is described in ”G enera l Pur pose Reg ist e r File” on

page 9.

Figure 7-2. Data Memory Map

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(512 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF 0x0100

0x02FF

cycles as described in Figure 1.

CPU

8052B–AVR–09/08

Figure 1. On-chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

Address

Compute Address

Data

Address valid

7.4 EEPROM Data Memory

The ATmega4HVD/8HVD contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of Serial and Parallel data downloading to the EEPROM, see page

131 and page 131 respectively.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

Data

Memory Access Instruction

Write

Read

Next Instruction

7.5 I/O Memory

ATmega4HVD/8HVD

The write access time for the EEPROM is given in Table 7-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

The I/O space definition of the ATmega4HVD/8HVD is shown in ”Register Summary” on page

151.

All ATmega4HVD/8HVD I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked b y using the SBIS and SBIC instru c-

8052B–AVR–09/08

ATmega4HVD/8HVD

tions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When a ddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega4HVD/8HVD is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections. The ATmega4HVD/8HVD contains three General Purpose I/O Registers. These registers can

be used for storing any information, and they are par ti cular ly u se ful for sto rin g global var i ables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.6 Register Description

7.6.1 EEARL – The EEPROM Address Register

Bit 76543210

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X

• Bits 7:0 – EEAR7:0: EEPROM Address

The EEPROM Address Registers – EEARL specify the EEPROM address in the 256 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255. The initial value of EEARL is undefined. A proper value must be written before the EEPROM may be accessed.

7.6.2 EEDR – The EEPROM Data Register

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEARL.

8052B–AVR–09/08

7.6.3 EECR – The EEPROM Control Register

Bit 76543210

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATmega4HVD/8HVD and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programm ing tim e s fo r th e d iff er en t m o de s ar e shown in Table 7-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 7-1. EEPROM Mode Bits

EEPM1 EEPM0

0 0 3.4 ms

Typ Programming Time,

= 4.0 MHz Operation

OSC

Erase and Write in one operation

(Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Write Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardwar e clears the bit t o zero aft er four clock cycle s. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Write Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential) :

1. Wait until EEPE becomes zero.

2. Write new EEPROM address to EEARL (optional).

3. Write new EEPROM data to EEDR (optional).

ATmega4HVD/8HVD

8052B–AVR–09/08

ATmega4HVD/8HVD

4. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

5. Within four clock cycles after setting EEMPE, write a logical one to EEPE. Caution:

An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will timeout. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEARL or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

Note that a BLOD reset will abort any ongoing write operation and invalidate the result.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEARL Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEARL Register.

The Calibrated Fast RC Oscillator is used to time the EEPROM access and the programing time will therefore depend on the calibrated oscillator frequency. Table 7-2 lists the typical programming time for EEPROM access from the CPU.

Table 7-2. EEPROM Programming Time

Symbol

EEPROM write (from CPU)

Number of Calibrated RC

Oscillator Cycles

13 600 3.4 ms

Typ Programming Time,

= 4.0 MHz

OSC

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

8052B–AVR–09/08

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r17) in address register

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEARL = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

ATmega4HVD/8HVD

8052B–AVR–09/08

ATmega4HVD/8HVD

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no in terrupts will occur during execu tion of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEARL = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

7.6.4 GPIOR2 – General Purpose I/O Register 2

Bit 76543210

MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

7.6.5 GPIOR1 – General Purpose I/O Register 1

Bit 76543210

MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

7.6.6 GPIOR0 –General Purpose I/O Register 0

Bit 76543210

MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

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8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the

clocks need not be active at a given time. In order to reduce power co nsum pt ion, th e cl ocks to modules not being used can be halted by using di fferent sleep modes, as described in ”Power

Management and Sleep Modes” on page 32. The clock systems are detailed below.

Figure 8-1. Clock Distribution

8.1.1 CPU Clock – clk

CPU

Oscillator Sampling

Interface

Slow RC

Oscillator

CPU

CORE

Watchdog Timer Battery Protection Reset Logic

Ultra Low Power

RC Oscillator

RAM

clk

CPU

FLASH and

EEPROM

clk

FLASH

ADC Prescaler

AVR

Clock Control

System Clock

Prescaler

Fast RC

Oscillator

clk

Voltage

ADC

VADC

Other I/O

Modules

clk

I/O

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

8.1.2 I/O Clock – clk

I/O

8.1.3 F lash Clock – clk

8.1.4 ADC Clock – clk

ATmega4HVD/8HVD

The I/O clock is used by the majority of the I/O modules. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

ADC

The ADC is provided with a dedicated clock domain. The ADC is automatically prescaled according to the System Clock Prescaler's setting to provide a fixed clock frequency to the

8052B–AVR–09/08

ADC. The dedicated ADC clock allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion resu lts.

8.1.5 Watchdog Timer and Battery Protection Clock

The Watchdog Timer and Current Protectio n are pr ovide d with a dedicat ed clock doma in. T his allows operation in all modes except Power-off. It also allows low power operation by utilizing a Ultra Low Power Oscillator dedicated to this purpose.

8.2 Clock Sources

The following section describe the clock sources available in the device. The clocks are input to the AVR clock generator, and routed to the appropriate modules.

8.3 Calibrated Fast RC Oscillator

The calibrated Fast RC Oscillator by default provides a 8.0 MHz clock to the system clock prescaler. The frequency is nominal value at 85 components. With an accurate time reference and by using runtime calibration, this oscillator can be calibrated to an accuracy of ± 1% over the entire temperature range. During reset, hardware loads the calibration byte into the FOSCCAL Re gister and ther eby automatica lly calibrates the Fast RC Oscillator. At 85 oscillator can be calibrated to any frequency in the range 7.3- 8.1 MHz by changing the FOSCCAL register. For more information on the pre-programmed calibration value, see the section

”Reading the Signature Row from Software” on page 124. Note that the frequency of the sys-

tem clock is given by the ”System Clock Prescaler” on page 25.

ATmega4HVD/8HVD

°C. This clock will operate with no external

°C, this calibration gives a frequency of 8 MHz ± 4%. The

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-1 on page 23.

Table 8-1. Start-up times for the calibrated Fast RC Oscillator clock selection

Start-up Time from

SUT3..0

000 6 CK 14 CK + 4 ms 001 6 CK 14 CK + 8 ms 010 6 CK 14 CK + 16 ms 011 6 CK 14 CK + 32 ms 100 6 CK 14 CK + 64 ms 101 6 CK 14 CK + 128 ms 110 6 CK 14 CK + 256 ms

(1)

111

Notes: 1. The device is shipped with this option selected.

2. The actual value of the added, selectable 4- 512 ms delay depends on the actual frequency of the ”Ultra Low Power RC Oscillator” on page 24. See Table 8-2 on pag e 25 and ”Electri-

cal Characteristics” on page 142

Power-save Additional Delay from Reset, Typical Values

6 CK 14 CK + 512 ms

(2)

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8.4 Slow RC Oscillator

Clock period

Slow RC Word

1024

-------------------------------------- -

(1-Slow RC Temp Pred iction TT

HOT

–())⋅=

The Slow RC Oscillator provides a 131 kHz clock (typical value, refer to section "Electrical Characteristics" on page 164 for details). This clock can be used as a timing ref erence for ru ntime calibration of the Fast RC Oscillator and for accurately determining the actual ULP Oscillator frequency, refer to ”OSI – Oscillator Sampling Interface” on page 27 for details.

To provide good accuracy when used as a timing reference, the Slow RC Oscillator has calibration bytes stored in the signature address space, refer to section ”Reading the Signature

Row from Software” on page 124 for details. The actual clock period of the Slow RC Oscillator

in μs as a function of temperature is given by:

where T is the die temperature in Kelvin and T signature row. The die temperature can be found using the ADC, refer to ”ADC - Analog-to-

Digital Converter” on page 90 for details.

8.5 Ultra Low Power RC Oscillator

The Ultra Low Power RC Oscillator (ULP Oscillator) provides a 128 kHz clock (typical value, refer to section ”Electrical Characteristics” on page 142). There are two alternative methods for determining the actual clock period of the ULP Oscillator:

1. To determine the actual clock period as a function of die temperature, the Oscillator Sampling Interface should be used. Refer to section ”OSI – Oscillator Sampling Inter-

face” on page 27 for details.

2. To determine a fixed value for the actual clock period independent of the die temperature, for example to determine the best setting of the Battery Protection timing, use the calibration byte ULP_RC_FRQ stored in the signature address space, refer to section

”Reading the Signature Row from Software” on page 124 for details.

8.6 CPU, I/O, Flash, and ADC Clock

The clock source for the CPU, I/O, Flash, and ADC is the calibrated Fast RC Oscillator.

8.7 Watchdog Timer and Battery Protection

The clock source for the Watchdog Timer and Battery Protection is the Ultra Low Power RC Oscillator. The Oscillator is automatically enabled in all operational modes. It is also enabled during reset.

is the calibration temperature stored in the

HOT

8.8 Clock Startup Sequence

When the CPU wakes up from Power-save, the CPU clock source is used to time the start-up, ensuring a stable clock before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the voltage regulator to reach a stable level before commencing normal operation. The Ultra Low Power RC Oscillator is used for timing this real-time part of the start-up time. Start-up times are determined by the SUT Fuses as shown in Table

ATmega4HVD/8HVD

8052B–AVR–09/08

8.9 Clock Output

ATmega4HVD/8HVD

8-1 on page 23. The number of Ultra Low Power RC Oscillator cycles used for each time-out is

shown in Table 8-2.

Table 8-2. Number of Ultra Low Power RC Oscillator Cycles

Typ Time-out

4 ms 512

8 ms 1K 16 ms 2K 32 ms 4K 64 ms 8K

128 ms 16K 256 ms 32K 512 ms 64K

Note: 1. The actual value depends on the actual clock period of the Ultra Low Power RC Oscillator,

refer to ”Ultra Low Power RC Oscillator” on page 24 for details.

(1)

Number of Cycles

The CPU clock divided by 2 can be output to the PB2 pin. The CPU can enable the clock output function by setting the CKOE bit in the MCU Control Register. The clock will not run in any sleep modes.

8.10 System Clock Prescaler

The ATmega4HVD/8HVD has a System Clock Prescaler, used to prescale the Calibrated Fast RC Oscillator. The system clock can be divided by setting the ”CLKPR – Clock Prescale Reg-

ister” on page 29, and this enables the user to decrease or increase the system clock

frequency as the requirement for power consumption and processing power changes. This system clock will affect the clock frequency of the CPU and all synchronous peripherals. clk clk

and clk

CPU

When switching between prescaler settings, the System Clock Prescaler ensures th at no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the prev ious setting, nor the clock f requency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, may be faster than the CPU's clock frequency. It is not possible to determine the state of the prescaler, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period correspondin g to the new prescaler setting.

are divided by a factor as shown in Table 8-4 on page 30.

FLASH

I/O

8052B–AVR–09/08

To avoid unintentional changes of clock frequency, a special write procedur e must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting t o make sure the wr ite procedu re is not interrupted.

8.11 ADC Clock Prescaler

The ADC clock will be automatically prescaled relative to the System Clock Prescaler settings, see ”System Clock Prescaler” on page 25. Depending on the Clock Prescale Select bits, CLKPS1..0, the ADC clock, clk

page 26.

, will be prescaled by 24, 12 or 6 as shown in Table 8-3 on

ADC

Table 8-3. ADC Clock Prescaling

CLKPS1 CLKPS0 ADC Division Factor

00Reserved 0124 1012 116

Note: 1. When changing Prescaler value, the ADC Prescaler will automatically change frequency of

the ADC. The result of the ongoing conversion will be invalid.

(1)

ATmega4HVD/8HVD

8052B–AVR–09/08

8.12 OSI – Oscillator Sampling Interface

osi_posedge

Databus

Ultra Low

Power RC

Oscillator

Slow RC

Oscillator

OSCILLATOR SELECT

7 bit prescaler

Edge

Detector

OSISEL0

OSICSR

Fast RC

Oscillator

(1)

8.12.1 Features

Runtime selectable oscillator input (Slow RC or ULP RC Oscillator)

•

• 7 bit prescaling of the selected oscillator

• Software read access to the phase of the prescaled clock

• Input capture trigger source for Timer/Counter0

8.12.2 Overview

The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low Power RC (ULP) oscillators in ATmega4HVD/8HVD. OSI can be used to calibrate the Fast RC Oscillator runtime with high accuracy. OSI can also provide an accurate reference for compensating the ULP Oscillator frequency drift.

The prescaled oscillator phase can be continuously read by the CPU through the OSICSR register. In addition, the input capture function of Timer /Counter0 can be set up to tr igger on the rising edge of the prescaled clock. This enables accurate measurements of the oscillator frequencies relative to the Fast RC Oscillator.

A simplified block diagram of the Oscillator Sampling Interface is shown in Figure 8-2.

ATmega4HVD/8HVD

8052B–AVR–09/08

Figure 8-2. Oscillator Sampling Interfac e Bloc k Diagram.

Note: 1. One prescaled Slow RC/ULP oscillator period corresponds to 128 times the actual Slow

RC/ULP oscillator period.

The osi_posedge signal pulses on each rising edge of the prescaled Slow RC/ ULP oscillator clock. This signal is not directly accessible by the CPU, but can be used to trigger the input capture function of Timer/Counter0. Using OSI in combination with the input capture function of Timer/Counter0 facilitates accurate measurement of the oscillator frequencies with a minimum of CPU calculation. Refer to ”Timer/Counter(T/C0,T/C1)” on page 74 for details on how to enable the Input Capture function.

8.12.3 Usage

FastRCTSlowRC

128 n⋅

number of CPU cycles in n prescaled Slow RC periods

------------------------------------------------------------------------------------------------------------------------------------------------ -

⋅=

ULPRCTSlowRC

number of CPU cycles in n prescaled ULP RC periods number of CPU cycles in n prescaled Slow RC periods

------------------------------------------------------------------------------------------------------------------------------------------------ -

⋅=

The Slow RC oscillator represents a highly predictable and accurate clock source over the entire temperature range and provides an excellen t refe rence for calibratin g the Fa st RC o scillator runtime. Typically, runtime calibration is needed to provide an accurate Fast RC frequency for asynchronous serial communication in the complete temperature range.

The Slow RC frequency at 70°C and the Slow RC temperature coefficient are st ored in the signature row. These characteristics can be used to calculate the actual Slow RC clock period at a given temperature with high precision. Refer to ”Slow RC Oscillator” on page 24 for details.

By measuring the number of CPU cycles of one or more prescaled Slow RC clock periods, t he actual Fast RC oscillator clock period can be determined. The Fast RC clock period can then be adjusted by writing to the FOSCCAL register. The new Fast RC clock period after calibration should be verified by repeating the measurement and repeating the calibration if necessary. The Fast RC clock period as a functi on of the Slow RC clock period is given by:

where n is the number of prescaled Slow RC periods that is used in the measurement. Using more prescaled Slow RC periods decreases the measurement error, but in creases the time consumed for calibration. Note that the Slow RC Oscillator needs very short time to stabilize after being enabled by the OSI module. Hence, the calibration algorithm may use the time between the first and second osi_posedge as time reference for calculations.

Another usage of OSI is determining the ULP frequency accurately. The ULP frequency at 70°C and the ULP temperature coefficient are stored in the signature row, allowing the ULP frequency to be calculated directly. However, the ULP frequency is less predictable over temperature than the Slow RC oscillator frequency, therefore a more accurate result can be obtained by calculating the ratio between the Slow RC and ULP oscillators. This is done by sampling both the ULP and Slow RC oscillators and comparing the results. When the ratio is known, the actual ULP frequency can be determined with high accuracy. The ULP RC clock period as a function of the Slow RC clock period is given by:

where n is the number of prescaled ULP RC and Slow RC periods that is used in the measurement. Using more prescaled ULP RC and Slow RC periods decreases t he measurement er ror, but increases the time consumed for calibration. Note that th e FOSCCAL register must be kept at a constant value during this operation to ensure accurate results.

These clock period calculations should be performed again when there is a significant change in die temperature since the previous calculation. The die temperature can be found using the ADC, refer to section TBD for details.

ATmega4HVD/8HVD

8052B–AVR–09/08

8.13 Register Description

8.13.1 FOSCCAL – Fast RC Oscillator Calibration Register

Bit 76543210

FCAL7 FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0 FOSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Device Specific Calibration Value

• Bits 7:0 – FCAL7:0: Fast RC Oscillator Calibration Value

The Fast RC Oscillator Calibration Register is used to trim the Fast RC Oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 85 application software can write this register to change the oscillator frequency. The oscillator can be run-time calibrated to any frequency in the range 7.3-8.1 MHz. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.1 MHz. Otherwise, the EEPROM or Flash write may fail.

ATmega4HVD/8HVD

°C. The

The FCAL[7:5] bits determine the range of operation for the oscillator. Setting these bits to 0b000 gives the lowest frequency range, setting this bit to 0b111 gives the highest frequency range. The frequency ranges are overlapping. A setting of for instance FOSCCAL = 0x1F gives a higher frequency than FOSCCAL = 0x20.

The FCAL[4:0] bits are used to tune the frequency within the selected r ang e. A sett ing of 0x00 gives the lowest frequency in that range, and a setting of 0x1F gives the highest frequency in the range. Incrementing FCAL[4:0] by 1 will give a frequency increment of less than 1.5 % in the frequency range 7.3-8.1 MHz. With an accurate time refere nce, an oscillator accuracy of ±1% can be achieved after calibration. The frequency will drift with temperature, so run-time calibration will be required to maintain the accuracy. Refer to ”OSI – Oscillator Sampling Inter-

face” on page 27 for details.

8.13.2 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0

Read/Write R R R/W R/W R R R R Initial Value 0 0 0 0 0 0 0 0

• Bit 5 – CKOE: Clock Output

When this bit is written to one, the CPU clock divided by 2 is output on the PB2 pin.

8.13.3 CLKPR – Clock Prescale Register

-– – CKOE PUD – – – – MCUCR

8052B–AVR–09/08

Bit 7 65432 1 0

CLKPCE

Read/Write R/W R R R R R R/W R/W Initial Value0 00000 1 1

– – – – – CLKPS1 CLKPS0 CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, or clear the CLKPCE bit.

• Bit 1:0 – CLKPS1:0: Clock Prescaler Select Bit 1..0

These bits define the division factor betwe en the selected clock sour ce and the internal sys tem clock. These bits can be written run-tim e to vary th e clo ck frequen cy to suit the ap plication requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division facto rs are given in Table 8-4 on page 30. Note that writing to the System Cloc k Prescaler Sele ct bits will abort any ongoing ADC conversion.

Table 8-4. System Clock Prescaler Select

CLKPS1 CLKPS0 Clock Division Factor

00Reserved 012 104 118

(1)

Note: 1. Reserved values should not be written to CLKPS1..0

8.13.4 OSICSR – Oscillator Sampling Interface Control and Status Register

Bit 76543210

– – – OSISEL0 – – OSIST OSIEN OSICSR

Read/Write R R R R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7:5,3:2 – RES: Reserved bits

These bits are reserved bits in the ATmega4HVD/8HVD and will always read as zero.

• Bit 4 - OSISEL0: Oscillator Sampling Interface Select 0

Table 8-5. OSISEL Bit Description

OSISEL0 Oscillator source

0 ULP Oscillator 1 Slow RC Oscillator

• Bit 1 – OSIST: Osci llator Sampling Interface Status

This bit continuously displays the phase of the prescaled clock. This bit can be polled by the CPU to determine the rising and falling edges of the prescaled clock.

ATmega4HVD/8HVD

8052B–AVR–09/08

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