• High Performance, Low Power AVR ® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
– 16/32/64K Bytes Flash of In-System Programmable Program Memory
– 512B/1K/2K Bytes of In-System Programmable EEPROM
– 1/2/4K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data Retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)
• CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified
• LIN 2.1 and 1.3 Controller or 8-Bit UART
• One 12-bit High Speed PSC (Power Stage Controller)
– Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
– Variable PWM duty Cycle and Frequency
– Synchronous Update of all PWM Registers
– Auto Stop Function for Emergency Event
• Peripheral Features
– One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode
and Capture Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– One Master/Slave SPI Serial Interface
– 10-bit ADC
Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs
Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels
Internal Reference Voltage
Direct Power Supply Voltage Measurement
– 10-bit DAC for Variable Voltage Reference (Comparators, ADC)
– Four Analog Comparators with Variable Threshold Detection
– 100µA ±2% Current Source (LIN Node Identification)
– Interrupt and Wake-up on Pin Change
– Programmable Watchdog Timer with Separate On-Chip Oscillator
– On-chipTemperature Sensor
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– In-System Programmable via SPI Port
– High Precision Crystal Oscillator for CAN Operations (16 MHz)
– Internal Calibrated RC Oscillator ( 8 MHz)
– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)
• Operating Voltage: 2.7V - 5.5V
• Extended Operating Temperature:
– -40°C to +85°C
• Core Speed Grade:
– 0 - 8MHz @ 2.7 - 4.5V
– 0 - 16MHz @ 4.5 - 5.5V
Note:1. See “Data Retention” on page 9 for details.
2. On the engineering samples, the ACMPN3 alternate function is not located on PC4. It is
located on PE2.
The ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega16M1/32M1/64M1 achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
8209A–AVR–08/09
5
2.1Block Diagram
Flash Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
4 Analog
Comparators
DAC
ADC
MPSC
Timer 1
Timer 0
HW LIN/UART
CAN
Current Source
ATmega16M1/32M1/64M1
Figure 2-1.Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega16M1/32M1/64M1 provides the following features: 16/32/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM,
1/2/4K bytes SRAM, 27 general purpose I/O lines, 32 general p urpose working registers, one
Motor Power Stage Controller, two flexible Timer/Counters with compare modes and PWM, one
UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator,
an SPI serial port, an On-chip Debug system and four software selectable power saving modes.
8209A–AVR–08/09
6
ATmega16M1/32M1/64M1
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN,
LIN/UART and interrupt system to continue functioning. The Power -down mo de saves the r egister contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except
ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega16M1/32M1/64M1 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control app lications.
The ATmega16M1/32M1/64M1 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
2.2Pin Descriptions
2.2.1VCC
Digital supply voltage.
2.2.2GND
Ground.
2.2.3Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port B also serves the functions of v ari ous s pecia l feat ures of th e ATme ga16 M1/ 32M1/ 64M 1 as
listed on page 72.
2.2.4Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
8209A–AVR–08/09
Port C also serves the functions of special features of the ATmega16M1/32M1/64M1 as listed
on page 75.
7
2.2.5Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16M1/32M1/64M1 as
listed on page 79.
ATmega16M1/32M1/64M1
2.2.6Port E (PE2..0) RESET/
XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port E.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in “System and Reset Characteristics” on page 313. Shorter
pulses are not guaranteed to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock oper ating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
The various special features of Port E are elaborated in “Alternate Functions of Port E” on page
82 and “Clock Systems and their Distribution” on page 27.
XTAL1/
2.2.7AVCC
2.2.8AREF
8209A–AVR–08/09
AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should
be externally connected to V
be connected to V
through a low-pass filter.
CC
, even if the ADC, DAC are not used. If the ADC is used, it should
CC
This is the analog reference pin for the A/D Converter.
8
3.Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.
4.Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
5.About Code Examples
This documentation contains simple code examples tha t briefly sh ow how to use var ious par ts of
the device. Be aware that not all C compiler vendors include bit def initions in the header files
and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumentation for more details.
These code examples assume that the part spe cific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBI C", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
ATmega16M1/32M1/64M1
6.Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
8209A–AVR–08/09
9
7.AVR CPU Core
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
7.1Overview
ATmega16M1/32M1/64M1
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 7-1.Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
8209A–AVR–08/09
10
ATmega16M1/32M1/64M1
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointe rs
can also be used as an address pointe r for look up tables in Flash pr ogram memory. Thes e
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM (Store Program Memory) instruction that writes into the Applicatio n Flash
memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher is the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega16M1/32M1/64M1 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
7.2ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
7.3Status Register
The Status Register contains information abou t th e result o f th e most r ecently exe cuted arith metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
8209A–AVR–08/09
11
specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be hand le d by so ftware.
The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
ATmega16M1/32M1/64M1
ITHSVNZCSREG
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the negative flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
8209A–AVR–08/09
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
12
7.4General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In or der to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7-2.AVR CPU General Purpose Working Registers
…
R260x1AX-register Low Byte
R270x1BX-register High Byte
R280x1CY-register Low Byte
R290x1DY-register High Byte
R300x1EZ-register Low Byte
R310x1FZ-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
7.4.1The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 7-3.
8209A–AVR–08/09
13
7.5Stack Pointer
ATmega16M1/32M1/64M1
Figure 7-3.The X-, Y-, and Z-registers
15XHXL0
X-register7070
R27 (0x1B)R26 (0x1A)
15YHYL0
Y-register7070
R29 (0x1D)R28 (0x1C)
15ZHZL0
Z-register7070
R31 (0x1F)R30 (0x1E)
In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement ,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. Note that the Stack is implemented as
growing from higher to lower memory locations. The Stack Pointer Register always points to the
top of the Stack. The Stack Pointer points to the data SRAM Stack area wh ere the Subroutine
and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls ar e
executed or interrupts are enabled. Initial Stack Pointer value equa ls the last address of the
internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure
8-2 on page 19.
See Table 7-1 for Stack Pointer details.
Table 7-1.Stack Pointer instructions
InstructionStack pointerDescription
PUSHDecremented by 1Data is pushed onto the stack
CALL
ICALL
RCALL
POPIncremented by 1Data is popped from the stack
RET
RETI
Decremented by 2
Incremented by 2Return address is popped from the stack with return from
Return address is pushed onto the stack with a subroutine call or
interrupt
subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
8209A–AVR–08/09
14
ATmega16M1/32M1/64M1
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1T2T3T4
CPU
Total Execution Time
ALU Operation Execute
Result Write Back
T1T2T3T4
clk
CPU
7.5.1SPH and SPL – Stack Pointer High and Stack Pointer Low Register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
, directly generated from the selected clock source for the
CPU
Figure 7-4.The Parallel Instruction Fetches and Instruction Executions
Figure 7-5 shows the internal timing concept for th e Regi ster File . In a single clock cycl e an ALU
operation using two register operands is executed, and the result is stored back to the destination register.
Figure 7-5.Single Cycle ALU Operation
8209A–AVR–08/09
15
7.7Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 289 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 54. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is ANACOMP0 – the Analog Comparator
0 Interrupt. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting
the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 54 for more
information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-
Programming” on page 272.
7.7.1Interrupt Behavior
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
ATmega16M1/32M1/64M1
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts , the Program Cou nter is vectored t o the actual In terrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corres ponding interrup t enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt rou tine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to a void interrupts during the
timed EEPROM write sequence.
8209A–AVR–08/09
16
ATmega16M1/32M1/64M1
Assembly Code Example
in r16, SREG; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE; start EEPROM write
sbi EECR, EEWE
out SREG, r16; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /*enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
7.7.2Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector addre ss fo r t he actua l interr up t ha nd ling rout ine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in ad dition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
8209A–AVR–08/09
17
ATmega16M1/32M1/64M1
F
8.Memories
8.1Overview
This section describes the different memories in the ATmega16M1/32M1/64M1. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega16M1/32M1/64M1 features an EEPROM Memory for data storage. All
three memory spaces are linear and regular.
8.2In-System Reprogrammable Flash Program Memory
The ATmega16M1/32M1/64M1 contains 16/32/64K bytes On-chip In-System Reprogrammable
Flash memory for program storage . Since all AVR instructio ns are 16 or 32 bits wide, the Flas h
is organized as 16K x 16 / 32K x 16. For software security, the Flash Program memory space is
divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega16M1/32M1/64M1 Program Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits
for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-
Programming” on page 272. “Memory Programming” on page 289 contains a detailed descrip-
tion on Flash programming in SPI or Parallel programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory.
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 15.
Figure 8-1.Program Memory Map
Program Memory
0x0000
Application Flash Section
8209A–AVR–08/09
Boot Flash Section
0x1FFF/0x3FFF/0x7FF
18
8.3SRAM Data Memory
32 Registers
64 I/O Registers
Internal SRAM
(1024/2048/4096 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x04FF/0x08FF/0x10FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
Figure 8-2 shows how the ATmega16M1/32M1/64M1 SRAM Memory is organized.
The ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can
be supported within the 64 locations reserved in the Opcode for th e IN and OUT instr uctions. For
the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 2304 data memory locations address both the Reg ister File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 1/2/4K locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations f rom the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
ATmega16M1/32M1/64M1
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 1/2/4K bytes of internal data SRAM in the ATmega16M1 /32M1/64M1 are all accessible
through all these addressing modes. The Register File is described in “General Purpose Regis-
ter File” on page 13.
Figure 8-2.Data Memory Map1/2/4K
8.3.1SRAM Data Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
cycles as described in Figure 8-3.
CPU
8209A–AVR–08/09
19
Figure 8-3.On-chip Data SRAM Access Cycles
clk
WR
RD
Data
Data
Address
Address valid
T1T2T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
8.4EEPROM Data Memory
The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory. It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the
EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
ATmega16M1/32M1/64M1
For a detailed description of SPI and Parallel data downloading to the EEPROM, see “Serial
Downloading” on page 305 , and “Parallel Programming Parameters, Pin Mapping, and Commands” on page 294 respectively.
8.4.1EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-2. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contain s instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC
period of time to run at a voltage lower than specif ied as mi nimum for the clock fre quen cy used .
See “Preventing EEPROM Corruption” on page 21.for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
is likely to rise or fall slowly on power-up/down. This causes the device for some
8209A–AVR–08/09
20
8.4.2Preventing EEPROM Corruption
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues a re the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an exter nal low V
be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
8.5I/O Memory
The I/O space definition of the ATmega16M1/32M1/64M1 is shown in “Register Summary” on
page 322.
All ATmega16M1/32M1/64M1 I/O s and peripherals are placed in t he I /O sp ace. All I/O locations
may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between
the 32 general purpose working registers and the I/O space. I/O registers within the address
range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set section for more details. When using the I/O specific commands IN and OUT,
the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space
using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega16M1/32M1/64M1
the EEPROM data can be corrupted because the supply voltage is
CC,
reset Protection circuit can
CC
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to th em. Note that, u nlike most other
AVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be
used on registers containing such status flags. The CBI and SBI instructions work with registers
0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
8.6General Purpose I/O Registers
The ATmega16M1/32M1/64M1 contains four General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global variables and status flags. See “Register Description” on page 22 for details.
The General Purpose I/O Registers, within the address range 0x00 - 0x1F, are directly bitaccessible using the SBI, CBI, SBIS, and SBIC instructions.
8209A–AVR–08/09
21
8.7Register Description
8.7.1EEARH and EEARL – The EEPROM Address Registers
Bit1514131211 10 9 8
–––––-EEAR9EEAR8EEARH
EEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0EEARL
76543 2 10
Read/WriteRRRRRR/WR/WR/W
R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value0000000X
XXXXX X XX
• Bits 15:10 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 9:0 – EEAR[8:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512B/1K/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0
and 1023. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
For the EEPROM write operation, the EEDR Register contains the data to b e written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEWE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 8-1. While
8209A–AVR–08/09
22
ATmega16M1/32M1/64M1
EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to
0b00 unless the EEPROM is busy programming.
Table 8-1.EEPROM Mode Bits
Programming
EEPM1EEPM0
003.4 msErase and Write in one operation (Atomic Operation)
011.8 msErase Only
101.8 msWrite Only
11–Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. The interrupt will not be generated during EEPROM write or SPM.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
TimeOperation
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value in to the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1.Wait until EEWE becomes zero.
2.Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Control and Status Register) becomes zero.
3.Write new EEPROM address to EEAR (optional).
4.Write new EEPROM data to EEDR (optional).
5.Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the
Flash. If the Flash is never bein g up da te d by th e CPU, step 2 can be omitted. See “Boot Loader
Support – Read-While-Write Self-Programming” on page 272 for details about Boot
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
8209A–AVR–08/09
23
ATmega16M1/32M1/64M1
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero bef ore wr iting th e next byte. Whe n EEWE has b een set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Registe r, the EERE b it must be writte n to a log ic one t o trigger t he
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 8-2 lists the typica l programming time for EEPROM access from the CPU.
Table 8-2.EEPROM Programming Time.
SymbolNumber of Calibrated RC Oscillator CyclesTyp Programming Time
EEPROM write
(from CPU)
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also
assume that no Flash Boot Loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.
263683.3 ms
8209A–AVR–08/09
24
ATmega16M1/32M1/64M1
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write (unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
8209A–AVR–08/09
25
ATmega16M1/32M1/64M1
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to unused
modules can be halted by using different slee p modes, as described in “Power Man agement and
Sleep Modes” on page 38. The clock systems are detailed below.
Figure 9-1.Clock Distribution
ATmega16M1/32M1/64M1
9.1.1CPU Clock – clk
9.1.2I/O Clock – clk
9.1.3Flash Clock – clk
8209A–AVR–08/09
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
I/O
The I/O clock is used by the majority of the I/O modules, like Timer /Counters, SPI, UART. The
I/O clock is also used by the External Interrupt module, but note that some external interrupts
are detected by asynchronous logic, allowing such interru pts t o be det ected even if the I/ O clock
is halted.
FLASH
The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.
27
ATmega16M1/32M1/64M1
9.1.4PLL Clock – clk
9.1.5ADC Clock – clk
9.2Clock Sources
PLL
The PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock. A 16
MHz clock is also derived for the CPU.
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as illustrated
Table 9-1. The clock from the selected source is input to the AVR clock generator, and routed to
the appropriate modules.
Table 9-1.Device Clocking Options Select
Device Clocking OptionSystem
External Crystal/Ceramic ResonatorExt OscRC Osc1111 - 1000
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
PLL output divided by 4 : 16 MHzPLL / 4RC Osc0011
Calibrated Internal RC OscillatorRC OscRC Osc0010
PLL output divided by 4 : 16 MHz / PLL driven by External
clock
External ClockExt ClkRC Osc0000
Note:1. For all fuses “1” means unprogrammed while “0” means programmed.
2. Ext Osc : External Osc
3. RC Osc : Internal RC Oscillator
4. Ext Clk : External Clock Input
PLL / 4Ext Clk0001
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before starting
normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up
time. The number of WDT Oscillator cycles used for each time-out is shown in Table 9-2. The
frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.
8209A–AVR–08/09
28
Table 9-2.Number of Watchdog Oscillator Cycles
XTAL2
XTAL1
GND
C2
C1
Typ Time-o ut (VCC = 5.0V)Typ Time-out (VCC = 3.0V)Number of Cycles
4.1 ms4.3 ms4K (4,096)
65 ms69 ms64K (65,536)
9.3Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “ 10”, and CKDIV8 programmed. The default
clock source setting is the Internal RC Oscillator with longest start-up time and an initial system
clock prescaling of 8. This defa ult setting ensure s that all users ca n make their des ired clock
source setting using an In-System or Parallel programmer.
9.4Low Power Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 9-2. Either a quartz crystal or a
ceramic resonator may be used.
This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs.
ATmega16M1/32M1/64M1
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for
use with crystals are given in Table 9-3. For ceramic resonators, the capacitor values given by
the manufacturer should be used. For more information on how to choose capacitors and other
details on Oscillator operation, refer to the Multi-purpose Oscillator Application Note.
Figure 9-2.Crystal Oscillator Connections
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 9-3.
Notes:1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table
9-4.
Table 9-4.Start-up Times for the Oscillator Clock Selection
Start-up Time from
Power-down and
CKSEL0SUT1..0
000258 CK
001258 CK
0101K CK
0111K CK
Power-save
(1)
(1)
(2)
(2)
Additional Delay
from Reset
(VCC = 5.0V)Recommended Usage
14CK + 4.1 ms
14CK + 65 ms
14CK
14CK + 4.1 ms
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Ceramic resonator, BOD
enabled
Ceramic resonator, fast
rising power
8209A–AVR–08/09
1001K CK
(2)
14CK + 65 ms
10116K CK14CK
11016K CK14CK + 4.1 ms
11116K CK14CK + 65 ms
Ceramic resonator, slowly
rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator, slowly
rising power
Notes:1. These options should only be used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.
30
9.5Calibrated Internal RC Oscillator
By default, the Internal RC OScillator provides an approximate 8.0 MHz clock. Though voltage
and temperature dependent, this clock can be very accurately ca librated by the use r. The device
is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 34 for
more details.
This clock may be selected as the system cloc k by p rogr am m in g th e CKS E L Fus es a s sh own in
Table 9-1. If selected, it will operate with no external components. During reset, hardware loads
the pre-programmed calibration value into th e OSCCAL Re giste r a nd the reby aut omat ica lly calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in
Table 29-1 on page 312.
By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on
page 35, it is possible to get a higher calibration accuracy than by using the factory calibration.
The accuracy of this calibration is shown as User calibration in “Clock Characteristics” on page
312.
When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the
Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section .
Notes:1. The device is shipped with this option selected.
2. If 8 MHz frequency exceeds the specification of the device (depends on V
Fuse can be programmed in order to divide the internal frequency by 8.
(1)(2)
), the CKDIV8
CC
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 9-6 on page 31.
Table 9-6.Start-up times for the internal calibrated RC Oscillator clock selection
Start-up Time from Power-
Power Conditions
BOD enabled6 CK14CK
Fast rising power6 CK14CK + 4.1 ms01
Slowly rising power6 CK14CK + 65 ms
Notes:1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1 ms to ensure programming mode can be entered.
2.
The device is shipped with this option selected.
down and Power-save
Reserved11
Additional Delay from
Reset (VCC = 5.0V)SUT1..0
(1)
(2)
00
10
8209A–AVR–08/09
31
9.6PLL
9.6.1Internal PLL
ATmega16M1/32M1/64M1
The internal PLL in ATmega16M1/32M1/64M1 gener ates a clock frequency that is 64x multiplied
from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal
RC Oscillator which is divided down to 1 MHz. See the Figure 9-3 on page 33.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register
will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC
Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency saturates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be
noted that the PLL in this case is not locked any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1
MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only
when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is
set when PLL is locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep
modes
.
Table 9-7.Start-up Times when the PLL is selected as system clock
CKSEL
3..0SUT1..0
001K CK14CK
0011
RC Osc
0101
Ext Osc
0001
Ext Clk
Note:1. This value do not provide a proper restart ; do not use PD in this clock scheme
011K CK14CK + 4 ms
101K CK14CK + 64 ms
1116K CK14CK
001K CK14CK
011K CK14CK + 4 ms
1016K CK14CK + 4 ms
1116K CK14CK + 64 ms
006 CK
016 CK
106 CK
11Reserved
Start-up Time from Power-down
and Power-save
(1)
(1)
(1)
Additional Delay from Reset
(VCC = 5.0V)
14CK
14CK + 4 ms
14CK + 64 ms
8209A–AVR–08/09
32
Figure 9-3.PCK Clocking System
8 MHz
RC OSCILLATOR
OSCCAL
XTAL1
XTAL2
OSCILLATORS
DIVIDE
BY 8
DIVIDE
BY 2
CK
PLL
64x
PLLE
Lock
Detector
PLOCK
SOURCE
PLLF
DIVIDE
BY 4
CLK
PLL
XTAL2
XTAL1
GND
NC
External
Clock
Signal
9.7128 kHz Internal Oscillator
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
ATmega16M1/32M1/64M1
9.8External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure
9-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 9-4.External Clock Drive Configuration
Table 9-8.External Clock Frequency
CKSEL3..0Frequency Range
00000 - 16 MHz
8209A–AVR–08/09
33
ATmega16M1/32M1/64M1
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 9-9.
Table 9-9.Start-up Times for the External Clock Selection
SUT1..0
006 CK14CKBOD enabled
016 CK14CK + 4.1 msFast rising power
106 CK14CK + 65 msSlowly rising power
11Reserved
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-ti me changes of the int ernal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
34 for details.
9.9Clock Output Buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when chip clock is used to drive other circuits on the system. The clock will be output
also during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output (CKOUT Fuse programmed).
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (VCC = 5.0V)Recommended Usage
9.10System Clock Prescaler
The ATmega16M1/32M1/64M1 system clock can be divided by setting the Clock Prescale R egister – CLKPR. This feature can be used to decrease power consumption when the requirement
for processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
are divided by a factor as shown in Table 9-10.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also en sures th at no in te rme diate freq ue ncy is higher t han
neither the clock frequency corresponding to the pr eviou s sett ing, nor t he clock fr equency co rr esponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock fr equen cy. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 acti ve cl ock e dge s ar e prod uced. Her e, T1 is t he previous clock period, and T2 is the period corresponding to the new pre scaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
I/O
, clk
ADC
, clk
, and clk
CPU
FLASH
8209A–AVR–08/09
34
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure t he write procedur e is
not interrupted.
9.11Register Description
9.11.1OSCCAL – Oscillator Calibration Register
Bit76543210
CAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0OSCCAL
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
Initial ValueDevice Specific Calibration Value
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in Table 29-1 on page 312. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 29-
1 on page 312. Calibration outside that range is not guaranteed.
ATmega16M1/32M1/64M1
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6:0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that r ange, and a setting of 0x7F g ives the high est freq uency in the
range.
9.11.2PLLCSR – PLL Control and Status Register
Bit76543210
–––––PLLFPLLEPLOCKPLLCSR
Read/WriteRRRRRR/WR/WR
Initial Value0000000/10
• Bit 7:3 – Res: Reserved Bits
These bits are reserved and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
8209A–AVR–08/09
If PLLF is set, the PLL output is 64MHz.
If PLLF is clear, the PLL output is 32MHz.
• Bit 1 – PLLE: PLL Enable
35
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
for Fast Peripherals. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
PLL
9.11.3CLKPR – Clock Prescaler Register
Bit76543210
CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0CLKPR
Read/WriteR/WRRRR/WR/WR/WR/W
Initial Value0000See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to t he MCU, the speed o f all synchronous peripherals is reduced when a division factor is used. The division factors are given in
Table 9-10.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
the selcted clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the po wer consumption to the application’s requirements.
10.2Sleep Modes
Figure 9-1 on page 27 presents the different clock systems in the ATmeg a16M1/32M1/64M1,
and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 10-1
shows the different sleep modes and their wake-up sources.
Table 10-1.Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock DomainsOscillatorsWake-up Sources
CPU
clk
Sleep Mode
IdleXXX XXXXXXX
ADC Noise
Reduction
Power-downX
Standby
(1)
FLASH
clk
Notes:1. Only recommended with external crystal or resonator selected as clock source.
IO
clk
2. Only level interrupt.
ADC
clk
XXXX
PLL
clk
Main Clock
Source Enabled
XX
INT3..0
(2)
(2)
(2)
XXXX
PSC
SPM/EEPROM
Ready
ADC
X
X
WDT
OtherI/O
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See Table 10-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the register file and
SRAM are unaltered when the device wakes up from slee p. I f a r eset occurs d uri ng sle ep mode,
the MCU wakes up and executes from the Reset Vector.
10.3Idle Mode
8209A–AVR–08/09
When the SM2:0 bits are written to 000, the SLEEP instru ctio n makes the MCU enter Idle mode,
stopping the CPU but allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halt clk
clk
, while allowing the other clocks to run.
FLASH
CPU
and
Idle mode enables the MCU to wake up from external triggered interrupts as well a s internal
ones like the Timer Overflow and UART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
38
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
10.4ADC Noise Reduction Mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts,
Timer/Counter (if their clock source is external - T0 or T1) and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is e ntered. Apart fr om the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, a Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an External Level Interrupt
on INT3:0 can wake up the MCU from ADC Noise Reduction mode.
10.5Power-down Mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the External Oscillator is stopped, while the External Interrupts and
the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a
Brown-out Reset, a PSC Interrupt, an External Level Interrupt on INT3:0 can wake up the MCU.
This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
ATmega16M1/32M1/64M1
I/O
, clk
, and clk
CPU
, while allowing the
FLASH
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 60
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL fuses that define the
Reset Time-out period, as described in “Clock Sources” on page 28.
10.6Standby Mode
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
10.7Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 42, pro-
vides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in t he sa me stat e a s befor e shut down.
8209A–AVR–08/09
A full predictible behaviour of a peripheral is not guaranteed during and after a cycle of stopping
and starting of its clock. So its recommended to stop a peripheral before stopping its clock with
PRR register.
39
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
10.8Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
10.8.1Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “ADC – Analog to Digital Converter” on
page 225 for details on ADC operation.
10.8.2Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independe nt of sleep
mode. Refer to “AC – Analog Comparator” on page 256 for details on how to configure the Ana-
log Comparator.
ATmega16M1/32M1/64M1
10.8.3Brown-out Detector
If the Brown-out Detector is not needed by the a pplication, this module sh ould be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 45 for details
on how to configure the Brown-out Detector.
10.8.4Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 46 for details on the start-up time.
10.8.5Watchdog Timer
If the Watchdog Timer is not needed in t he application, the m odule should be tu rned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 47 for details on how to configu re t he Wa tchd og Time r.
10.8.6Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
8209A–AVR–08/09
40
ATmega16M1/32M1/64M1
the I/O clock (clk
) and the ADC clock (clk
I/O
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “I/O-Ports” on page 65 for details on which pins are enabled. If the
input buffer is enabled and the input signal is left floating or have an analog signal level close to
V
/2, the input buffer will use excessive power.
CC
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
/2 on an input pin can cause significant current even in active mode. Digital
CC
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” and “DIDR0 – Digital Input Disable
Register 0” on page 264 and page 248 for details.
10.8.7On-chip Debug System
If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the
main clock source is enabled, and hence, always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
10.9Register Description
10.9.1SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bit76543210
––––SM2SM1SM0SESMCR
Read/WriteRRRRR/WR/WR/WR/W
Initial Value 00000000
) are stopped, the input buffers of the device will
ADC
• Bits 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
Note:1. Standby mode is only recommended for use with external crystals or resonators.
(1)
8209A–AVR–08/09
41
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when th e SLEEP
instruction is executed. To avoid the MCU enteri ng th e sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) b it to one just befor e the exe cution of
the SLEEP instruction and to clear it immediately after waking up.
This bit is reserved and will always read as zero.
• Bit 6 - PRCAN: Power Reduction CAN
Writing a logic one to this bit reduces the consumption of the CAN by stopping the clock to this
module. When waking up the CAN again, the CAN should be re initialized to ensure proper
operation.
ATmega16M1/32M1/64M1
PRTIM1PRTIM0PRSPIPRLINPRADCPRR
• Bit 5 - PRPSC: Power Reduction PSC
Writing a logic one to this bit reduces the consumption of the PSC by stopping the clock to this
module. When waking up the PSC again, the PSC should be re initialized to ensure proper
operation.
• Bit 4 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit reduces the consumption of the Timer/Counter1 module. When the
Timer/Counter1 is enabled, operation will continue like before the setting of this bit.
• Bit 3 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit reduces the consumption of the Timer/Counter0 module. When the
Timer/Counter0 is enabled, operation will continue like before the setting of this bit.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing a logic one to this bit reduces the consumption of the Serial Peripheral Interface by stopping the clock to this module. When waking up the SPI again, the SPI should be re initialized to
ensure proper operation.
• Bit 1 - PRLIN: Power Reduction LIN
Writing a logic one to this bit reduces the consumption of the UART controller by stopping the
clock to this module. When waking up the UART controller again, the UART con trolle r should be
re initialized to ensure proper operation.
8209A–AVR–08/09
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit reduces the consumption of the ADC by stopping the clock to this
module. The ADC must be disabled before using this function. The analog comparator cannot
use the ADC input MUX when the clock of ADC is stopped.
42
11. System Control and Reset
11.1Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. This is also the case if the Reset Vector is in the Application section while the Interrupt
Vectors are in the Boot section or vice versa. The circuit diagram in Figure 11-1 shows the reset
logic. “System and Reset Characteristics” on page 313 defines the electrical parameters of the
reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 28.
ATmega16M1/32M1/64M1
11.2Reset Sources
The ATmega16M1/32M1/64M1 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (V
• External Reset. The MCU is reset when a low level is present on the RESET
than the minimum pulse length.
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage V
Reset threshold (V
POT
).
) and the Brown-out Detector is enabled.
BOT
pin for longer
is below the Brown-out
CC
8209A–AVR–08/09
43
Figure 11-1. Reset Logic
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BU S
Clock
Generator
Spike
Filter
Pull-up Resistor
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
RESET
TIME-OUT
INTER N AL
RESET
t
TOUT
V
RST
V
V
CC
CCRR
V
V
PORMIN
PORMAX
ATmega16M1/32M1/64M1
11.2.1Power-on Reset
8209A–AVR–08/09
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 313. The POR is activated whenever
V
is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
CC
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reac hing the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
when V
Figure 11-2. MCU Start-up, RESET
decreases below the detection level.
CC
rise. The RESET signal is activated again, without any delay,
An External Reset is generated by a low level on the RESET
minimum pulse width (see “System and Reset Characteristics ” on page 313) will generate a
reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
When the applied signal reaches the Reset Threshold Voltage – V
delay counter starts the MCU after the Time-out period – t
pin. Reset pulses longer than the
– on its positive edge, the
RST
has expired.
TOUT –
11.2.3Brown-out Detection
Figure 11-4. External Reset During Operation
ATmega16M1/32M1/64M1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the
V
level during operation by comparing it to a fixed trigger level. The trigger level for the BOD
CC
can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike
free Brown-out Detection. The hysteresis on the det ection leve l should be interp rete d as V
V
+ V
BOT
When the BOD is enabled, and V
11-5), the Brown-out Reset is immediately activated. When V
level (V
/2 and V
HYST
in Figure 11-5), the delay counter starts the MCU after the Time-out period t
BOT+
BOT-
= V
BOT
- V
CC
/2.
HYST
decreases to a value below the trigger level (V
increases above the trigger
CC
BOT-
in Figure
BOT+
TOUT
=
has
expired.
The BOD circuit will only detect a drop in V
ger than t
given in “System and Reset Characteristics” on page 313.
BOD
if the voltage stays below the trigger level for lon-
CC
8209A–AVR–08/09
45
11.2.4Watchdog Reset
V
CC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
CK
CC
ATmega16M1/32M1/64M1
Figure 11-5. Brown-out Reset During Operation
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
page 47 for details on operation of the Wat chdog Timer.
TOUT
. Refer to
Figure 11-6. Watchdog Reset During Operation
11.3Internal Voltage Reference
ATmega16M1/32M1/64M1 features an internal bandgap reference. This reference is used for
Brown-out DetectionDetection, and it can be used as an input to the Analog Comparators or the
ADC. The V
internal bandgap reference.
REF
2.56V reference to the ADC, DAC or Analog Comparators is generated from the
11.3.1Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. T he
8209A–AVR–08/09
start-up time is given in “System and Reset Characteristics” on page 313. To save power, the
reference is not always turned on. The reference is on during the following situations:
46
Thus, when the BOD is not enabled, after setting t he ACBG b it o r enab ling th e ADC or t he DAC,
128 KHz
OSCILLATOR
MCU RESET
INTERRUPT
WDIE
WDIF
OSC/2K
OSC/4K
OSC/8K
WDP3
the user must always allow the referen ce to st art up befo re the o utpu t from the An alog C ompar ator or ADC or DAC is used. To reduce power consumption in Power-down mode, the user can
avoid the three conditions above to ensure that the reference is turned off be fore entering
Power-down mode.
11.4Watchdog Timer
11.4.1Features
•
• 3 Operating modes
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
ATmega16M1/32M1/64M1
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR) .
3. When the ADC is enabled.
4. When the DAC is enabled.
Clocked from separate On-chip Oscillator
– Interrupt
– System Reset
– Interrupt and System Reset
11.4.2Overview
The ATmega16M1/32M1/64M1 has an Enhanced Watchdog Timer (WDT). The WDT is a timer
counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt o r a system reset when the counter reaches a given time-out value. In normal operation mode, it is
required that the system uses the WDR - Wat chdog Timer Reset - instr uction to restart th e counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or
system reset will be issued.
Figure 11-7. Watchdog Timer
8209A–AVR–08/09
In Interrupt mode, the WDT gives an interrupt when the time r expires. This int errupt can be used
to wake the device from sleep-modes, and also as a general system timer. One example is to
limit the maximum time allowed for certain operations, giving an interrupt when the operation
has run longer than expected. In System Reset mode, th e WDT gives a reset when the timer
47
ATmega16M1/32M1/64M1
expires. This is typically used to prevent system hang-up in case of runaway code. The third
mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown
by saving critical parameters before a system reset.
The “Watchdog Timer Always On” (WDTON) fuse, if programmed, will force the Watchdog Timer
to System Reset mode. With the fuse programmed th e System Reset mode bit (WDE) and In terrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and
WDE. A logic one must be written to WDE regardless of the previous value of the WDE
bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as
desired, but with the WDCE bit cleared. This must be done in one operation.
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during the execution of these functions.
8209A–AVR–08/09
48
ATmega16M1/32M1/64M1
Assembly Code Example
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in r16, MCUSR
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; Turn off WDT
ldi r16, (0<<WDE)
sts WDTCSR, r16
; Turn on global interrupt
sei
ret
C Code Example
(1)
(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCSR = 0x00;
__enable_interrupt();
}
Note:1. The example code assumes that the part specific header file is included.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out
condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is n ot
set up to handle the Watchdog, this might lead to an etern al loop of time-out resets. To avoid t his
situation, the application software should always clear the Watchdog System Reset Flag
(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
The following code example shows one assembly and one C function for changing the time-out
value of the Watchdog Timer.
8209A–AVR–08/09
49
ATmega16M1/32M1/64M1
Assembly Code Example
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCSR
ori r16, (1<<WDCE) | (1<<WDE)
sts WDTCSR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCSR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed equence */
WDTCSR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
(1)
(1)
8209A–AVR–08/09
Note:1. The example code assumes that the part specific header file is included.
Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change
in the WDP bits can result in a time-out when switching to a shorter time-out period.
50
11.5Register Description
11.5.1MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit76543210
Read/WriteRRRRR/WR/WR/WR/W
Initial Value0000See Bit Description
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
ATmega16M1/32M1/64M1
––––WDRFBORFEXTRFPORFMCUSR
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the prog ram. If the register is cle ared before anot her reset
occurs, the source of the reset can be found by examining the reset flags.
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is clear ed by writing a logic on e to the f lag. Whe n the I-bi t in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed .
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Re gister is set, the Wa tchdog Interr upt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
8209A–AVR–08/09
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
51
ATmega16M1/32M1/64M1
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should h owever not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.
Note:1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed.
Interrupt and System Reset
Mode
Interrupt, then go to System
Reset Mode
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensur es multiple reset s during co nditions causing failure, and a safe start-up after the failure.
• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in
Table 11-2 on page 53.
8209A–AVR–08/09
52
.
Table 11-2.Watchdog Timer Prescale Select
ATmega16M1/32M1/64M1
Number of WDT Oscillator
WDP3WDP2WDP1WDP0
00002K (2048) cycles16 ms
00014K (4096) cycles32 ms
00108K (8192) cycles64 ms
001116K (16384) cycles0.125 s
010032K (32768) cycles0.25 s
010164K (65536) cycles0.5 s
0110 128K (131072) cycles1.0 s
0111 256K (262144) cycles2.0 s
1000 512K (524288) cycles4.0 s
10011024K (1048576) cycles8.0 s
1010
1011
1100
1101
1110
1111
Cycles
Reserved
Typical Time-out at
VCC = 5.0V
8209A–AVR–08/09
53
12. Interrupts
This section describes the specifics of the interrupt handling as performed in
ATmega16M1/32M1/64M1. For a general explanation of the AVR interrupt handling , refer to
90x0010INT1External Interrupt Request 1
100x0012INT2External Interrupt Request 2
110x0014INT3External Interrupt Request 3
120x0016TIMER1 CAPTTimer/Counter1 Capture Event
130x0018TIMER1 COMPATimer/Counter1 Compare Match A
140x001ATIMER1 COMPBTimer/Counter1 Compare Match B
150x001CTIMER1 OVFTimer/Counter1 Overflow
160x001ETIMER0 COMPATimer/Counter0 Compare Match A
170x0020TIMER0 COMPBTimer/Counter0 Compare Match B
Notes:1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at
Program
AddressSourceInterrupt Definition
reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 272.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot
Flash Section. The address of each Interrupt Vector will then be the address in this table
added to the start address of the Boot Flash Section.
Table 12-2 shows reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt
Vectors are not used, and regular program co de can be placed at these locations. This is also
the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the
Boot section or vice versa.
Table 12-2.Reset and Interrupt Vectors Placement in ATmega16M1/32M1/64M1
Note:1. The Boot Reset Address is shown in Table 27-4 on page 277. For the BOOTRST Fuse “1”
means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATmega16M1/32M1/64M1 is:
Address Labels CodeComments
0x000jmpRESET; Reset Handler
0x002jmpANA_COMP_0; Analog Comparator 0 Handler
0x004jmpANA_COMP_1; Analog Comparator 1 Handler
0x006jmpANA_COMP_2; Analog Comparator 2 Handler
0x008jmpANA_COMP_3; Analog Comparator 3 Handler
0x00AjmpPSC_FAULT; PSC Fault Handler
0x00CjmpPSC_EC; PSC End of Cycle Handler
0x00EjmpEXT_INT0; IRQ0 Handler
0x010jmpEXT_INT1; IRQ1 Handler
0x012jmpEXT_INT2; IRQ2 Handler
0x014jmpEXT_INT3; IRQ3 Handler
0x016jmpTIM1_CAPT; Timer1 Capture Handler
0x018jmpTIM1_COMPA; Timer1 Compare A Handler
0x01AjmpTIM1_COMPB; Timer1 Compare B Handler
8209A–AVR–08/09
55
ATmega16M1/32M1/64M1
0x01CjmpTIM1_OVF; Timer1 Overflow Handler
0x01EjmpTIM0_COMPA; Timer0 Compare A Handler
0x020jmpTIM0_COMPB; Timer0 Compare B Handler
0x022jmpTIM0_OVF; Timer0 Overflow Handler
0x024jmpCAN_INT; CAN MOB,Burst,General Errors Handler
0x026jmpCAN_TOVF; CAN Timer Overflow Handler
0x028jmpLIN_TC; LIN Transfer Complete Handler
0x02AjmpLIN_ERR; LIN Error Handler
0x02CjmpPCINT0; Pin Change Int Request 0 Handler
0x02EjmpPCINT1; Pin Change Int Request 1 Handler
0x030jmpPCINT2; Pin Change Int Request 2 Handler
0x032jmpPCINT3; Pin Change Int Request 3 Handler
0x034jmpSPI_STC; SPI Transfer Complete Handler
0x036jmpADC; ADC Conversion Complete Handler
0x038jmpWDT; Watchdog Timer Handler
0x03AjmpEE_RDY; EEPROM Ready Handler
0x03CjmpSPM_RDY; Store Program Memory Ready Handler
;
0x03ERESET:ldir16, high(RAMEND); Main program start
0x03Fout SPH,r16; Set Stack Pointer to top of RAM
0x040ldi r16, low(RAMEND)
0x041out SPL,r16
0x042sei; Enable interrupts
0x043<instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses in
ATmega16M1/32M1/64M1 is:
8209A–AVR–08/09
Address Labels CodeComments
0x000RESET: ldir16,high(RAMEND); Main program start
0x001outSPH,r16; Set Stack Pointer to top of RAM
0x002ldir16,low(RAMEND)
0x003outSPL,r16
0x004sei; Enable interrupts
0x005<instr> xxx
;
.org 0xC02
0xC02jmpANA_COMP_0; Analog Comparator 0 Handler
0xC04jmpANA_COMP_1; Analog Comparator 1 Handler
.........;
0xC3CjmpSPM_RDY; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most
typical and general program setup for the Reset and Inter rupt Vector Addresses in
ATmega16M1/32M1/64M1 is:
56
ATmega16M1/32M1/64M1
Address Labels CodeComments
.org 0x002
0x002jmpANA_COMP_0; Analog Comparator 0 Handler
0x004jmpANA_COMP_1; Analog Comparator 1 Handler
.........;
0x03C jmpSPM_RDY; Store Program Memory Ready Handler
;
.org 0xC00
0xC00RESET: ldir16,high(RAMEND); Main program start
0xC01outSPH,r16; Set Stack Pointer to top of RAM
0xC02ldir16,low(RAMEND)
0xC03outSPL,r16
0xC04sei; Enable interrupts
0xC05<instr> xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interr upt Vector Addresses in ATmega16M1/32M1/64M1 is:
Address Labels CodeComments
;
.org 0xC00
0xC00jmpRESET; Reset handler
0xC02jmpANA_COMP_0; Analog Comparator 0 Handler
0xC04jmpANA_COMP_1; Analog Comparator 1 Handler
.........;
0xC3CjmpSPM_RDY; Store Program Memory Ready Handler
;
0xC3ERESET: ldir16,high(RAMEND); Main program start
0xC3FoutSPH,r16; Set Stack Pointer to top of RAM
0xC40ldir16,low(RAMEND)
0xC41outSPL,r16
0xC42sei; Enable interrupts
0xC43<instr> xxx
12.1.1Moving Interrupts Between Application and Boot Space
The MCU Control Register controls the placement of the Interrupt Vector table.
8209A–AVR–08/09
57
12.2Register Description
12.2.1MCUCR – MCU Control Register
Bit76543210
SPIPS––PUD––IVSELIVCEMCUCR
Read/WriteR/WRRR/WRRR/WR/W
Initial Value00000000
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write
Self-Programming” on page 272 for details. To avoid unintentio nal changes of Interrupt Vecto r
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
ATmega16M1/32M1/64M1
Note:If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-
Write Self-Programming” on page 272 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above . See Code Example below.
8209A–AVR–08/09
58
Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ldi r16, (1<<IVSEL)
out MCUCR, r16
ret
C Code Example
void Move_interrupts(void)
{
/* Enable change of Interrupt Vectors */
MCUCR = (1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = (1<<IVSEL);
}
ATmega16M1/32M1/64M1
8209A–AVR–08/09
59
13. External Interrupts
LE
DQ
DQ
clk
pin_latpin_syncpcint_in[i]
PCINT[i]
pin
PCINT[i] bit
(of PCMSK
n
)
DQDQDQ
clk
pcint_syncpcint_set/flag
0
7
PCIF
n
(interrupt
flag)
PCINT[i] pin
pin_lat
pin_sync
clk
pcint_in[i]
pcint_syn
pcint_set/flag
PCIF
n
The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23:0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23:0 pins are configured as
outputs. This feature provides a way of gener ating a so ft ware int er rupt . Th e pin chang e int erru pt
PCI2 will trigger if any enabled PCINT23:16 pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT14:8 pin toggles. The pin change interrupt PCI0 will trigger if any
enabled PCINT7:0 pin toggles. The PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT26:0 are
detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode.
The INT3:0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A – EICRA. When the
INT3:0 interrupts are enabled and are configured as level triggered, the interrupts will trigger as
long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT3:0
requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on
page 27. Low level interrupt on INT3:0 is detected asynchronously. This implies that this inter-
rupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock
is halted in all sleep modes except Idle mode.
ATmega16M1/32M1/64M1
Note that if a level triggered interrupt is used for wake-up from Power -down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in “Clock Systems and their Distribution” on page 27.
13.1Pin Change Interrupt Timing
An example of timing of a pin change interrupt is schown in Figure 13-1.
Figure 13-1. Timing of a pin change interrupts
8209A–AVR–08/09
60
13.2Register Description
13.2.1EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 7:0 – ISC3[1:0] - ISC0[1:0]: Interrupt Sense Control 3 to 0, Bit 1 and Bit 0
The External Interrupts 3, 2, 1 and 0 are activated by the external pins INT3:0 if the SREG I-flag
and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external
pins that activate the interrupt are defined in Table 13-1. Edges on INT3:0 are registered asynchronously. The value on the INT3:0 pins are sampled before detecting edges. If edge or toggle
interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency
can be lower than XTAL frequency if the XTAL divider is enabled. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as
long as the pin is held low.
ATmega16M1/32M1/64M1
Table 13-1.Interrupt Sense Control
ISCn1ISCn0Description
00The low level of INTn generates an interrupt request.
01Any logical change on INTn generates an interrupt request.
10The falling edge between two samples of INTn generates an interrupt request.
11The rising edge between two samples of INTn generates an interrupt request.
Note:1. n = 3, 2, 1 or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
13.2.2EIMSK – External Interrupt Mask Register
Bit76543210
––––INT3INT2INT1INT0EIMSK
Read/Write RRRRRRR/WR/W
Initial Value00000000
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3:0 – INT[3:0]: External Interrupt Request 3:0 Enable
When an INT3:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the
corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External
Interrupt Control Register A - EICRA defines whether the external interrupt is activated on rising
or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even
if the pin is enabled as an output. This provides a way of generating a software interrupt.
(1)
8209A–AVR–08/09
61
13.2.3EIFR – External Interrupt Flag Register
Bit76543210
––––INTF3INTF2INTF1INTF0EIFR
Read/WriteRRRRR/WR/WR/WR/W
Initial Value00000000
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3:0 – INTF[3:0]: External Interrupt Flag 3:0
When an edge or logic change on the I NT3:0 pin tri ggers a n inter rupt r equest, INTF3: 0 becomes
set (one). If the I-bit in SREG and the correspond ing interrupt enable b it INT3:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. The se flags are
always cleared when INT3:0 are configured as a level interrupt.
13.2.4PCICR – Pin Change Interrupt Control Register
Bit76543210
––––PCIE3PCIE2PCIE1PCIE0PCICR
Read/Write RRRRRR/WR/WR/W
Initial Value00000000
ATmega16M1/32M1/64M1
• Bit 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 - PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT26:24 pin will cause an interrupt. The corresponding interrupt of Pin Change Inter rupt Request is executed from the PCI3
Interrupt Vector. PCINT26:24 pins are enabled individually by the PCMSK3 Register.
• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an interrupt. The corresponding interrupt of Pin Change Inter rupt Request is executed from the PCI2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT14:8 pin will cause an interrupt. The corresponding interrupt of Pin Change Inter rupt Request is executed from the PCI1
Interrupt Vector. PCINT14:8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.
8209A–AVR–08/09
62
13.2.5PCIFR – Pin Change Interrupt Flag Register
Bit76543210
––––PCIF3PCIF2PCIF1PCIF0PCIFR
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
• Bit 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 - PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT26:24 pin triggers an interrupt request, PCIF3 becomes set
(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
ATmega16M1/32M1/64M1
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
These bits are reserved and will always read as zero.
• Bit 2:0 – PCINT26:24: Pin Change Enable Mask 26:24
Each PCINT26:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT26:24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in PCICR is set, pin change inte rrupt is ena bled on the
corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interru p t is en abled on the corresponding I/O pin. If PCINT7::0 is cleared, pin change interrupt on the corresponding I/O pin is
disabled.
8209A–AVR–08/09
64
14. I/O-Ports
C
pin
Logic
R
pu
See Figure
"General Digital I/O" for
Details
Pxn
14.1Overview
ATmega16M1/32M1/64M1
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/ disabling of p ull-up resist ors (if con figured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have prot ection diodes to both V
14-1. Refer to “Electrical Characteristics” on page 309 for a complete list of parameters.
Figure 14-1. I/O Pin Equivalent Schematic
and Ground as indicated in Figure
CC
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” rep resents the bit number. However,
when using the register or bit defines in a program , the precise form must be used. For examp le,
PORTB3 for bit no. 3 in Port B, here documented ge ner ally as PO RTxn . The physical I /O Registers and bit locations are listed in “Register Description”.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O”. Most port
pins are multiplexed with alternate functions for the peripheral features on the device. How each
alternate function interferes with the port pin is described in “Alternate Port Functions” on page
70. Refer to the individual module sections for a full descriptio n of the alt er nate fun ctio n s.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn.
ATmega16M1/32M1/64M1
Figure 14-2. General Digital I/O
(1)
Note:1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. cl k
14.2.1Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description” on page 84, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin h as to
be configured as an output pin
The port pins are tri-stated when reset condition becomes active, even if no clocks are running.
8209A–AVR–08/09
SLEEP, and PUD are common to all ports.
,
I/O
66
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
14.2.2Toggli ng the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
14.2.3Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-sta te ({DDxn, PORTxn} = 0b00) o r the o utput high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 14-1 summarizes the control signals for the pin value.
Table 14-1.Port Pin Configurations
ATmega16M1/32M1/64M1
DDxnPORTxn
00XInputNo
010InputYesPxn will source current if ext. pulled low.
011InputNoTri-state (Hi-Z)
10XOutputNoOutput Low (Sink)
11XOutputNoOutput High (So urce)
14.2.4Reading the Pin Value
Independent of the setting of Data Direction b it DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 14-2, t he PINxn Regist er bit a nd th e prece ding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also intro duces a delay. Fi gure 14-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are deno te d t
PUD
(in MCUCR)I/OPull-upComment
Default configuration after Reset.
Tri-state (Hi-Z)
pd,max
and t
respectively.
pd,min
8209A–AVR–08/09
67
ATmega16M1/32M1/64M1
XXXin r17, PINx
0x000xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min
out PORTx, r16nopin r17, PINx
0xFF
0x000xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
Figure 14-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows t
between ½ and 1½ system clock period depending upon the time of assertion.
pd,max
and t
, a single signal transition on the pin will be delayed
pd,min
8209A–AVR–08/09
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 14-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay t
Figure 14-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
through the synchronizer is 1 system clock period.
pd
68
ATmega16M1/32M1/64M1
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldir16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldir17, (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
outPORTB, r16
outDDRB, r17
; Insert nop for synchronization
nop
; Read port pins
inr16, PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
...
(1)
Note:1. For the assembly program, two temporary registers are used to minimize the time from pull-
ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
14.2.5Digital Input Enable and Sleep Modes
As shown in Figure 14-2, the digital input signal can be clamped to ground at the input of the
schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode, Power-save mode, and Standb y mode to avoid high power co nsumption if
some input signals are left floating, or have an analog signal level close to V
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 70.
If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the extern al interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned sleep modes, as the clamping in these sleep modes produces the requested
logic change.
8209A–AVR–08/09
CC
/2.
69
14.3Alternate Port Functions
clk
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
DLQ
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
RESET
Q
Q
D
CLR
Q
Q
D
CLR
Q
Q
D
CLR
PINxn
PORTxn
DDxn
DATA BUS
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
Pxn
I/O
0
1
PTOExn
WPx
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
WPx: WRITE PINx
Most port pins have alternate functions in addition to being general digital I/Os. Figure 14-5
shows how the port pin control signals from th e simplified Figure 14-2 can be overridden by
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
ATmega16M1/32M1/64M1
Figure 14-5. Alternate Port Functions
(1)
8209A–AVR–08/09
Note:1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. cl k
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 14-2 summarizes the function of the o verridin g signals. Th e pin and por t indexes f rom Fig-
ure 14-5 are not shown in the succeeding tables. The overriding signals ar e gen erat ed intern ally
in the modules having the alternate function.
,
I/O
70
ATmega16M1/32M1/64M1
Table 14-2.Generic Description of Overriding Signals for Alternate Functions
Signal NameFull NameDescription
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
PUOE
Pull-up Override
Enable
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DIDigital Input
AIO
Pull-up Override
Value
Data Direction
Override Enable
Data Direction
Override Value
Port Value
Override Enable
Port Value
Override Value
Port Toggle
Override Enable
Digital Input
Enable Override
Enable
Digital Input
Enable Override
Value
Analog
Input/Output
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the schmitt trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bidirectionally.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
8209A–AVR–08/09
71
14.3.1Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 14-3.
Table 14-3.Port B Pins Alternate Functions
Port PinAlternate Functions
PSCOUT0B (PSC output 0B)
PB7
PB6
PB5
PB4
PB3
PB2
ADC4 (Analog Input Channel 4)
SCK (SPI Bus Serial Clock)
PCINT7 (Pin Change Interrupt 7)
PSCOUT0B, Output 0B of PSC.
ADC4, Analog to Digital Converter, input channel 4
.
SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB7 bit.
PCINT7, Pin Change Interrupt 7.
• ADC7/PSCOUT1B/PCINT6 – Bit 6
ADC7, Analog to Digital Converter, input channel 7
.
PSCOUT1B, Output 1B of PSC.
8209A–AVR–08/09
72
PCINT6, Pin Change Interrupt 6.
ATmega16M1/32M1/64M1
•ADC6/INT2
ADC6, Analog to Digital Converter, input channel 6
INT2, External Interrupt source 2. This pin can ser ve as an External I nterrupt sour ce to the MCU.
ACMPN1, Analog Comparator 1 Negative Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
AMP0-, Analog Differential Amplifier 0 Negative Input Channel. Configure the port pin as input
with the internal pull-up switched off to avoid the digital port function from interfering with the
function of the Analog Amplifier.
PCINT3, Pin Change Interrupt 3.
•ADC5/INT1
ADC5, Analog to Digital Converter, input channel 5
/ACMPN1/AMP2-/PCINT5 – Bit 5
.
/ACMPN0/PCINT2 – Bit 2
.
INT1, External Interrupt source 1. This pin can ser ve as an exter nal inter rupt sour ce to th e MCU.
ACMPN0, Analog Comparator 0 Negative Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT2, Pin Change Interrupt 2.
• PCINT1/MOSI/PSCOUT2B – Bit 1
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1 When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 and PUD bits.
PSCOUT2B, Output 2B of PSC.
PCINT1, Pin Change Interrupt 1.
• PCINT0/MISO/PSCOUT2A – Bit 0
MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB0. When the SPI is
enabled as a slave, the data direction of th is pi n is controlled b y DDB0. When the pin is f orced to
be an input, the pull-up can still be controlled by the PORTB0 and PUD bits.
PSCOUT2A, Output 2A of PSC.
8209A–AVR–08/09
PCINT0, Pin Change Interrupt 0.
73
ATmega16M1/32M1/64M1
Table 14-4 and Table 14-5 relates the alternate functions of Port B to the overriding signals
shown in Figure 14-5 on page 70.
Table 14-4.Overriding Signals for Alternate Functions in PB7..PB4
PB7/ADC4/
PSCOUT0B/SCK/
Signal Name
PUOESPE • MSTR
PUOVPB7 • PUD
DDOE
DDOVPSCen01100
PVOESPE • MSTR • SPIPSPSCen1100
PVOV
DIEOEADC4DADC7DADC6D + In2enAMP0ND
DIEOV00In2en0
DI
AIOADC4ADC7ADC6AMP0+
PCINT7
• SPIPS000
• SPIPS000
SPE • MSTR
+ PSCen01
PSCout01 • SPIPS +
PSCout01 •
PSCen01 • SPIPS
+ PSCout01 •
PSCen01 • SPIPS
SCKin • SPIPS •
ireset
• SPIPS
PB6/ADC7/
PSCOUT1B/
PCINT6
PSCen1100
PSCOUT1100
ICP1BINT2
PB5/ADC6/
INT2/ACMPN1/
AMP2-/PCINT5
PB4/AMP0+/
PCINT4
Table 14-5.Overriding Signals for Alternate Functions in PB3..PB0
D2A, Digital to Analog output
AMP2+, Analog Differential Amplifier 2 Positive Input. Configure the port pin as input with the
internal pull-up switched off to avoid the digital port function from interfering with the function of
the Amplifier.
PCINT15, Pin Change Interrupt 15.
8209A–AVR–08/09
75
ATmega16M1/32M1/64M1
• ADC10/ACMP1/PCINT14 – Bit 6
ADC10, Analog to Digital Converter, input channel 10.
ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT14, Pin Change Interrupt 14.
• ADC9/ACMP3/AMP1+/PCINT13 – Bit 5
ADC9, Analog to Digital Converter, input channel 9.
ACMP3, Analog Comparator 3 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
AMP1+, Analog Differential Amplifier 1 Positive Input Channel. Configure the port pin as input
with the internal pull-up switched off to avoid the digital port function from interfering with the
function of the Analog Amplifier.
PCINT13, Pin Change Interrupt 13.
• ADC8/AMP1-/ACMPN3/PCINT12 – Bit 4
ADC8, Analog to Digital Converter, input channel 8.
AMP1-, Analog Differential Amplifier 1 Negative Input Channel. Configure the port pin as input
with the internal pull-up switched off to avoid the digital port function from interfering with the
function of the Analog Amplifier.
ACMPN3, Analog Comparator 3 Negative Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT12, Pin Change Interrupt 12.
• PCINT11/T1/RXCAN/ICP1B – Bit 3
T1, Timer/Counter1 counter source.
RXCAN, CAN Rx Data.
ICP1B, Input Capture Pin: The PC3 pin can act as an Input Capture Pin for Timer/Counter1.
PCINT11, Pin Change Interrupt 11.
OC1B, Output Compare Match B output: This pin can serve as an external output for the
Timer/Counter1 Output Compare B. The pin has to be configured as an outpu t (DDC1 set “one ”)
to serve this function. This pin is also the output pin for the PWM mode timer function.
76
ATmega16M1/32M1/64M1
SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDD0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTD0 bit.
PCINT9, Pin Change Interrupt 9.
• PCINT8/PSCOUT1A/INT3
– Bit 0
PSCOUT1A, Output 1A of PSC.
INT3, External Interrupt source 3: This pin can ser ve as an exter nal inter rupt sour ce to th e MCU.
PCINT8, Pin Change Interrupt 8.
Table 14-7 and Table 14-8 relate the alternate functions of Port C to the overriding signals
shown in Figure 14-5 on page 70.
Table 14-7.Overriding Signals for Alternate Functions in PC7..PC4
ACMP0, Analog Comparator 0 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT23, Pin Change Interrupt 23.
• ADC3/ACMPN2/INT0
/PCINT22 – Bit 6
ADC3, Analog to Digital Converter, input channel 3.
79
ATmega16M1/32M1/64M1
ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
INT0, External Interrupt source 0. This pin can ser ve as an exter nal inter rupt sour ce to th e MCU.
PCINT22, Pin Change Interrupt 23.
• ADC2/ ACMP2/PCINT21 – Bit 5
ADC2, Analog to Digital Converter, input channel 2.
ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal
pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
PCINT21, Pin Change Interrupt 21.
• PCINT20/ADC1/RXD/RXLIN/ICP1/SCK_A – Bit 4
ADC1, Analog to Digital Converter, input channel 1.
RXD/RXLIN, LIN/UART Receive Pin. Receive Data (Data input pin for the LIN/UART). When the
LIN/UART receiver is enabled this pin is configured as an input regardless of the value of
DDRD4. When the UART forces this pin to be an input, a logical one in PORTD4 will turn on the
internal pull-up.
ICP1, Input Capture Pin1: This pin can act as an input capture pin for Timer/Counter1.
SCK_A: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as
a slave, this pin is configured as an input regardless of the setting of DDD4. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDD4. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTD4 bit.
PCINT20, Pin Change Interrupt 20.
• PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A, Bit 3
TXD/TXLIN, LIN/UART Transmit pin. Data output pin for the LIN/UART. When the LIN/UART
Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.
OC0A, Output Compare Match A output: This pin can serve as an external output for the
Timer/Counter0 Output Compare A. The pin has to be configured as an outpu t (DDD3 set “one ”)
to serve this function. The OC0A pin is also the output pin for the PWM mode
SS
: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDD3. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDD3.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTD3 bit.
MOSI_A: SPI Master Data output, Slave Data input for SPI channel. Whe n the SPI is enabled as
a slave, this pin is configured as an input regardless of the setting of DDD3 When the SPI is
enabled as a master, the data direction of this pin is controlled by DDD3. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTD3 bit.
8209A–AVR–08/09
PCINT19, Pin Change Interrupt 19.
• PCINT18/PS CIN2 /O C1 A/M ISO_A, Bit 2
PCSIN2, PSC Digital Input 2.
80
ATmega16M1/32M1/64M1
OC1A, Output Compare Match A output: This pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an outpu t (DDD2 set “one ”)
to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
MISO_A: Master Data input, Slave Data output pi n for SPI channel. When the SPI is enabled as
a master, this pin is configured as an input regardless of the setting of DDD2. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDD2. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTD2 bit.
PCINT18, Pin Change Interrupt 18.
• PCINT17/PSCIN0/CLKO – Bit 1
PCSIN0, PSC Digital Input 0.
CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided
system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTD1 and
DDD1 settings. It will also be output during reset.
XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency
crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
ADC0, Analog to Digital Converter, input channel 0.
PCINT26, Pin Change Interrupt 26.
• PCINT25/XTAL1/OC0B – Bit 1
XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC
Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
OC0B, Output Compare Match B output: This pin can serve as an external output for the
Timer/Counter0 Output Compare B. The pin has to be config ured as an out put (DDE1 se t “ one ”)
to serve this function. This pin is also the output pin for the PWM mode timer function.
PCINT25, Pin Change Interrupt 25.
• PCINT24/RESET
RESET
, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O
/OCD – Bit 0
pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources.
When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the
pin can not be used as an I/O pin.
If PE0 is used as a reset pin, DDE0, PORTE0 and PINE0 will all read 0.
PCINT24, Pin Change Interrupt 24.
Table 14-13 relates the alternate functions of Port E to the overriding signals shown in Figure
14-5 on page 70.
Table 14-13. Overriding Signals for Alternate Functions in PE2..PE0
PE2/ADC0/XTAL2/
Signal Name
PUOE000
PUOV000
DDOE000
DDOV000
PVOE0OC0Ben0
PCINT26
PE1/XTAL1/OC0B/
PCINT25
PE0/RESET
OCD/PCINT24
/
8209A–AVR–08/09
PVOV0OC0B0
DIEOEADC0D00
DIEOV000
DI
AIO
Osc Output
ADC0
Osc / Clock input
83
14.4Register Description
14.4.1MCUCR – MCU Control Register
Bit76543210
SPIPS––PUD––IVSELIVCEMCUCR
Read/WriteR/WRRR/WRRR/WR/W
Initial Value00000000
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 66 for more details on this feature.
• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
15.2Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate progr am execution timing (event management) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual
placement of I/O pins, refer to “Pin Descriptions” on page 7. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-spe cific I/O Register and bit locations are listed in the “Register Description” on page 97 .
ATmega16M1/32M1/64M1
The PRTIM0 bit in “Power Reduction Register” on page 39 must be written to zero to enable
Timer/Counter0 module.
Figure 15-1. 8-bit Timer/Counter Block Diagram
8209A–AVR–08/09
86
15.2.1Definitions
15.2.2Registers
ATmega16M1/32M1/64M1
Many register and bit references in this section are written in genera l form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 15-1 are also used extensively throughout the document.
Table 15-1.Definitions
BOTTOMThe counter reaches the BOTTOM when it becomes 0x00.
MAXThe counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOPThe counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Re gister. The assignment is dependent on the mode of operation.
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A an d OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interr upts are individ ually masked with the Timer Inte rrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via th e prescaler, or b y an external clo ck source on
the T0 pin. The Clock Select logic block controls which clock source a nd edge the Tim er/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Using the Output Comp are Unit” on page 113. for details. The comp are match
event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request.
15.3Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B) . For details o n clock sources and p rescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 131.
15.4Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
15-2 shows a block diagram of the counter and its surroundings.
T0
).
8209A–AVR–08/09
87
ATmega16M1/32M1/64M1
Figure 15-2. Counter Unit Block Diagram
TOVn
top
(Int.Req.)
clk
Tn
DATA BUS
count
TCNTnControl Logic
clear
direction
bottom
Signal description (internal signals):
countIncrement or de cre m en t TCNT0 by 1.
directionSelect between increment and decrement.
clearClear TCNT0 (set all bits to zero).
Clock Select
Edge
Detector
( From Prescaler )
Tn
clk
topSignalize that TCNT0 has reached maximum value.
bottomSignalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation, see “Modes of
Operation” on page 91.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
15.5Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is aut om atica lly cleare d wh en the int errup t is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Compa re Outpu t mode (COM0x1:0) bits. The max
and bottom signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation (“Modes of Operation” on page 91).
Tn
is present or not. A CPU write overrides (has priority over) all counter clear or
T0
Timer/Counter clock, referred to as clkT0 in the following.
). clkT0 can be generated from an external or internal clock source,
T0
8209A–AVR–08/09
Figure 15-3 shows a block diagram of the Output Compare unit.
88
ATmega16M1/32M1/64M1
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform Generator
top
FOCn
COMnx1:0
bottom
Figure 15-3. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any o f the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Comp are (CTC) mode s of oper ation, the do uble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the doub le buffering
is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.
15.5.1Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0x) bit. Forcing compare match will not set the
OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare
match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or
toggled).
15.5.2Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an inte rrupt when the Timer/Counte r clock is
enabled.
15.5.3Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
downcounting.
8209A–AVR–08/09
89
The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their valu es even when
changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
15.6Compare Match Output Unit
The Compare Output mode (COM0x1:0) bits have two funct ions. The Wavefor m Generato r uses
the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match.
Also, the COM0x1:0 bits control the OC0x pin output source. Figure 15-4 shows a simplified
schematic of the logic affected by the COM0x 1:0 bit setting. Th e I/O Registe rs, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR
and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x
state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur,
the OC0x Register is reset to “0”.
Figure 15-4. Compare Match Output Unit, Schematic
ATmega16M1/32M1/64M1
COMnx1
COMnx0
FOCn
clk
I/O
Waveform
Generator
DQ
1
OCnx
DQ
PORT
DATA BUS
DQ
DDR
0
OCnx
Pin
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independen t of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state befor e the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation. See “Register Description” on page 97.
15.6.1Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x1:0 bits diff erently in Nor mal, CTC, and PWM modes.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the ne xt compare mat ch. For compa re output actio ns in the
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90
non-PWM modes refer to Table 15-2 on page 97. For fast PWM mode, refer to Table 15-3 on
page 97, and for phase correct PWM refer to Table 15-4 on page 98.
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.
15.7Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Gen eration mode (WGM02:0) and Comp are Output
mode (COM0x1:0) bits. The Compare Output mode bits do no t affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1: 0 bits control wheth er the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare
match (See “Compare Match Output Unit” on page 90.).
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 95.
15.7.1Normal Mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
ATmega16M1/32M1/64M1
The Output Compare unit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou tput Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
15.7.2Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero wh en the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output fre quency. It
also simplifies the operation of counting exte rn al ev en ts.
The timing diagram for the CTC mode is shown in Figure 15-5. The counter value (TCNT0)
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CT C mod e, the O C0A outp ut can be set to t oggle it s logica l
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of f
f
/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
clk_I/O
OC0
=
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
15.7.3Fast PWM Mode
8209A–AVR–08/09
As for the Normal mode of operation, the TOV0 Flag is set in the same tim er clock cycle tha t the
counter counts from MAX to 0x00.
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match
between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mo de can be twice as high as the phase co rrect PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
92
ATmega16M1/32M1/64M1
T
P
O
O
t
f
OCnxPWM
f
clk_I/O
N 256⋅
----------------- -=
PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation . The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slop es represent compare
matches between OCR0x and TCNT0.
Figure 15-6. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Se
OCRnx Update and
TOVn Interrupt Flag Set
CNTn
Cn
Cn
eriod
1
23
4567
(COMnx1:0 = 2)
(COMnx1:0 = 3)
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows
the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This op tion is no t ava ilable
for the OC0B pin (see Table 15-6 on page 9 8). The actual OC0x value will only be visible on the
port pin if the data direction for the port pin is set as output . Th e PWM wa vef orm is g ene rate d by
setting (or clearing) the OC0x Register at the compare match between OCR0x and TCNT0, and
clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes
from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
8209A–AVR–08/09
The extreme values for the OCR0A Regis ter represe nts specia l cases when generat ing a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform
generated will have a maximum frequency of f
OC0
= f
/2 when OCR0A is set to zero. This
clk_I/O
93
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
15.7.4Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match
between TCNT0 and OCR0x while upcounting, and set o n the compare ma tch while do wncounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is increme nted until the counter valu e matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 15-7 . The TCNT0 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x
and TCNT0.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTT OM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
8209A–AVR–08/09
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inve rted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
94
ATmega16M1/32M1/64M1
f
OCnxPCPWM
f
clk_I/O
N 510⋅
----------------- -=
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTnMAX - 1MAXBOTTOMBOTTOM + 1
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (see Table 15-7 on page 99). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is se t as o ut put. Th e PWM wa vef orm is
generated by clearing (or setting) the OC0x Re gister at the comp are match between OCR0x and
TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare
match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If th e OCR0A is set equal to BOTTOM , the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 15-7 OCnx has a transition from high to low even thoug h
there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.
• OCRnx changes its value from MAX, lik e in Figure 15-7. Whe n th e O CR0 A value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an upcounting Compare Match.
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
misses the Compare Match and hence the OCnx change that would have happened on the
way up.
15.8Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 15-8. Timer/Counter Timing Diagram, no Prescaling
Figure 15-9 shows the same timing data, but with the prescaler enabled.
8209A–AVR–08/09
95
ATmega16M1/32M1/64M1
TOVn
TCNTn
MAX - 1MAXBOTTOMBOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1OCRnxOCRnx + 1OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1TOPBOTTOMBOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O
/8)
8209A–AVR–08/09
Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal por t function ality of th e I/O pin it is conne cted
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 15-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 15-2.Compare Output Mode, non-PWM Mode
COM0A1COM0A0Description
00Normal port operation, OC0A disconnected.
ATmega16M1/32M1/64M1
01Toggle OC0A on Compare Match
10Clear OC0A on Compare Match
11Set OC0A on Compare Match
Table 15-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 15-3.Compare Output Mode, Fast PWM Mode
COM0A1COM0A0Description
00Normal port operation, OC0A disconnected.
01
10Clear OC0A on Compare Match, set OC0A at TOP
11Set OC0A on Compare Match, clear OC0A at TOP
Note:1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 92
for more details.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0 A on Compare Match.
(1)
8209A–AVR–08/09
97
ATmega16M1/32M1/64M1
Table 15-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
Note:1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 118 for more details.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
(1)
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal por t function ality of th e I/O pin it is conne cted
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 15-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 15-5.Compare Output Mode, non-PWM Mode
COM0B1COM0B0Description
00Normal port operation, OC0B disconnected.
01Toggle OC0B on Compare Match
10Clear OC0B on Compare Match
11Set OC0B on Compare Match
Table 15-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Table 15-6.Compare Output Mode, Fast PWM Mode
COM0B1COM0B0Description
00Normal port operation, OC0B disconnected.
01Reserved
10Clear OC0B on Compare Match, set OC0B at TOP
11Set OC0B on Compare Match, clear OC0B at TOP
Note:1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 92
for more details.
(1)
8209A–AVR–08/09
98
ATmega16M1/32M1/64M1
Table 15-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-
00Normal port operation, OC0B disconnected.
01Reserved
10
11
Note:1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 94 for more details.
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
(1)
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 15-8. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 91).
Table 15-8.Waveform Generatio n Mod e Bit Des crip tio n
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
ATmega16M1/32M1/64M1
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 97.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 15-9.Clock Select Bit Description
CS02CS01CS00Description
000No clock source (Timer/Counter stopped)
8209A–AVR–08/09
001clk
010clk
011clk
/(No prescaling)
I/O
/8 (From prescaler)
I/O
/64 (From prescaler)
I/O
100
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