Rainbow Electronics ATmega64M1 User Manual

Features

• High Performance, Low Power AVR ® 8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier

• Data and Non-Volatile Program Memory

– 16/32/64K Bytes Flash of In-System Programmable Program Memory – 512B/1K/2K Bytes of In-System Programmable EEPROM – 1/2/4K Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data Retention: 20 years at 85°C/ 100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– Programming Lock for Flash Program and EEPROM Data Security

• On Chip Debug Interface (debugWIRE)

• CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified

• LIN 2.1 and 1.3 Controller or 8-Bit UART

• One 12-bit High Speed PSC (Power Stage Controller)

– Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time – Variable PWM duty Cycle and Frequency – Synchronous Update of all PWM Registers – Auto Stop Function for Emergency Event

• Peripheral Features

– One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode

and Capture Mode

– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare

Mode and Capture Mode – One Master/Slave SPI Serial Interface – 10-bit ADC

Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels Internal Reference Voltage

Direct Power Supply Voltage Measurement – 10-bit DAC for Variable Voltage Reference (Comparators, ADC) – Four Analog Comparators with Variable Threshold Detection – 100µA ±2% Current Source (LIN Node Identification) – Interrupt and Wake-up on Pin Change – Programmable Watchdog Timer with Separate On-Chip Oscillator – On-chipTemperature Sensor

• Special Microcontroller Features

– Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – In-System Programmable via SPI Port – High Precision Crystal Oscillator for CAN Operations (16 MHz) – Internal Calibrated RC Oscillator ( 8 MHz) – On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)

• Operating Voltage: 2.7V - 5.5V

• Extended Operating Temperature:

– -40°C to +85°C

• Core Speed Grade:

– 0 - 8MHz @ 2.7 - 4.5V – 0 - 16MHz @ 4.5 - 5.5V

Note: 1. See “Data Retention” on page 9 for details.

(1)

8-bit Microcontroller

with 16/32/64K Bytes In-System Programmable Flash

ATmega16M1 ATmega32M1 ATmega64M1

Preliminary

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1. Pin Configurations

1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

(PCINT18/PSCIN2/OC1A/MISO_A) PD2

(PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3

(PCINT9/PSCIN1/OC1B/SS_A) PC1

VCC

GND

(PCINT10/T0/TXCAN) PC2

(PCINT11/T1/RXCAN/ICP1B) PC3

(PCINT0/MISO/PSCOUT2A) PB0

PB4 (AMP0+/PCINT4) PB3 (AMP0-/PCINT3) PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND AVCC PC5 (ADC9/ACMP3/AMP1+/PCINT13) PC4 (ADC8/ACMPN3/AMP1-/PCINT12)

32313029282726

9101112131415

(PCINT1/MOSI/PSCOUT2B) PB1

(PCINT25/OC0B/XTAL1) PE1

(PCINT26/ADC0/XTAL2) PE2

(ADC2/ACMP2/PCINT21) PD5

(ADC3/ACMPN2/INT0/PCINT22) PD6

(ACMP0/PCINT23) PD7

(ADC5/INT1/ACMPN0/PCINT2) PB2

PD1

(PCINT17/PSCIN0/CLKO)

PE0

(PCINT24/RESET/OCD)

PC0

(PCINT8/INT3/PSCOUT1A)

PD0

(PCINT16/PSCOUT0A)

PB7 (ADC4/PSCOUT0B/SCK/PCINT7)

PB6 (ADC7/PSCOUT1B/PCINT6)

PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5)

PC7 (D2A/AMP2+/PCINT15)

Figure 1-1. ATmega16M1/32M1/64M1 TQFP32/QFN32 (7*7 mm) Package.

ATmega16M1/32M1/64M1

8209A–AVR–08/09

1.1 Pin Descriptions

Table 1-1. Pin out description

QFN32 Pin

ATmega16M1/32M1/64M1

Number Mnemonic Type Name, Function & Alternate Function

5GNDPowerGround: 0V reference

20 AGND Power Analog Ground: 0V reference for analog part

4VCCPowerPower Supply

Analog Power Supply: This is the power supply voltage for analog

19 AVCC Power

21 AREF Power

part For a normal use this pin must be connected.

Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog

ISRC (Current Source Output)

8 PB0 I/O

9 PB1 I/O

16 PB2 I/O

23 PB3 I/O

24 PB4 I/O

26 PB5 I/O

27 PB6 I/O

MISO (SPI Master In Slave Out) PSCOUT2A PCINT0 (Pin Change Interrupt 0)

MOSI (SPI Master Out Slave In) PSCOUT2B PCINT1 (Pin Change Interrupt 1)

ADC5 (Analog Input Channel 5 ) INT1 (External Interrupt 1 Input) ACMPN0 (Analog Comparator 0 Negative Input) PCINT2 (Pin Change Interrupt 2)

AMP0- (Analog Differential Amplifier 0 Negative Input) PCINT3 (Pin Change Interrupt 3)

AMP0+ (Analog Differential Amplifier 0 Positive Input) PCINT4 (Pin Change Interrupt 4)

ADC6 (Analog Input Channel 6) INT2 (External Interrupt 2 Input) ACMPN1 (Analog Comparator 1 Negative Input) AMP2- (Analog Differential Amplifier 2 Negative Input) PCINT5 (Pin Change Interrupt 5)

ADC7 (Analog Input Channel 7) PSCOUT1B PCINT6 (Pin Change Interrupt 6)

(1)

(PSC Module 2 Output A)

(1)

(PSC Module 2 Output B)

(1)

(PSC Module 1 Output A)

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28 PB7 I/O

30 PC0 I/O

ADC4 (Analog Input Channel 4) PSCOUT0B SCK (SPI Clock) PCINT7 (Pin Change Interrupt 7)

PSCOUT1A INT3 (External Interrupt 3 Input) PCINT8 (Pin Change Interrupt 8)

(1)

(PSC Module 0 Output B)

(1)

(PSC Module 1 Output A)

ATmega16M1/32M1/64M1

Table 1-1. Pin out description (Continued)

QFN32 Pin

Number Mnemonic Type Name, Function & Alternate Function

PSCIN1 (PSC Digital Input 1)

3 PC1 I/O

6 PC2 I/O

7 PC3 I/O

17 PC4

I/O

OC1B (Timer 1 Output Compare B) SS_A (Alternate SPI Slave Select) PCINT9 (Pin Change Interrupt 9)

T0 (Timer 0 clock input) TXCAN (CAN Transmit Output) PCINT10 (Pin Change Interrupt 10)

T1 (Timer 1 clock input) RXCAN (CAN Receive Input) ICP1B (Timer 1 input capture alternate B input) PCINT11 (Pin Change Interrupt 11)

ADC8 (Analog Input Channel 8) AMP1- (Analog Differential Amplifier 1 Negative Input) ACMPN3 (Analog Comparator 3 Negative Input ) PCINT12 (Pin Change Interrupt 12)

18 PC5 I/O

22 PC6 I/O

25 PC7 I/O

29 PD0 I/O

32 PD1 I/O

1 PD2 I/O

2 PD3 I/O

ADC9 (Analog Input Channel 9) AMP1+ (Analog Differential Amplifier 1 Positive Input) ACMP3 (Analog Comparator 3 Positive Input) PCINT13 (Pin Change Interrupt 13)

ADC10 (Analog Input Channel 10) ACMP1 (Analog Comparator 1 Positive Input ) PCINT14 (Pin Change Interrupt 14)

D2A (DAC output ) AMP2+ (Analog Differential Amplifier 2 Positive Input) PCINT15 (Pin Change Interrupt 15)

(1)

PSCOUT0A PCINT16 (Pin Change Interrupt 16)

PSCIN0 (PSC Digital Input 0) CLKO (System Clock Output) PCINT17 (Pin Change Interrupt 17)

OC1A (Timer 1 Output Compare A) PSCIN2 (PSC Digital Input 2) MISO_A (Programming & alternate SPI Master In Slave Out) PCINT18 (Pin Change Interrupt 18)

TXD (UART Tx data) TXLIN (LIN Transmit Output) OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In) PCINT19 (Pin Change Interrupt 19)

(PSC Module 0 Output A)

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ATmega16M1/32M1/64M1

Table 1-1. Pin out description (Continued)

QFN32 Pin

Number Mnemonic Type Name, Function & Alternate Function

ADC1 (Analog Input Channel 1) RXD (UART Rx data)

12 PD4 I/O

13 PD5 I/O

14 PD6 I/O

RXLIN (LIN Receive Input) ICP1A (Timer 1 input capture alternate A input) SCK_A (Programming & alternate SPI Clock) PCINT20 (Pin Change Interrupt 20)

ADC2 (Analog Input Channel 2) ACMP2 (Analog Comparator 2 Positive Input ) PCINT21 (Pin Change Interrupt 21)

ADC3 (Analog Input Channel 3 ) ACMPN2 (Analog Comparator 2 Negative Input) INT0 (External Interrupt 0 Input) PCINT22 (Pin Change Interrupt 22)

2. Overview

15 PD7 I/O

31 PE0 I/O or I

10 PE1 I/O

11 PE2 I/O

ACMP0 (Analog Comparator 0 Positive Input ) PCINT23 (Pin Change Interrupt 23)

RESET (Reset Input) OCD (On Chip Debug I/O) PCINT24 (Pin Change Interrupt 24)

XTAL1 (XTAL Input) OC0B (Timer 0 Output Compare B) PCINT25 (Pin Change Interrupt 25)

XTAL2 (XTAL Output) ADC0 (Analog Input Channel 0) PCINT26 (Pin Change Interrupt 26)

Note: 1. Only for Atmega32M1/64M1.

2. On the engineering samples, the ACMPN3 alternate function is not located on PC4. It is located on PE2.

The ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16M1/32M1/64M1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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2.1 Block Diagram

Flash Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

4 Analog

Comparators

DAC

ADC

MPSC

Timer 1

Timer 0

HW LIN/UART

CAN

Current Source

ATmega16M1/32M1/64M1

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega16M1/32M1/64M1 provides the following features: 16/32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4K bytes SRAM, 27 general purpose I/O lines, 32 general p urpose working registers, one Motor Power Stage Controller, two flexible Timer/Counters with compare modes and PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes.

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ATmega16M1/32M1/64M1

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power -down mo de saves the r egister contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16M1/32M1/64M1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control app lications.

The ATmega16M1/32M1/64M1 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of v ari ous s pecia l feat ures of th e ATme ga16 M1/ 32M1/ 64M 1 as listed on page 72.

2.2.4 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

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Port C also serves the functions of special features of the ATmega16M1/32M1/64M1 as listed on page 75.

2.2.5 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega16M1/32M1/64M1 as listed on page 79.

ATmega16M1/32M1/64M1

2.2.6 Port E (PE2..0) RESET/ XTAL2

Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port E.

If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 313. Shorter pulses are not guaranteed to generate a Reset.

Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock oper ating circuit.

Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier.

The various special features of Port E are elaborated in “Alternate Functions of Port E” on page

82 and “Clock Systems and their Distribution” on page 27.

XTAL1/

2.2.7 AVCC

2.2.8 AREF

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AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should be externally connected to V be connected to V

through a low-pass filter.

, even if the ADC, DAC are not used. If the ADC is used, it should

This is the analog reference pin for the A/D Converter.

3. Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es will be available after the device is characterized.

4. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

5. About Code Examples

This documentation contains simple code examples tha t briefly sh ow how to use var ious par ts of the device. Be aware that not all C compiler vendors include bit def initions in the header files and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumentation for more details.

These code examples assume that the part spe cific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBI C", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

ATmega16M1/32M1/64M1

6. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

8209A–AVR–08/09

7. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

7.1 Overview

ATmega16M1/32M1/64M1

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 7-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

8209A–AVR–08/09

ATmega16M1/32M1/64M1

ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointe rs can also be used as an address pointe r for look up tables in Flash pr ogram memory. Thes e added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM (Store Program Memory) instruction that writes into the Applicatio n Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher is the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega16M1/32M1/64M1 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

7.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

7.3 Status Register

The Status Register contains information abou t th e result o f th e most r ecently exe cuted arith metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as

8209A–AVR–08/09

specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be hand le d by so ftware.

7.3.1 SREG – AVR Status Register

Bit 76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

ATmega16M1/32M1/64M1

ITHSVNZCSREG

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

8209A–AVR–08/09

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

7.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In or der to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 7-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11

ATmega16M1/32M1/64M1

70Addr. R0 0x00

R1 0x01 R2 0x02 … R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

7.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3.

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7.5 Stack Pointer

ATmega16M1/32M1/64M1

Figure 7-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement , automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area wh ere the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls ar e executed or interrupts are enabled. Initial Stack Pointer value equa ls the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure

8-2 on page 19.

See Table 7-1 for Stack Pointer details.

Table 7-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack CALL

ICALL RCALL

POP Incremented by 1 Data is popped from the stack RET

RETI

Decremented by 2

Incremented by 2 Return address is popped from the stack with return from

Return address is pushed onto the stack with a subroutine call or interrupt

subroutine or return from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

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ATmega16M1/32M1/64M1

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register

Bit 1514131211109 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

7.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

, directly generated from the selected clock source for the

CPU

Figure 7-4. The Parallel Instruction Fetches and Instruction Executions

Figure 7-5 shows the internal timing concept for th e Regi ster File . In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7-5. Single Cycle ALU Operation

8209A–AVR–08/09

7.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 289 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 54. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is ANACOMP0 – the Analog Comparator 0 Interrupt. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 54 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-

Programming” on page 272.

7.7.1 Interrupt Behavior

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

ATmega16M1/32M1/64M1

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts , the Program Cou nter is vectored t o the actual In terrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corres ponding interrup t enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt rou tine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to a void interrupts during the timed EEPROM write sequence.

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ATmega16M1/32M1/64M1

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

7.7.2 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector addre ss fo r t he actua l interr up t ha nd ling rout ine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in ad dition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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ATmega16M1/32M1/64M1

8. Memories

8.1 Overview

This section describes the different memories in the ATmega16M1/32M1/64M1. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16M1/32M1/64M1 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

8.2 In-System Reprogrammable Flash Program Memory

The ATmega16M1/32M1/64M1 contains 16/32/64K bytes On-chip In-System Reprogrammable Flash memory for program storage . Since all AVR instructio ns are 16 or 32 bits wide, the Flas h is organized as 16K x 16 / 32K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16M1/32M1/64M1 Program Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-

Programming” on page 272. “Memory Programming” on page 289 contains a detailed descrip-

tion on Flash programming in SPI or Parallel programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory. Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 15.

Figure 8-1. Program Memory Map

Program Memory

0x0000

Application Flash Section

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Boot Flash Section

0x1FFF/0x3FFF/0x7FF

8.3 SRAM Data Memory

32 Registers

64 I/O Registers

Internal SRAM

(1024/2048/4096 x 8)

0x0000 - 0x001F 0x0020 - 0x005F

0x04FF/0x08FF/0x10FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

Figure 8-2 shows how the ATmega16M1/32M1/64M1 SRAM Memory is organized.

The ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for th e IN and OUT instr uctions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2304 data memory locations address both the Reg ister File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 1/2/4K locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations f rom the base address given

by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

ATmega16M1/32M1/64M1

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 1/2/4K bytes of internal data SRAM in the ATmega16M1 /32M1/64M1 are all accessible through all these addressing modes. The Register File is described in “General Purpose Regis-

ter File” on page 13.

Figure 8-2. Data Memory Map1/2/4K

8.3.1 SRAM Data Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

cycles as described in Figure 8-3.

CPU

8209A–AVR–08/09

Figure 8-3. On-chip Data SRAM Access Cycles

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

8.4 EEPROM Data Memory

The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

ATmega16M1/32M1/64M1

For a detailed description of SPI and Parallel data downloading to the EEPROM, see “Serial

Downloading” on page 305 , and “Parallel Programming Parameters, Pin Mapping, and Commands” on page 294 respectively.

8.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 8-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contain s instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V

period of time to run at a voltage lower than specif ied as mi nimum for the clock fre quen cy used .

See “Preventing EEPROM Corruption” on page 21.for details on how to avoid problems in these

situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

is likely to rise or fall slowly on power-up/down. This causes the device for some

8209A–AVR–08/09

8.4.2 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an exter nal low V be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

8.5 I/O Memory

The I/O space definition of the ATmega16M1/32M1/64M1 is shown in “Register Summary” on

page 322.

All ATmega16M1/32M1/64M1 I/O s and peripherals are placed in t he I /O sp ace. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

ATmega16M1/32M1/64M1

the EEPROM data can be corrupted because the supply voltage is

CC,

reset Protection circuit can

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to th em. Note that, u nlike most other AVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

8.6 General Purpose I/O Registers

The ATmega16M1/32M1/64M1 contains four General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. See “Register Description” on page 22 for details.

The General Purpose I/O Registers, within the address range 0x00 - 0x1F, are directly bitaccessible using the SBI, CBI, SBIS, and SBIC instructions.

8209A–AVR–08/09

8.7 Register Description

8.7.1 EEARH and EEARL – The EEPROM Address Registers

Bit 1514131211 10 9 8

– – – – – - EEAR9 EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543 2 10

Read/Write R R R R R R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

XXXXX X XX

• Bits 15:10 – Res: Reserved

These bits are reserved and will always read as zero.

• Bits 9:0 – EEAR[8:0]: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512B/1K/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

ATmega16M1/32M1/64M1

8.7.2 EEDR – The EEPROM Data Register

Bit 76543210

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bits 7:0 – EEDR[7:0]: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to b e written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

8.7.3 EECR – The EEPROM Control Register

Bit 76543210

– – EEPM1 EEPM0 EERIE EEMWE EEWE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bits 7:6 – Reserved Bits

These bits are reserved and will always read as zero.

• Bits 5:4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEWE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 8-1. While

8209A–AVR–08/09

ATmega16M1/32M1/64M1

EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 8-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

Time Operation

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value in to the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Control and Status Register) becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never bein g up da te d by th e CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-Programming” on page 272 for details about Boot

programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

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ATmega16M1/32M1/64M1

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero bef ore wr iting th e next byte. Whe n EEWE has b een set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Registe r, the EERE b it must be writte n to a log ic one t o trigger t he EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 8-2 lists the typica l programming time for EEPROM access from the CPU.

Table 8-2. EEPROM Programming Time.

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU)

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

26368 3.3 ms

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ATmega16M1/32M1/64M1

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write (unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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ATmega16M1/32M1/64M1

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

8.7.4 GPIOR0 – General Purpose I/O Register 0

Bit 76543210

GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

8.7.5 GPIOR1 – General Purpose I/O Register 1

Bit 76543210

GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

8.7.6 GPIOR2 – General Purpose I/O Register 2

Bit 76543210

GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

8209A–AVR–08/09

9. System Clock and their Distribution

General I/O

Modules

ADC CPU Core RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and EEPROM

clk

FLASH

clk

ADC

Source Clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog Clock

Calibrated RC

Oscillator

(Crystal

Oscillator)

External Clock

Fast Peripherals

PLL

CLK

PLL

9.1 Clock Systems and their Distribution

Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different slee p modes, as described in “Power Man agement and

Sleep Modes” on page 38. The clock systems are detailed below.

Figure 9-1. Clock Distribution

ATmega16M1/32M1/64M1

9.1.1 CPU Clock – clk

9.1.2 I/O Clock – clk

9.1.3 Flash Clock – clk

8209A–AVR–08/09

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

I/O

The I/O clock is used by the majority of the I/O modules, like Timer /Counters, SPI, UART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interru pts t o be det ected even if the I/ O clock is halted.

FLASH

The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.

ATmega16M1/32M1/64M1

9.1.4 PLL Clock – clk

9.1.5 ADC Clock – clk

9.2 Clock Sources

PLL

The PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock. A 16 MHz clock is also derived for the CPU.

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion results.

The device has the following clock source options, selectable by Flash Fuse bits as illustrated Table 9-1. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 9-1. Device Clocking Options Select

Device Clocking Option System

External Crystal/Ceramic Resonator Ext Osc RC Osc 1111 - 1000 PLL output divided by 4 : 16 MHz / PLL driven by External

Crystal/Ceramic Resonator PLL output divided by 4 : 16 MHz / PLL driven by External

Crystal/Ceramic Resonator Reserved N/A N/A 0110 Reserved N/A N/A 0111

(1)

CKSEL3..0

Clock PLL Input

Ext Osc Ext Osc 0100

PLL / 4 Ext Osc 0101

PLL output divided by 4 : 16 MHz PLL / 4 RC Osc 0011 Calibrated Internal RC Oscillator RC Osc RC Osc 0010 PLL output divided by 4 : 16 MHz / PLL driven by External

clock External Clock Ext Clk RC Osc 0000

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

2. Ext Osc : External Osc

3. RC Osc : Internal RC Oscillator

4. Ext Clk : External Clock Input

PLL / 4 Ext Clk 0001

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the startup, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 9-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.

8209A–AVR–08/09

Table 9-2. Number of Watchdog Oscillator Cycles

XTAL2

XTAL1

GND

Typ Time-o ut (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096) 65 ms 69 ms 64K (65,536)

9.3 Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “ 10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This defa ult setting ensure s that all users ca n make their des ired clock source setting using an In-System or Parallel programmer.

9.4 Low Power Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 9-2. Either a quartz crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs.

ATmega16M1/32M1/64M1

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-3. For ceramic resonators, the capacitor values given by the manufacturer should be used. For more information on how to choose capacitors and other details on Oscillator operation, refer to the Multi-purpose Oscillator Application Note.

Figure 9-2. Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 9-3.

8209A–AVR–08/09

ATmega16M1/32M1/64M1

Table 9-3. Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

CKSEL3..1 Frequency Range

100

(2)

0.4 - 0.9 –

(1)

(MHz)

101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 -16.0 12 - 22

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

9-4.

Table 9-4. Start-up Times for the Oscillator Clock Selection

Start-up Time from

Power-down and

CKSEL0 SUT1..0

0 00 258 CK

0 01 258 CK

010 1K CK

011 1K CK

Power-save

(1)

(2)

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

14CK + 4.1 ms

14CK + 65 ms

14CK

14CK + 4.1 ms

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

8209A–AVR–08/09

100 1K CK

(2)

14CK + 65 ms

1 01 16K CK 14CK

1 10 16K CK 14CK + 4.1 ms

1 11 16K CK 14CK + 65 ms

Ceramic resonator, slowly rising power

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

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