Rainbow Electronics ATmega3290PV User Manual

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles

32K bytes (ATmega329/ATmega3290) 64K bytes (ATmega649/ATmega6490)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– EEPROM, Endurance: 100,000 Write/Erase Cycles

1K bytes (ATmega329/ATmega3290) 2K bytes (ATmega649/ATmega6490)

– Internal SRAM

2K bytes (ATmega329/ATmega3290) 4K bytes (ATmega649/ATmega6490)

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– 4 x 25 Segment LCD Driver (ATmega329/ATmega649) – 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega329V/ATmega3290V/ATmega649V/ATmega6490V:

0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega329/3290/649/6490:

0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

8-Bit Microcontroller

8-bit

Microcontroller with In-System Programmable Flash

ATmega329/V ATmega3290/V ATmega649/V ATmega6490/V

Preliminary

2552H–AVR–11/06

Features (Continued)

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 350 µA 32 kHz, 1.8V: 20 µA (including Oscillator) 32 kHz, 1.8V: 40 µA (including Oscillator and LCD)

– Power-down Mode:

100 nA at 1.8V

Pin Configurations Figure 1. Pinout ATmega3290/6490

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

9998979695949392919089888786858483828180797877

100

LCDCAP

VCC

GND

DNC

INDEX CORNER

26272829303132333435363738394041424344454647484950

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(PCINT24/SEG35) PJ0

(PCINT25/SEG34) PJ1

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

ATmega3290/6490

PH7 (PCINT23/SEG36)

PH6 (PCINT22/SEG37)

PH5 (PCINT21/SEG38)

PH4 (PCINT20/SEG39)

DNC

GND

VCC

DNC

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

DNC

PH3 (PCINT19/SEG7)

PH2 (PCINT18/SEG8)

PH1 (PCINT17/SEG9)

PH0 (PCINT16/SEG10)

DNC

PC5 (SEG11)

PC4 (SEG12)

PC3 (SEG13)

PC2 (SEG14)

PC1 (SEG15)

PC0 (SEG16)

PG1 (SEG17)

PG0 (SEG18)

RESET/PG5

(T1/SEG33) PG3

(T0/SEG32) PG4

VCC

GND

DNC

(TOSC2) XTAL2

(TOSC1) XTAL1

(PCINT26/SEG31) PJ2

(PCINT27/SEG30) PJ3

DNC

(PCINT28/SEG29) PJ4

(ICP1/SEG26) PD0

(PCINT29/SEG28) PJ5

(PCINT30/SEG27) PJ6

(SEG24) PD2

(SEG23) PD3

(SEG22) PD4

(INT0/SEG25) PD1

(SEG21) PD5

(SEG20) PD6

(SEG19) PD7

DNC

(OC2A/PCINT15) PB7

ATmega329/3290/649/6490

2552H–AVR–11/06

Figure 2. Pinout ATmega329/649

AREF

GND

AVCC

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

INDEX CORNER

ATmega329/3290/649/6490

VCC

PF0 (ADC0)

PF1 (ADC1)

6018592058

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

57225623552454255326522751

ATmega329/649

GND

PF7 (ADC7/TDI)

PF6 (ADC6/TDO)

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

PC5 (SEG7)

PC4 (SEG8)

PC3 (SEG9)

PC2 (SEG10)

PC1 (SEG11)

PC0 (SEG12)

PG1 (SEG13)

PG0 (SEG14)

VCC

GND

RESET/PG5

(T0/SEG23) PG4

(T1/SEG24) PG3

(OC2A/PCINT15) PB7

(TOSC1) XTAL1

(TOSC2) XTAL2

(ICP1/SEG22) PD0

(SEG18) PD4

(SEG19) PD3

(SEG20) PD2

(INT0/SEG21) PD1

(SEG16) PD6

(SEG17) PD5

(SEG15) PD7

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally

connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

Disclaimer Typical values contained in this datasheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

2552H–AVR–11/06

Overview

The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 3. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF

AVR CPU

PORTF DRIVERS

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

ALU

STATUS

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

CONTROLLER/

LCD

DRIVER

XTAL1

XTAL2

RESET

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

COMPARATOR

DATA REGISTER

USART

PORTE

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

DATA REGISTER

PORTB

ATmega329/3290/649/6490

REG. PORTB

PORTB DRIVERS

PB0 - PB7PE0 - PE7

DATA DIR.

SPI

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

2552H–AVR–11/06

ATmega329/3290/649/6490

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of InSystem Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal contrast control, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega329/3290/649/6490 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

2552H–AVR–11/06

Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490

The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and pinout. Table 1 on page 6 summarizes the different configurations for the four devices.

Table 1 . Configuration Summary

LCD

Device Flash EEPROM RAM

ATmega329 32K bytes 1K bytes 2K bytes 4 x 25 54

ATmega3290 32K bytes 1K bytes 2K bytes 4 x 40 69

ATmega649 64K bytes 2K bytes 4K bytes 4 x 25 54

ATmega6490 64K bytes 2K bytes 4K bytes 4 x 40 69

Segments

Pin Descriptions The following section describes the I/O-pin special functions.

General Purpose I/O Pins

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Digital supply voltage.

bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 67.

bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 68.

bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed on page 71.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

ATmega329/3290/649/6490

2552H–AVR–11/06

ATmega329/3290/649/6490

Port D also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 73.

Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75.

Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75.

Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3290/6490 as listed on page 75.

Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3290/6490 as listed on page 75.

ESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table 16 on page 41. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2552H–AVR–11/06

XTAL2 Output from the inverting Oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally

connected to V nected to V

AREF This is the analog reference pin for the A/D Converter.

LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as

shown in Figure 99. This capacitor acts as a reservoir for LCD power (V capacitance reduces ripple on V value.

, even if the ADC is not used. If the ADC is used, it should be con-

through a low-pass filter.

but increases the time until V

LCD

reaches its target

LCD

). A large

LCD

Resources A comprehensive set of development tools, application notes and datasheets are avail-

able for download on http://www.atmel.com/avr.

About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

ATmega329/3290/649/6490

2552H–AVR–11/06

ATmega329/3290/649/6490

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview Figure 4. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Status

and Control

32 x 8 General Purpose

Registrers

ALU

Indirect Addressing

Data

SRAM

EEPROM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

2552H–AVR–11/06

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File,

the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

ALU – Arithmetic Logic Unit

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega329/3290/649/6490 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

ATmega329/3290/649/6490

2552H–AVR–11/06

ATmega329/3290/649/6490

AVR Status Register The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

SREG – AVR Status Register The AVR Status Register – SREG – is defined as:

Bit 76543210

0x3F (0x5F) ITHSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

2552H–AVR–11/06

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 5 shows the structure of the 32 general purpose working registers in the CPU.

Figure 5. AVR CPU General Purpose Working Registers

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 5, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

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The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6.

Figure 6. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit 151413121110 9 8

0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

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Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk

, directly generated from the selected clock

CPU

source for the chip. No internal clock division is used.

Figure 7 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 7. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

clk

CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 8 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Reset and Interrupt Handling

Figure 8. Single Cycle ALU Operation

T1 T2 T3 T4

clk

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 281 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 49. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 49 for more information. The Reset Vector can also be

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moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 268.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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AVR ATmega329/3290/649/6490 Memories

This section describes the different memories in the ATmega329/3290/649/6490. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega329/3290/649/6490 features an EEPROM Memory for data storage. All three memory spaces are linear.

ATmega329/3290/649/6490

In-System Reprogrammable Flash Program Memory

The ATmega329/3290/649/6490 contains 32/64K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16/32K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega329/3290/649/6490 Program Counter (PC) is 14/15 bits wide, thus addressing the 16/32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 268. “Memory Programming” on page 281 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 14.

Figure 9. Program Memory Map

Program Memory

0x0000

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Application Flash Section

Boot Flash Section

0x3FFF/0x7FFF

SRAM Data Memory Figure 10 shows how the ATmega329/3290/649/6490 SRAM Memory is organized.

The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2304/4352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 2048/4096 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2,048 bytes of internal data SRAM in the ATmega329/3290/649/6490 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 12.

Figure 10. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(2048 x 8)/ (4096 x 8)

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clk

11.

0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00F

0x0100

0x08FF/0x10FF

cycles as described in Figure

CPU

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ATmega329/3290/649/6490

Figure 11. On-chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

Address

Data

Compute Address

Address valid

Write

Data

Memory Access Instruction

Next Instruction

Read

EEPROM Data Memory The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory. It is

organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 296, page 301, and page 284 respectively.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

23. for details on how to avoid problems in these situations.

is likely to rise or fall slowly on power-up/down. This

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In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

EEARH and EEARL – The EEPROM Address Register

Bit 151413121110 9 8

0x22 (0x42) – – – – – EEAR10 EEAR9 EEAR8 EEARH

0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRR/WR/WR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 X X X

XXXXXXXX

• Bits 15:11 – Res: Reserved Bits

These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.

• Bits 10:0 – EEAR10:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 1/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023/2047. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

Note: EEAR10 is only valid for ATmega649 and ATmega6490.

EEDR – The EEPROM Data Register

EECR – The EEPROM Control Register

Bit 76543210

0x20 (0x40) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit 76543210

0x1F (0x3F) ––––EERIEEEMWEEEWEEEREEECR

Read/Write R R R R R/W R/W R/W R/W

Initial Value000000X0

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

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ATmega329/3290/649/6490

Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” on page 268 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical programming time for EEPROM access from the CPU.

Table 2 . EEPROM Programming Time

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Number of Calibrated

Symbol

EEPROM write (from CPU) 27,072 3.4 ms

RC Oscillator Cycles Typical Programming Time

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

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Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

EEPROM Write During Powerdown Sleep Mode

Preventing EEPROM Corruption

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When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the clock continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down.

During periods of low V

the EEPROM data can be corrupted because the supply volt-

CC,

age is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection

level of the internal BOD does not match the needed detection level, an external low V

reset Protection circuit can be used. If a reset occurs while a write operation is in

progress, the write operation will be completed provided that the power supply voltage is sufficient.

I/O Memory The I/O space definition of the ATmega329/3290/649/6490 is shown in “Register Sum-

mary” on page 350.

All ATmega329/3290/649/6490 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

General Purpose I/O Registers The ATmega329/3290/649/6490 contains three General Purpose I/O Registers. These

registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

GPIOR2 – General Purpose I/O Register 2

Bit 76543210

0x2B (0x4B) MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

GPIOR1 – General Purpose I/O Register 1

Bit 76543210

0x2A (0x4A) MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

GPIOR0 – General Purpose I/O Register 0

Bit 76543210

0x1E (0x3E) MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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System Clock and Clock Options

ATmega329/3290/649/6490

Clock Systems and their Distribution

Figure 12 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. The clock systems are detailed below.

Figure 12. Clock Distribution

LCD Controller

Asynchronous Timer/Counter

General I/O

Modules

clk

ASY

CPU Core RAM

I/O

AVR Clock

Control Unit

Source clock

Clock

Multiplexer

clk

CPU

clk

FLASH

Reset Logic

Watchdog Timer

Watchdog clock

Watchdog

Oscillator

Flash and EEPROM

CPU Clock – clk

I/O Clock – clk

Flash Clock – clk

CPU

I/O

FLASH

Asynchronous Timer Clock – clk

ASY

Timer/Counter

Oscillator

External Clock

Crystal

Oscillator

Low-frequency

Crystal Oscillator

Calibrated RC

Oscillator

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clk

is halted, enabling USI start condition

I/O

detection in all sleep modes.

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. It also allows the LCD controller output to continue while the rest of the device is in sleep mode.

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ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as

shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 3 . Device Clocking Options Select

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1000

External Low-frequency Crystal 0111 - 0110

Calibrated Internal RC Oscillator 0010

External Clock 0000

Reserved 0011, 0001, 0101, 0100

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

(1)

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 4. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega329/3290/649/6490 Typical Characteristics – Preliminary Data” on page 320.

Table 4 . Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K (65,536)

Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed.

The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer.

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can

be configured for use as an On-chip Oscillator, as shown in Figure 13. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 5. For ceramic resonators, the capacitor values given by the manufacturer should be used.

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Figure 13. Crystal Oscillator Connections

XTAL2

XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5.

Table 5 . Crystal Oscillator Operating Modes

Frequency Range

CKSEL3..1

(1)

100

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

(MHz)

0.4 - 0.9 –

Recommended Range for Capacitors C1

and C2 for Use with Crystals (pF)

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 6.

Table 6 . Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

CKSEL0 SUT1..0

000 258 CK

001 258 CK

010 1K CK

011 1K CK

100 1K CK

01 16K CK 14CK Crystal Oscillator,

10 16K CK 14CK + 4.1 ms Crystal Oscillator, fast

11 16K CK 14CK + 65 ms Crystal Oscillator,

Power-save

(1)

(2)

Additional Delay

from Reset

(VCC = 5.0V)

14CK + 4.1 ms Ceramic resonator,

14CK + 65 ms Ceramic resonator,

14CK Ceramic resonator,

14CK + 4.1 ms Ceramic resonator,

14CK + 65 ms Ceramic resonator,

Recommended Usage

fast rising power

slowly rising power

BOD enabled

fast rising power

slowly rising power

BOD enabled

rising power

slowly rising power

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Notes: 1. These options should only be used when not operating close to the maximum fre-

quency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

Low-frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111”. The crystal should be connected as shown in Figure 13. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7 and CKSEL1..0 as shown in Table 8.

Table 7 . Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Recommended Usage

00 14CK Fast rising power or BOD enabled

01 14CK + 4.1 ms Slowly rising power

10 14CK + 65 ms Stable frequency at start-up

11 Reserved

Table 8 . Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

Start-up Time from

CKSEL3..0

(1)

0110

0111 32K CK Stable frequency at start-up

Note: 1. This option should only be used if frequency stability at start-up is not important for

the application

Power-down and Power-save Recommended Usage

1K CK

Calibrated Internal RC Oscillator

ATmega329/3290/649/6490

The calibrated Internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nominal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 31 for more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9 on page 29. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 143 on page 319.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on page 29, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 143 on page 319.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the preprogrammed calibration value, see the section “Calibration Byte” on page 284.

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ATmega329/3290/649/6490

OSCCAL – Oscillator Calibration Register

Table 9 . Internal Calibrated RC Oscillator Operating Modes

Frequency Range

7.3 - 8.1 0010

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8.

(2)

(MHz) CKSEL3..0

(1)(3)

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10 on page 29.

Table 10. Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00

Fast rising power 6 CK 14CK + 4.1 ms 01

Slowly rising power 6 CK 14CK + 65 ms

Note: 1. The device is shipped with this option selected.

Bit 76543210

(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

down and Power-save

Reserved 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

(1)

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 143 on page 319. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 143 on page 319. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range.

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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in

Figure 14. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Figure 14. External Clock Drive Configuration

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12.

Table 11. Crystal Oscillator Clock Frequency

CKSEL3..0 Frequency Range

0000 0 - 16 MHz

Table 12. Start-up Times for the External Clock Selection

Start-up Time from Power-

SUT1..0

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4.1 ms Fast rising power

10 6 CK 14CK + 65 ms Slowly rising power

down and Power-save

Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

11 Reserved

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 31 for details.

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Clock Output Buffer When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This

mode is suitable when the chip clock is used to drive other circuits on the system. The clock will be output also during reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that is output when the CKOUT Fuse is programmed.

Timer/Counter Oscillator ATmega329/3290/649/6490 share the Timer/Counter Oscillator Pins (TOSC1 and

TOSC2) with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when the calibrated internal RC Oscillator is selected as system clock source. The Oscillator is optimized for use with a 32.768 kHz watch crystal. See Figure 13 on page 27 for crystal connection.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. See “Asynchronous operation of the Timer/Counter” on page 147 for further description on selecting external clock as input instead of a 32 kHz crystal.

System Clock Prescaler The ATmega329/3290/649/6490 system clock can be divided by setting the Clock Pres-

cale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O

, clk

ADC

, clk

CPU

, and clk

are divided by a factor as shown in Table 13.

FLASH

CLKPR – Clock Prescale Register

Bit 76543210

(0x61)

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 13.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

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Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 13. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that

no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the state of the prescaler – even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

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Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed, see “SMCR – Sleep Mode Control Register” on page 38. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction. See Table 14 on page 33 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Figure 12 on page 25 presents the different clock systems in the ATmega329/3290/649/6490, and their distribution. The figure is helpful in selecting an appropriate sleep mode.

Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

Sleep Mode

CPU

clk

Idle X X X X X

FLASH

clk

ADC

clkIOclk

ASY

clk

Main Clock

Source

Enabled

Timer Osc

Enabled

INT0 and Pin

Change

(2)

XX XXXXX

USI Start

ADC Noise Reduction X X X X

Powerdown X

Powersave X X

Standby

(1)

(2)

(3)

XXX

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.

3. For INT0, only level interrupt.

Condition

LCD

(2)

Controller

Timer2

SPM/EEPROM

Ready

ADC

Other I/O

(2)

2552H–AVR–11/06

Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

CPU

and clk

, while allowing the

FLASH

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI start condition detection, Timer/Counter2, LCD Controller, and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk clk

, and clk

CPU

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an LCD controller interrupt, USI start condition interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

, while allowing the other clocks to run.

FLASH

I/O

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 54 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock Sources” on page

26.

Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller interrupt.

If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended instead of Power-save mode.

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The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. The clock source for the two modules can be selected independent of each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the LCD controller and Timer/Counter2.

Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 38, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers inaccessible. Resources used by the peripheral when stopping the clock will remain occupied so the peripheral should be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in IDLE mode and active mode to reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

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Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should

be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 203 for details on ADC operation.

Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When

entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 200 for details on how to configure the Analog Comparator.

Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 42 for details on how to configure the Brown-out Detector.

Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-

tion, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 45 for details on the start-up time.

Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off.

If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 45 for details on how to configure the Watchdog Timer.

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.

The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk

) and the ADC clock (clk

I/O

) are stopped, the input buff-

ADC

ers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 64 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V

/2,

the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V

/2 on an input pin can cause significant current even in active

mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-

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ATmega329/3290/649/6490

ters (DIDR1 and DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” on page 202 and “DIDR0 – Digital Input Disable Register 0” on page 219 for details.

JTAG Interface and On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCSR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.

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Register Description

SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Bit 76543210

0x33 (0x53)

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000000

– – – – SM2 SM1 SM0 SE SMCR

• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 15.

Table 15. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

0 0 1 ADC Noise Reduction

010Power-down

011Power-save

100Reserved

101Reserved

110Standby

111Reserved

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

(1)

• Bit 1 – SE: Sleep Enable

PRR – Power Reduction Register

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

Bit 76543210

(0x64)

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

– – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC PRR

• Bits 7, 6, 5 - Res: Reserved bits

These bits are reserved bits in ATmega329/3290/649/6490 and will always read as zero.

• Bit 4 - PRLCD: Power Reduction LCD

Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled and the display discharged before shut down. See "Disabling the LCD" on page 217 for details on how to disable the LCD controller.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

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Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper operation.

• Bit 1 - PRUSART: Power Reduction USART

Writing logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re-initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

Note: The Analog Comparator is disabled using the ACD-bit in the “ACSR – Analog Compara-

tor Control and Status Register” on page 200.

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System Control and Reset

Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts exe-

cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 15 shows the reset logic. Table 16 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 26.

Reset Sources The ATmega329/3290/649/6490 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V Brown-out Reset threshold (V

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “IEEE

1149.1 (JTAG) Boundary-scan” on page 242 for details.

POT

pin for

is below the

) and the Brown-out Detector is enabled.

BOT

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2552H–AVR–11/06

Figure 15. Reset Logic

ATmega329/3290/649/6490

DATA BU S

MCU Status

JTRF

BORF

Power-on Reset

Circuit

PORF

WDRF

EXTRF

BODLEVEL [1..0]

Pull-up Resistor

SPIKE

FILTER

JTAG Reset

Brown-out

Reset Circuit

Watchdog Oscillator

Clock

Generator

CKSEL[3:0]

SUT[1:0]

Delay Counters

TIMEOUT

Table 16. Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

POT

Power-on Reset Threshold Voltage (rising)

Power-on Reset Threshold Voltage (falling)

(1)

TA = -40°C

to 85°C

TA = -40°C

to 85°C

0.7 1.0 1.4 V

0.6 0.9 1.3 V

RST

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V

RESET Pin Threshold Voltage VCC = 3V 0.2 V

Minimum pulse width on RESET

= 3V 800 ns

0.85 V

POT

(falling)

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 16. The POR is activated whenever V

is below the

detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V again, without any delay, when V

decreases below the detection level.

rise. The RESET signal is activated

2552H–AVR–11/06

Figure 16. MCU Start-up, RESET Tied to V

RESET

TIME-OUT

INTERNAL

RESET

POT

RST

TOUT

Figure 17. MCU Start-up, RESET Extended Externally

RESET

TIME-OUT

POT

RST

TOUT

INTERNAL

RESET

External Reset An External Reset is generated by a low level on the RESET

pin. Reset pulses longer than the minimum pulse width (see Table 16) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V counter starts the MCU after the Time-out period – t

– on its positive edge, the delay

RST

TOUT –

has expired.

Figure 18. External Reset During Operation

Brown-out Detection ATmega329/3290/649/6490 has an On-chip Brown-out Detection (BOD) circuit for mon-

itoring the V

level during operation by comparing it to a fixed trigger level. The trigger

level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hys-

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ATmega329/3290/649/6490

teresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V

Table 17. BODLEVEL Fuse Coding

BOT+

= V

BOT

(1)

+ V

HYST

/2 and V

BOT-

= V

BOT

- V

HYST

/2.

BODLEVEL 2:0 Fuses Min V

BOT

Typ V

BOT

Max V

BOT

Units

11 BOD Disabled

10 1.8

V01 2.7

00 4.3

Note: 1. V

may be below nominal minimum operating voltage for some devices. For

BOT

devices where this is the case, the device is tested down to VCC = V

BOT

during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 10 for ATmega329/3290/649/6490V and BODLEVEL = 01 for ATmega329/3290/649/6490L.

Table 18. Brown-out Characteristics

Symbol Parameter Min Typ Max Units

HYST

BOD

When the BOD is enabled, and VCC decreases to a value below the trigger level (V

Brown-out Detector Hysteresis 50 mV

Min Pulse Width on Brown-out Reset 2 µs

BOT-

in Figure 19), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (V out period t

has expired.

TOUT

The BOD circuit will only detect a drop in V for longer than t

BOD

in Figure 19), the delay counter starts the MCU after the Time-

BOT+

if the voltage stays below the trigger level

given in Table 16.

Figure 19. Brown-out Reset During Operation

RESET

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

. Refer to page 45 for details on operation of the Watchdog Timer.

TOUT

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Figure 20. Watchdog Reset During Operation

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 76543210

0x35 (0x55)

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 See Bit Description

– – – JTRF WDRF BORF EXTRF PORF MCUSR

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

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ATmega329/3290/649/6490

Internal Voltage Reference

Voltage Reference Enable Signals and Start-up Time

ATmega329/3290/649/6490 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 19. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [1..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 19. Internal Voltage Reference Characteristics

Symbol Parameter Condition Min Typ Max Units

Bandgap reference voltage VCC = 2.7V,

Bandgap reference start-up time VCC = 2.7V,

(1)

= 25°C

TA= 25°C

1.0 1.1 1.2 V

40 70 µs

Note: 1. Values are guidelines only. Actual values are TBD.

Bandgap reference current consumption

VCC = 2.7V,

TA= 25°C

15 µA

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at

1 MHz. This is the typical value at V at other V

levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset

interval can be adjusted as shown in Table 21 on page 47. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega329/3290/649/6490 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 21 on page 47.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table

20. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer”

on page 48 for details.

Table 20. WDT Configuration as a Function of the Fuse Settings of WDTON

Safety

WDTON

Unprogrammed 1 Disabled Timed sequence Timed sequence

Programmed 2 Enabled Always enabled Timed sequence

Level

WDT Initial State

= 5V. See characterization data for typical values

How to Disable the WDT

How to Change Time-out

2552H–AVR–11/06

Figure 21. Watchdog Timer

WATCHDOG

OSCILLATOR

WDTCR – Watchdog Timer Control Register

Bit 76543210

(0x60) – – – WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

• Bits 7:5 – Res: Reserved Bits

These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 48.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 48.

• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Time-out Periods are shown in Table 21 on page 47.

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Table 21. Watchdog Timer Prescale Select

Number of WDT

WDP2 WDP1 WDP0

0 0 0 16K cycles 17.1 ms 16.3 ms

0 0 1 32K cycles 34.3 ms 32.5 ms

0 1 0 64K cycles 68.5 ms 65 ms

0 1 1 128K cycles 0.14 s 0.13 s

1 0 0 256K cycles 0.27 s 0.26 s

1 0 1 512K cycles 0.55 s 0.52 s

1 1 0 1,024K cycles 1.1 s 1.0 s

1 1 1 2,048K cycles 2.2 s 2.1 s

Oscillator Cycles

Typical Time-out

at VCC = 3.0V

Typical Time-out

at VCC = 5.0V

The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

WDT_off:

; Reset WDT

wdr

; Write logical one to WDCE and WDE

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

(1)

2552H–AVR–11/06

void WDT_off(void)

{

/* Reset WDT */

__watchdog_reset();

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

Note: 1. See “About Code Examples” on page 8.

Timed Sequences for Changing the

The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level.

Configuration of the Watchdog Timer

Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the

WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.

Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read

as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

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ATmega329/3290/649/6490

Interrupts This section describes the specifics of the interrupt handling as performed in

ATmega329/3290/649/6490. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 14.

Interrupt Vectors in ATmega329/3290/649/6490

Table 22. Reset and Interrupt Vectors

Vector

No.

1 0x0000

2 0x0002 INT0 External Interrupt Request 0

3 0x0004 PCINT0 Pin Change Interrupt Request 0

4 0x0006 PCINT1 Pin Change Interrupt Request 1

5 0x0008 TIMER2 COMP Timer/Counter2 Compare Match

6 0x000A TIMER2 OVF Timer/Counter2 Overflow

7 0x000C TIMER1 CAPT Timer/Counter1 Capture Event

8 0x000E TIMER1 COMPA Timer/Counter1 Compare Match A

9 0x0010 TIMER1 COMPB Timer/Counter1 Compare Match B

10 0x0012 TIMER1 OVF Timer/Counter1 Overflow

11 0x0014 TIMER0 COMP Timer/Counter0 Compare Match

12 0x0016 TIMER0 OVF Timer/Counter0 Overflow

13 0x0018 SPI, STC SPI Serial Transfer Complete

14 0x001A USART, RX USART0, Rx Complete

15 0x001C USART, UDRE USART0 Data Register Empty

16 0x001E USART, TX USART0, Tx Complete

Program

Address

(2)

Source Interrupt Definition

(1)

RESET External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset, and JTAG AVR Reset

2552H–AVR–11/06

17 0x0020 USI START USI Start Condition

18 0x0022 USI OVERFLOW USI Overflow

19 0x0024 ANALOG COMP Analog Comparator

20 0x0026 ADC ADC Conversion Complete

21 0x0028 EE READY EEPROM Ready

22 0x002A SPM READY Store Program Memory Ready

23 0x002C LCD LCD Start of Frame

(3)

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

0x002E PCINT2 Pin Change Interrupt Request 2

0x0030 PCINT3 Pin Change Interrupt Request 3

address at reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 268.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

3. PCINT2 and PCINT3 are only present in ATmega3290 and ATmega6490.

Table 23 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

Table 23. Reset and Interrupt Vectors Placement

(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002

1 1 0x0000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x0002

0 1 Boot Reset Address Boot Reset Address + 0x0002

Note: 1. The Boot Reset Address is shown in Table 120 on page 280. For the BOOTRST

Fuse “1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega329/3290/649/6490 is:

Address Labels Code Comments

0x0000 jmp RESET ; Reset Handler

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp PCINT0 ; PCINT0 Handler

0x0006 jmp PCINT1 ; PCINT1 Handler

0x0008 jmp TIM2_COMP ; Timer2 Compare Handler

0x000A jmp TIM2_OVF ; Timer2 Overflow Handler

0x000C jmp TIM1_CAPT ; Timer1 Capture Handler

0x000E jmp TIM1_COMPA ; Timer1 CompareA Handler

0x0010 jmp TIM1_COMPB ; Timer1 CompareB Handler

0x0012 jmp TIM1_OVF ; Timer1 Overflow Handler

0x0014 jmp TIM0_COMP ; Timer0 Compare Handler

0x0016 jmp TIM0_OVF ; Timer0 Overflow Handler

0X0018 jmp SPI_STC ; SPI Transfer Complete Handler

0x001A jmp USART_RXC ; USART0 RX Complete Handler

0x001C jmp USART_UDRE ; USART0,UDR0 Empty Handler

0x001E jmp USART_TXC ; USART0 TX Complete Handler

0x0020 jmp USI_STRT ; USI Start Condition Handler

0x0022 jmp USI_OVF ; USI Overflow Handler

0x0024 jmp ANA_COMP ; Analog Comparator Handler

0x0026 jmp ADC ; ADC Conversion Complete Handler

0x0028 jmp EE_RDY ; EEPROM Ready Handler

0x002A jmp SPM_RDY ; SPM Ready Handler

0x002C jmp LCD_SOF ; LCD Start of Frame Handler

0x002E jmp PCINT2 ; PCINT2 Handler

0x0030 jmp PCINT3 ; PCINT3 Handler

;

0x0032 RESET: ldi r16, high(RAMEND) ; Main program start

0x0033 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0034 ldi r16, low(RAMEND)

0x0035 out SPL,r16

0x0036 sei ; Enable interrupts

0x0037 <instr> xxx

... ... ...

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ATmega329/339/649/659

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

0x0000 RESET: ldi r16,high(RAMEND); Main program start

0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0002 ldi r16,low(RAMEND)

0x0003 out SPL,r16 0x0004 sei ; Enable interrupts

0x0005 <instr> xxx

;

.org 0x3802/0x7802

0x3804/0x7804 jmp EXT_INT0 ; IRQ0 Handler

0x3806/0x7806 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 4K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

.org 0x0002

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x002C jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0x3800/0x7800 0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start

0x3801/0x7801 out SPH,r16 ; Set Stack Pointer to top of RAM

0x3802/0x7802 ldi r16,low(RAMEND)

0x3803/0x7803 out SPL,r16 0x3804/0x7804 sei ; Enable interrupts

0x3805/0x7805 <instr> xxx

2552H–AVR–11/06

When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

;

.org 0x3800/0x7800 0x3800/0x7800 jmp RESET ; Reset handler 0x3802/0x7802 jmp EXT_INT0 ; IRQ0 Handler

0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler

... ... ... ;

0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start

0x382F/0x782F out SPH,r16 ; Set Stack Pointer to top of RAM

0x3830/0x7830 ldi r16,low(RAMEND)

0x3831/0x7831 out SPL,r16 0x3832/0x7832 sei ; Enable interrupts

0x3833/0x7833 <instr> xxx

Moving Interrupts Between Application and Boot Space

MCUCR – MCU Control Register

The MCU Control Register controls the placement of the Interrupt Vector table.

Bit 76543210

0x35 (0x55)

Read/Write R/W R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

JTD – – PUD – – IVSEL IVCE MCUCR

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 268 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 268 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.

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ATmega329/339/649/659

Assembly Code Example

Move_interrupts:

;Get MCUCR

in r16, MCUCR

mov r17, r16

; Enable change of Interrupt Vectors

ori r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ori r17, (1<<IVSEL)

out MCUCR, r17

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR |= (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR |= (1<<IVSEL);

}

2552H–AVR–11/06

External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK3, PCMSK2, PCMSK1, and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT30..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Register A – EICRA. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 25. Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 25.

Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 22.

Figure 22. Pin Change Interrupt

PCINT(0)

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pin_lat

D Q

clk

pin_sync

PCINT(0) in PCMSK(x)

pcint_in_(0)

clk

pcint_syn

pcint_setflag

PCIF

pcint_setflag

PCIF

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ATmega329/3290/649/6490

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210

(0x69)

Read/WriteRRRRRRR/WR/W

Initial Value00000000

– – – – – – ISC01 ISC00 EICRA

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 24. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.

Table 24. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

2552H–AVR–11/06

External Interrupt Mask Register – EIMSK

Bit 76543210

PCIE3 PCIE2 PCIE1 PCIE0

Read/Write R/W R/W R/W R/W R R R R/W

Initial Value 0 0 0 0 0 0 0 0

– – –INT0EIMSK

• Bit 7 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT3 Interrupt Vector. PCINT30..24 pins are enabled individually by the PCMSK3 Register.

This bit is reserved bit in ATmega329/649 and should always be written to zero.

• Bit 6 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT2 Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

This bit is reserved bit in ATmega329/649 and should always be written to zero.

• Bit 5 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

• Bit 4 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCINT0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.

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EIFR – External Interrupt Flag Register

Bit 76543210

0x1C (0x3C) PCIF3 PCIF2 PCIF1 PCIF0

Read/Write R/W R/W R/W R/W R R R R/W

Initial Value 0 0 0 0 0 0 0 0

– – – INTF0 EIFR

• Bit 7 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT30..24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega329/649 and will always be read as zero.

• Bit 6 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

This bit is reserved bit in ATmega329/649 and will always be read as zero.

• Bit 5 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 4 – PCIF0: Pin Change Interrupt Flag 0

PCMSK3 – Pin Change Mask Register 3

(1)

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.

Bit 76543210

(0x73)

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

– PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 PCMSK3

• Bit 6:0 – PCINT30..24: Pin Change Enable Mask 30..24

Each PCINT30..24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT30..24 is set and the PCIE3 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT30..24 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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PCMSK2 – Pin Change Mask Register 2

(1)

Bit 76543210

(0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value

00000000

• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16

Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

Note: 1. PCMSK3 and PCMSK2 are only present in ATmega3290/6490.

PCMSK1 – Pin Change Mask Register 1

PCMSK0 – Pin Change Mask Register 0

Bit 76543210

(0x6C)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15:8

Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

Bit 76543210

(0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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I/O-Ports

Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital

I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. Port B has a higher pin driver strength than the other ports, but all the pin drivers are strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supplyvoltage invariant resistance. All I/O pins have protection diodes to both V as indicated in Figure 23. Refer to “Electrical Characteristics” on page 313 for a complete list of parameters. If exceeding the pin voltage “Absolute Maximum Ratings”, resulting currents can harm the device if not limited accordingly. For segment pins used as general I/O, the same situation can also influence the LCD voltage level.

Figure 23. I/O Pin Equivalent Schematic

and Ground

Pxn

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 86.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

See Figure

"General Digital I/O" for

Logic

Details

2552H–AVR–11/06

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 60. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described

in “Alternate Port Functions” on page 65. Refer to the individual module sections for a full description of the alternate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 24 shows a functional description of one I/O-port pin, here generically called Pxn.

Figure 24. General Digital I/O

Pxn

(1)

SLEEP

SYNCHRONIZER

DLQ

PINxn

PUD

Q D

DDxn

CLR

RESET

Q D

PORTxn

CLR

RESET

RRx

WDx

RDx

DATA B U S

WPx

WRx

RPx

clk

I/O

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk

: I/O CLOCK

I/O

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clk

, SLEEP, and PUD are common to all ports.

I/O

Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 86, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

Toggli n g th e P in Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of

DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 25 summarizes the control signals for the pin value.

Table 25. Port Pin Configurations

PUD

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

(in MCUCR) I/O Pull-up Comment

Pxn will source current if ext. pulled low.

Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 24, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 25 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t

pd,max

and t

pd,min

respectively.

2552H–AVR–11/06

Figure 25. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX in r17, PINx

XXX

0x00 0xFF

pd, max

pd, min

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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 26. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 26. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r16

out PORTx, r16 nop in r17, PINx

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

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Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time

from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable and Sleep Modes

As shown in Figure 24, the digital input signal can be clamped to ground at the input of the Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V

/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 65.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined

level. Even though most of the digital inputs are disabled in the deep sleep modes as

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described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to V cause excessive currents if the pin is accidentally configured as an output.

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure

27 shows how the port pin control signals from the simplified Figure 24 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

or GND is not recommended, since this may

Figure 27. Alternate Port Functions

PUOExn

Pxn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

(1)

SYNCHRONIZER

SET

DLQ

PINxn

CLR

PUD

DDxn

CLR

RESET

Q D

PORTxn

CLR

RESET

CLR

WDx

RDx

RRx

RPx

clk

PTOExn

WRx

WPx

I/O

DATA BU S

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DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk

: I/O CLOCK

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

, SLEEP, and PUD are common to all ports. All other signals are unique for each

clk

I/O

pin.

Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 27 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.

Table 26. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE Pull-up Override

Enable

PUOV Pull-up Override

Valu e

DDOE Data Direction

Override Enable

DDOV Data Direction

Override Value

PVOE Port Value

Override Enable

PVOV Port Value

Override Value

PTOE Port Toggle

Override Enable

DIEOE Digital Input

Enable Override Enable

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

DIEOV Digital Input

Enable Override Valu e

DI Digital Input This is the Digital Input to alternate functions. In the

AIO Analog

Input/Output

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

Some pins are connected to different LCS segments on ATmega3290/6490 and ATmega3290/6490. See pinout on “Pinout ATmega3290/6490” on page 2 and “Pinout ATmega329/649” on page 3 for details.

ATmega329/3210/649/6410

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.

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ATmega329/3210/649/6410

MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0

0x35 (0x55)

Read/Write R/W R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

JTD – –PUD– – IVSEL IVCE MCUCR

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 60 for more details about this feature.

Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller.

Table 27. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7 SEG (LCD Front Plane 3)

PA6 SEG (LCD Front Plane 2)

PA5 SEG (LCD Front Plane 1)

PA4 SEG (LCD Front Plane 0)

PA3 COM (LCD Back Plane 3)

PA2 COM (LCD Back Plane 2)

PA1 COM (LCD Back Plane 1)

PA0 COM (LCD Back Plane 0)

Table 28 and Table 29 relates the alternate functions of Port A to the overriding signals shown in Figure 27 on page 65.

Table 28. Overriding Signals for Alternate Functions in PA7..PA4

Signal Name PA7/SEG3 PA6/SEG2 PA5/SEG1 PA4/SEG0

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN LCDEN LCDEN LCDEN

DIEOV0000

DI––––

AIO LCDSEG LCDSEG LCDSEG LCDSEG

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Table 29. Overriding Signals for Alternate Functions in PA3..PA0

Signal Name PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0

PUOE LCDEN •

(LCDMUX)

PUOV0000

DDOE LCDEN •

(LCDMUX)

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN •

(LCDMUX)

DIEOV0000

DI––––

AIOCOM3COM2COM1COM0

LCDEN • (LCDMUX)

Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 30.

Table 30. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7

OC2A/PCINT15 Pin Change Interrupt15).

(Output Compare and PWM Output A for Timer/Counter2 or

LCDEN

PB6

PB5

PB4

PB3

PB2

PB1 SCK/PCINT9

PB0 SS/PCINT8

OC1B/PCINT Pin Change Interrupt14).

OC1A/PCINT13 Pin Change Interrupt13).

OC0A/PCINT12 Pin Change Interrupt12).

MISO/PCINT11 Interrupt11).

MOSI/PCINT10 Interrupt10).

14 (Output Compare and PWM Output B for Timer/Counter1 or

(Output Compare and PWM Output A for Timer/Counter1 or

(Output Compare and PWM Output A for Timer/Counter0 or

(SPI Bus Master Input/Slave Output or Pin Change

(SPI Bus Master Output/Slave Input or Pin Change

(SPI Bus Serial Clock or Pin Change Interrupt9).

(SPI Slave Select input or Pin Change Interrupt8).

The alternate pin configuration is as follows:

• OC2A/PCINT15, Bit 7

OC2, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

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PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt source.

• OC1B/PCINT14, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.

• OC1A/PCINT13, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt source.

• OC0A/PCINT12, Bit 4

OC0A, Output Compare Match A output: The PB4 pin can serve as an external output for the Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt source.

• MISO/PCINT11 – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external interrupt source.

• MOSI/PCINT10 – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external interrupt source.

• SCK/PCINT9 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.

2552H–AVR–11/06

PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source.

•SS/PCINT8 – Port B, Bit 0

: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit

PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.

Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals shown in Figure 27 on page 65. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Table 31. Overriding Signals for Alternate Functions in PB7:PB4

Signal Name

PUOE0000

PUOV0000

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE OC2A ENABLE OC1B ENABLE OC1A ENABLE OC0A ENABLE

PVOV OC2A OC1B OC1A OC0A

PTOE––––

DIEOE PCINT15 •

DIEOV1111

DI PCINT15 INPUT PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT

AIO––––

PB7/OC2A/ PCINT15

PCIE1

PB6/OC1B/ PCINT14

PCINT14 • PCIE1

PB5/OC1A/ PCINT13

PCINT13 • PCIE1

PB4/OC0A/ PCINT12

PCINT12 • PCIE1

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Table 32. Overriding Signals for Alternate Functions in PB3:PB0

Signal Name

PUOE SPE • MSTR SPE • MSTR

PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR

PVOV SPI SLAVE

PTOE––––

DIEOE PCINT11 •

DIEOV1111

DI PCINT11 INPUT

AIO––––

PB3/MISO/ PCINT11

OUTPUT

PCIE1

SPI MSTR INPUT

PB2/MOSI/ PCINT10

SPE • MSTR SPE • MSTR 0

SPI MSTR OUTPUT

PCINT10 • PCIE1

PCINT10 INPUT SPI SLAVE

INPUT

PB1/SCK/ PCINT9

SPE • MSTR SPE • MSTR

SCK OUTPUT 0

PCINT9 • PCIE1 PCINT8 • PCIE1

PCINT9 INPUT SCK INPUT

Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller.

PB0/SS/ PCINT8

PCINT8 INPUT SPI SS

Table 33. Port C Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout)

Port Pin Alternate Function

PC7 SEG (LCD Front Plane 5/5)

PC6 SEG (LCD Front Plane 6/6)

PC5 SEG (LCD Front Plane 11/7)

PC4 SEG (LCD Front Plane 12/8)

PC3 SEG (LCD Front Plane 13/9)

PC2 SEG (LCD Front Plane14/10)

PC1 SEG (LCD Front Plane 15/11)

PC0 SEG (LCD Front Plane 16/12)

The alternate pin configuration is as follows:

• SEG – Port D, Bit 7:0

SEG, LCD front plane 5/5, 6/6, 11/7-16/12.

Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals shown in Figure 27 on page 65.

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Table 34. Overriding Signals for Alternate Functions in PC7:PC4

Signal Name PC7/SEG5 PC6/SEG6 PC5/SEG(11/7) PC4/SEG(12/8)

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN LCDEN LCDEN LCDEN

DIEOV0000

DI––––

AIO LCDSEG LCDSEG LCDSEG LCDSEG

Table 35. Overriding Signals for Alternate Functions in PC3:PC0

Signal Name PC3/SEG(13/9) PC2/SEG(14/10) PC1/SEG(15/11) PC0/SEG(16/12)

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN LCDEN LCDEN LCDEN

DIEOV0000

DI––––

AIO LCDSEG LCDSEG LCDSEG LCDSEG

ATmega329/3210/649/6410

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ATmega329/3210/649/6410

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 36.

Table 36. Port D Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout)

Port Pin Alternate Function

PD7 SEG (LCD front plane 19/15)

PD6 SEG (LCD front plane 20/16)

PD5 SEG (LCD front plane 21/17)

PD4 SEG (LCD front plane 22/18)

PD3 SEG (LCD front plane 23/19)

PD2 SEG (LCD front plane 24/20)

PD1 INT0

PD0 ICP1/SEG (Timer/Counter1 Input Capture pin or LCD front plane 26/22)

The alternate pin configuration is as follows:

• SEG – Port D, Bit 7:2

SEG, LCD front plane 19/15-24/20.

•INT0

/SEG – Port D, Bit 1

/SEG (External Interrupt0 Input or LCD front plane 25/21)

INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the MCU.

SEG, LCD front plane 25/21.

• ICP1/SEG – Port D, Bit 0

ICP1 – Input Capture pin1: The PD0 pin can act as an Input Capture pin for Timer/Counter1.

SEG, LCD front plane 26/22

Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals shown in Figure 27 on page 65.

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Table 37. Overriding Signals for Alternate Functions PD7:PD4

Signal Name PD7/SEG(19/15) PD6/SEG(20/16) PD5/SEG(21/17) PD4/SEG(22/18)

PUOE LCDEN •

(LCDPM)

PUOV0000

DDOE LCDEN •

(LCDPM)

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN •

(LCDPM)

DIEOV0000

DI––––

AIO LCDSEG LCDSEG LCDSEG LCDSEG

LCDEN • (LCDPM)

Table 38. Overriding Signals for Alternate Functions in PD3:PD0

Signal Name PD3/SEG(23/19) PD2/SEG(24/20)

PUOE LCDEN •

(LCDPM)

PUOV0000

LCDEN • (LCDPM)

PD1/INT0/ SEG(25/21)

LCDEN • (LCDPM)

PD0/ICP1/ SEG(26/22)

LCDEN • (LCDPM)

DDOE LCDEN •

(LCDPM)

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN •

(LCDPM)

DIEOV 0 0 LCDEN

DI – – INT0 INPUT ICP1 INPUT

AIO LCDSEG LCDSEG LCDSEG LCDSEG

ATmega329/3210/649/6410

LCDEN • (LCDPM)

LCDEN + (INT0 ENABLE)

•

(INT0 ENABLE)

LCDEN • (LCDPM)

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Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 39.

Table 39. Port E Pins Alternate Functions

Port Pin Alternate Function

PE7

PE6 DO/PCINT6 (USI Data Output or Pin Change Interrupt6)

PE5 DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5)

PE4

PE3 AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3)

PE2

PE1 TXD/PCINT1 (USART0 Transmit Pin or Pin Change Interrupt1)

PE0 RXD/PCINT0 (USART0 Receive Pin or Pin Change Interrupt0)

PCINT7 (Pin Change Interrupt7) CLKO (Divided System Clock)

USCK/SCL/PCINT4 (USART0 External Clock Input/Output or TWI Serial Clock or Pin Change Interrupt4)

XCK/AIN0/ PCINT2 (USART0 External Clock or Analog Comparator Positive Input or Pin Change Interrupt2)

• PCINT7 – Port E, Bit 7

PCINT7, Pin Change Interrupt Source 7: The PE7 pin can serve as an external interrupt source.

CLKO, Divided System Clock: The divided system clock can be output on the PE7 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTE7 and DDE7 settings. It will also be output during reset.

• DO/PCINT6 – Port E, Bit 6

DO, Universal Serial Interface Data output.

PCINT6, Pin Change Interrupt Source 6: The PE6 pin can serve as an external interrupt source.

• DI/SDA/PCINT5 – Port E, Bit 5

DI, Universal Serial Interface Data input.

SDA, Two-wire Serial Interface Data:

PCINT5, Pin Change Interrupt Source 5: The PE5 pin can serve as an external interrupt source.

• USCK/SCL/PCINT4 – Port E, Bit 4

USCK, Universal Serial Interface Clock.

SCL, Two-wire Serial Interface Clock.

PCINT4, Pin Change Interrupt Source 4: The PE4 pin can serve as an external interrupt source.

• AIN1/PCINT3 – Port E, Bit 3

AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator.

PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source.

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• XCK/AIN0/PCINT2 – Port E, Bit 2

XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 operates in synchronous mode.

AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator.

PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.

• TXD/PCINT1 – Port E, Bit 1

TXD0, UART0 Transmit pin.

PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source.

• RXD/PCINT0 – Port E, Bit 0

RXD, USART0 Receive pin. Receive Data (Data input pin for the USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.

PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source.

Table 40 and Table 41 relates the alternate functions of Port E to the overriding signals shown in Figure 27 on page 65.

Table 40. Overriding Signals for Alternate Functions PE7:PE4

Signal Name PE7/PCINT7

PUOE 0 0 USI_TWO-WIRE USI_TWO-WIRE

PUOV0000

DDOE CKOUT

DDOV 1 0 (SDA

PVOE CKOUT

PVOV clk

PTOE – – 0 USITC

DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 (PCINT5 •

DIEOV1111

DI PCINT7 INPUT PCINT6 INPUT DI/SDA INPUT

AIO––––

(1)

I/O

PE6/DO/ PCINT6

0 USI_TWO-WIRE USI_TWO-WIRE

USI_THREEWIRE

DO 0 0

PE5/DI/SDA/ PCINT5

+ PORTE5 DDE5

USI_TWO-WIRE

• DDE5

PCIE0) + USISIE

PCINT5 INPUT

) •

PE4/USCK/SCL/ PCINT4

(USI_SCL_HOL D + PORTE4) • DDE4

USI_TWO-WIRE

• DDE4

(PCINT4 • PCIE0) + USISIE

USCKL/SCL INPUT

PCINT4 INPUT

Note: 1. CKOUT is one if the CKOUT Fuse is programmed

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Table 41. Overriding Signals for Alternate Functions in PE3:PE0

Signal Name

PUOE 0 XCK OUTPUT

PUOV 0 XCK 0 PORTE0 • PUD

DDOE 0 0 TXEN RXEN

DDOV 0 0 1 0

PVOE 0 0 TXEN 0

PVOV 0 0 TXD 0

PTOE––––

DIEOE (PCINT3 •

DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 1 1

DI PCINT3 INPUT XCK/PCINT2

AIO AIN1 INPUT AIN0 INPUT – –

Note: 1. AIN0D and AIN1D is described in “DIDR1 – Digital Input Disable Register 1” on page

202.

PE3/AIN1/ PCINT3

PCIE0) +

(1)

AIN1D

PE2/XCK/AIN0/ PCINT2

ENABLE

(PCINT2 • PCIE0) +

(1)

AIN0D

INPUT

PE1/TXD/ PCINT1

TXEN RXEN

PCINT1 • PCIE0 PCINT0 • PCIE0

PCINT1 INPUT RXD/PCINT0

PE0/RXD/PCINT 0

INPUT

Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 42.

If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.

Table 42. Port F Pins Alternate Functions

Port Pin Alternate Function

PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

PF5 ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)

PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

PF3 ADC3 (ADC input channel 3)

PF2 ADC2 (ADC input channel 2)

PF1 ADC1 (ADC input channel 1)

PF0 ADC0 (ADC input channel 0)

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

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• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5

TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• ADC3 - ADC0 – Port F, Bit 3:0

Analog to Digital Converter, Channel 3-0.

Table 43. Overriding Signals for Alternate Functions in PF7:PF4

Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK

PUOE JTAGEN JTAGEN JTAGEN JTAGEN

PUOV1111

D D OE J TAG E N J TA GE N J TA G EN J TAG E N

DDOV 0 SHIFT_IR +

SHIFT_DR

PVOE 0 JTAGEN 0 0

PVOV 0 TDO 0 0

PTOE––––

D I EO E J TA GE N J TAG E N J TA GE N J TA G EN

DIEOV0000

DI––––

AIO TDI

ADC7 INPUT

ADC6 INPUT TMS

TCK

ADC5 INPUT

ADC4 INPUT

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Table 44. Overriding Signals for Alternate Functions in PF3:PF0

Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0

PUOE0000

PUOV0000

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE0000

DIEOV0000

DI––––

AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

Alternate Functions of Port G The alternate pin configuration is as follows:

Table 45. Port G Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout)

Port Pin Alternate Function

PG5 RESET

PG4 T0/SEG (Timer/Counter0 Clock Input or LCD Front Plane 32/23)

PG3 T1/SEG (Timer/Counter1 Clock Input or LCD Front Plane 33/24)

PG2 SEG (LCD Front Plane 4/4)

PG1 SEG (LCD Front Plane 17/13)

PG0 SEG (LCD Front Plane 18/14)

Note: 1. Port G, PG5 is input only. Pull-up is always on.

See Table 125 on page 282 for RSTDISBL fuse.

(1)

The alternate pin configuration is as follows:

• RESET

RESET

– Port G, Bit 5

: External Reset input. When the RSTDISBL Fuse is programmed (‘0’), PG5 will

function as input with pull-up always on.

• T0/SEG – Port G, Bit 4

T0, Timer/Counter0 Counter Source.

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SEG, LCD front plane 32/23.

• T1/SEG24 – Port G, Bit 3

T1, Timer/Counter1 Counter Source.

SEG, LCD front plane 33/24.

• SEG – Port G, Bit 2

SEG, LCD front plane 4/4.

• SEG – Port G, Bit 1

SEG, Segment driver 17/13.

• SEG – Port G, Bit 0

SEG, LCD front plane 18/14.

Table 45 and Table 46 relates the alternate functions of Port G to the overriding signals shown in Figure 27 on page 65.

Table 46. Overriding Signals for Alternate Functions in PG4

Signal Name

PUOE LCDEN

PUOV 0

DDOE LCDEN

DDOV 1

PVOE 0

PVOV 0

PTOE –

DIEOE LCDEN •

DIEOV 0

DI T0 INPUT

AIO LCDSEG

PG4/T0/ SEG(32/23)

(LCDPM)

Table 47. Overriding Signals for Alternate Functions in PG3:0

Signal Name

PG3/T1/ SEG(33/24) PG2/SEG(4/4) PG1/SEG(17/13) PG0/SEG(1814)

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE LCDEN •

(LCDPM)

DIEOV0000

DI T1 INPUT – – –

AIO LCDSEG LCDSEG LCDSEG LCDSEG

ATmega329/3210/649/6410

LCDEN LCDEN •

(LCDPM)

LCDEN • (LCDPM)

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Alternate Functions of Port H Port H is only present in ATmega3290/6490. The alternate pin configuration is as

follows:

Table 48. Port H Pins Alternate Functions

Port Pin Alternate Function

PH7 PCINT23/SEG (Pin Change Interrupt23 or LCD Front Plane 36)

PH6 PCINT22/SEG (Pin Change Interrupt22 or LCD Front Plane 37)

PH5 PCINT21/SEG (Pin Change Interrupt21 or LCD Front Plane 38)

PH4 PCINT20/SEG (Pin Change Interrupt20 or LCD Front Plane 39)

PH3 PCINT19/SEG (Pin Change Interrupt19 or LCD Front Plane 7)

PH2 PCINT18/SEG (Pin Change Interrupt18 or LCD Front Plane 8)

PH1 PCINT17/SEG (Pin Change Interrupt17 or LCD Front Plane 9)

PH0 PCINT16/SEG (Pin Change Interrupt16 or LCD Front Plane 10)

The alternate pin configuration is as follows:

• PCINT23/SEG – Port H, Bit 7

PCINT23, Pin Change Interrupt Source 23: The PH7 pin can serve as an external interrupt source.

SEG, LCD front plane 36.

• PCINT22/SEG – Port H, Bit 6

PCINT22, Pin Change Interrupt Source 22: The PH6 pin can serve as an external interrupt source.

SEG, LCD front plane 37.

• PCINT21/SEG – Port H, Bit 5

PCINT21, Pin Change Interrupt Source 21: The PH5 pin can serve as an external interrupt source.

SEG, LCD front plane 38.

• PCINT20/SEG – Port H, Bit 4

PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source.

SEG, LCD front plane 39.

• PCINT19/SEG – Port H, Bit 3

PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve as an external interrupt source.

SEG, LCD front plane 7.

• PCINT18/SEG – Port H, Bit 2

PCINT18, Pin Change Interrupt Source 18: The PH2 pin can serve as an external interrupt source.

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SEG, LCD front plane 8.

• PCINT17/SEG – Port H, Bit 1

PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external interrupt source.

SEG, LCD front plane 9.

• PCINT16/SEG – Port H, Bit 0

PCINT16, Pin Change Interrupt Source 16: The PH0 pin can serve as an external interrupt source.

SEG, LCD front plane 10.

Table 49 and Table 50 relates the alternate functions of Port H to the overriding signals shown in Figure 27 on page 65.

Table 49. Overriding Signals for Alternate Functions in PH7:4

Signal Name

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE PCINT23 •

DIEOV

DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT PCINT20 INPUT

AIO LCDSEG LCDSEG LCDSEG LCDSEG

PH7/PCINT23/ SEG36

PCIE0 •LCDEN • LCDPM

PH6/PCINT22/ SEG37

PCINT22 • PCIE0 •LCDEN • LCDPM

PH5/PCINT21/ SEG38

PCINT21 • PCIE0 •LCDEN • LCDPM

PH4/PCINT20/ SEG39

PCINT20 • PCIE0 •LCDEN • LCDPM

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Table 50. Overriding Signals for Alternate Functions in PH3:0

Signal Name

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE PCINT19 •

DIEOV

DI PCINT19 INPUT PCINT18 INPUT PCINT17 INPUT PCINT16 INPUT

AIO LCDSEG LCDSEG LCDSEG LCDSEG

PH3/PCINT19/ SEG7

PCIE0 •LCDEN • LCDPM

PH2/PCINT18/ SEG8

PCINT18 • PCIE0 •LCDEN • LCDPM

PH1/PCINT17/ SEG9

PCINT17 • PCIE0 •LCDEN • LCDPM

PH0/PCINT16/ SEG10

PCINT16 • PCIE0 •LCDEN • LCDPM

Alternate Functions of Port J Port J is only present in ATmega3290/6490. The alternate pin configuration is as

follows:

Table 51. Port J Pins Alternate Functions

Port Pin Alternate Function

PJ6 PCINT30/SEG (Pin Change Interrupt30 or LCD Front Plane 27)

PJ5 PCINT29/SEG (Pin Change Interrupt29 or LCD Front Plane 28)

PJ4 PCINT28/SEG (Pin Change Interrupt28 or LCD Front Plane 29)

PJ3 PCINT27/SEG (Pin Change Interrupt27 or LCD Front Plane 30)

PJ2 PCINT26/SEG(Pin Change Interrupt26 or LCD Front Plane 31)

PJ1 PCINT25/SEG(Pin Change Interrupt25 or LCD Front Plane 34)

PJ0 PCINT24/SEG (Pin Change Interrupt26 or LCD Front Plane 35)

The alternate pin configuration is as follows:

• PCINT30/SEG – Port J, Bit 6

PCINT30, Pin Change Interrupt Source 30: The PE30 pin can serve as an external interrupt source.

SEG, LCD front plane 27.

• PCINT29/SEG – Port J, Bit 5

PCINT29, Pin Change Interrupt Source 29: The PE29 pin can serve as an external interrupt source.

SEG, LCD front plane28.

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• PCINT28/SEG – Port J, Bit 4

PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source.

SEG, LCD front plane 29.

• PCINT27/SEG – Port J, Bit 3

PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source.

SEG, LCD front plane 30.

• PCINT26/SEG – Port J, Bit 2

PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source.

SEG, LCD front plane 31.

• PCINT25/SEG – Port J, Bit 1

PCINT25, Pin Change Interrupt Source 25: The PE25 pin can serve as an external interrupt source.

SEG, LCD front plane 34.

• PCINT24/SEG – Port J, Bit 0

PCINT24, Pin Change Interrupt Source 24: The PE24 pin can serve as an external interrupt source.

SEG, LCD front plane 35.

Table 52 and Table 53 relates the alternate functions of Port J to the overriding signals shown in Figure 27 on page 65.

Table 52. Overriding Signals for Alternate Functions in PJ7:4

Signal Name

PUOE LCDEN LCDEN LCDEN

PUOV 0 0 0

DDOE LCDEN LCDEN LCDEN

DDOV 0 0 0

PVOE 0 0 0

PVOV 0 0 0

PTOE – – –

DIEOE PCINT30 •

DIEOV

AIO LCDSEG LCDSEG LCDSEG

PJ6/PCINT30/ SEG27

PCIE0 •LCDEN • LCDPM

PJ5/PCINT29/ SEG28

PCINT29 • PCIE0 •LCDEN • LCDPM

PJ4/PCINT28/ SEG29

PCINT28 • PCIE0 •LCDEN • LCDPM

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Table 53. Overriding Signals for Alternate Functions in PH3:0

Signal Name

PUOE LCDEN LCDEN LCDEN LCDEN

PUOV0000

DDOE LCDEN LCDEN LCDEN LCDEN

DDOV 0 0 0 0

PVOE0000

PVOV0000

PTOE––––

DIEOE PCINT27 •

DIEOV

AIO LCDSEG LCDSEG LCDSEG LCDSEG

PJ3/PCINT27/ SEG30

PCIE0 •LCDEN • LCDPM

PJ2/PCINT26/ SEG31

PCINT26 • PCIE0 •LCDEN • LCDPM

PJ1/PCINT25/ SEG34

PCINT25 • PCIE0 •LCDEN • LCDPM

PJ0/PCINT24/ SEG35

PCINT24 • PCIE0 •LCDEN • LCDPM

2552H–AVR–11/06

Register Description for I/O-Ports

PORTA – Port A Data Register

DDRA – Port A Data Direction Register

PINA – Port A Input Pins Address

PORTB – Port B Data Register

DDRB – Port B Data Direction Register

Bit 76543210

0x22 (0x42)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x01 (0x21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x00 (0x20) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

0x05 (0x25)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0

PORTB7 PORTB6 PORT B5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

PORTA

PINB – Port B Input Pins Address

PORTC – Port C Data Register

DDRC – Port C Data Direction Register

PINC – Port C Input Pins Address

Bit 76543210

0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

0x08 (0x28)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x07 (0x27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x06 (0x26) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

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ATmega329/3210/649/6410

PORTD – Port D Data Register

DDRD – Port D Data Direction Register

PIND – Port D Input Pins Address

PORTE – Port E Data Register

DDRE – Port E Data Direction Register

Bit 76543210

0x0B (0x2B)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

0x0E (0x2E)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x0D (0x2D) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE

PINE – Port E Input Pins Address

PORTF – Port F Data Register

DDRF – Port F Data Direction Register

PINF – Port F Input Pins Address

Bit 76543210

0x0C (0x2C) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

0x11 (0x31)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x10 (0x30) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x0F (0x2F) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF

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PORTG – Port G Data Register

Bit 76543210

0x14 (0x34) –––

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG

DDRG – Port G Data Direction Register

PING – Port G Input Pins Address

PORTH – Port H Data Register

(1)

DDRH – Port H Data Direction Register

PINH – Port H Input Pins Address

(1)

Bit 76543210

0x13 (0x33) – – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x12 (0x32) – – PING5 PING4 PING3 PING2 PING1 PING0 PING

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 N/A N/A N/A N/A N/A

Bit 7 6543210

(0xDA) PORTH7

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0xD9) DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 DDRH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

(0xD8) PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 PINH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 PORTH

PORTJ – Port J Data Register

DDRJ – Port J Data Direction Register

PINJ – Port J Input Pins Address

(1)

ATmega329/3210/649/6410

Bit 76543210

(0xDD) –

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0xDC) – DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 DDRJ

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

(0xDB) – PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 PINJ

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 N/A N/A N/A N/A N/A N/A N/A

PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 PORTJ

Note: 1. Register only available in ATmega3290/6490.

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ATmega329/3290/649/6490

8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are:

Single Compare Unit Counter

•

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 28. For the

actual placement of I/O pins, refer to “Pinout ATmega3290/6490” on page 2 and “Pinout ATmega329/649” on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 99.

Figure 28. 8-bit Timer/Counter Block Diagram

TCCRn

count

clear

direction

BOTTOM

Control Logic

TOP

clk

Clock Select

Edge

Detector

TOVn

(Int.Req.)

Wavefo rm

Generation

( From Prescaler )

OCn

(Int.Req.)

OCn

Timer/Counter

TCNTn

DATA BU S

OCRn

= 0

0xFF

Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers.

Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk

The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See “Output Compare Unit” on page 91. for details. The compare match

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event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request.

Definitions Many register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare unit number, in this case unit A. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 54 are also used extensively throughout the document.

Table 54. Definitions of Timer/Counter values.

BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 103.

Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.

Figure 29 shows a block diagram of the counter and its surroundings.

Figure 29. Counter Unit Block Diagram

TOVn

top

(Int.Req.)

clk

Clock Select

Edge

Detector

( From Prescaler )

DATA B U S

count

TCNTn Control Logic

clear

direction

bottom

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

clk

Timer/Counter clock, referred to as clkT0 in the following.

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

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Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 94.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 94.).

). clkT0 can be generated from an external or internal

is present or not. A CPU write overrides (has

Figure 30 shows a block diagram of the Output Compare unit.

Figure 30. Output Compare Unit, Block Diagram

DATA B U S

OCRnx

= (8-bit Comparator )

top

bottom

FOCn

Waveform Generator

WGMn1:0

COMnX1:0

TCNTn

OCFnx (Int.Req.)

OCnx

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The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0A Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is disabled the CPU will access the OCR0A directly.

Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or toggled).

Compare Match Blocking by TCNT0 Write

Using the Output Compare Unit

Compare Match Output Unit

All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled.

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is counting down.

The setup of the OC0A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0A value is to use the Force Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes.

Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits will take effect immediately.

The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 31 shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System Reset occur, the OC0A Register is reset to “0”.

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Figure 31. Compare Match Output Unit, Schematic

COMnx1

COMnx0 FOCn

clk

I/O

Waveform Generator

OCnx

PORT

DATA BU S

DDR

OCn

The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is visible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 99.

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 56 on page 100. For fast PWM mode, refer to Table 57 on page 100, and for phase correct PWM refer to Table 58 on page 101.

A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits.

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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output Unit” on page 92.).

For detailed timing information refer to Figure 35, Figure 36, Figure 37 and Figure 38 in “Timer/Counter Timing Diagrams” on page 98.

Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the

counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 32. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 32. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn (Toggle)

Period

1 4

2 3

(COMnx1:0 = 1)

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written

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ATmega329/3290/649/6490

to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f is defined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00.

Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dualslope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

OC0

= f

/2 when OCR0A is set to zero (0x00). The waveform frequency

clk_I/O

OCnx

------------------------------------------------- -=

2 N 1 OCRnx+()⋅⋅

clk_I/O

In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 33. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.

Figure 33. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and TOVn Interrupt Flag Set

TCNTn

OCn

Period

2 3

4 5 6 7

(COMnx1:0 = 2)

(COMnx1:0 = 3)

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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 57 on page 100). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0A Register at the compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

OCnxPWM

clk_I/O

----------------- -=

N 256⋅

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of f

OC0

= f

/2 when OCR0A is

clk_I/O

set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.

Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A while counting up, and set on the compare match while counting down. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 34. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.

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Figure 34. Phase Correct PWM Mode, Timing Diagram

TCNTn

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

OCn

Period

1 2 3

(COMnx1:0 = 2)

(COMnx1:0 = 3)

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 58 on page 101). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

OCnxPCPWM

clk_I/O

----------------- -=

N 510⋅

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

2552H–AVR–11/06

The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 34 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 34. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 35 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 35. Timer/Counter Timing Diagram, no Prescaling

clk

I/O

clk

(clk

/1)

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

Figure 36 shows the same timing data, but with the prescaler enabled.

Figure 36. Timer/Counter Timing Diagram, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

clk_I/O

/8)

TCNTn

TOVn

MAX - 1 MAX BOTTOM BOTTOM + 1

Figure 37 shows the setting of OCF0A in all modes except CTC mode.

Figure 37. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

TCNTn

OCRnx

OCFnx

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCRnx Value

clk_I/O

/8)

ATmega329/3290/649/6490

2552H–AVR–11/06

ATmega329/3290/649/6490

Figure 38 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 38. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f

clk

I/O

clk

(clk

/8)

I/O

TCNTn

(CTC)

clk_I/O

/8)

TOP - 1 TOP BOTTOM BOTTOM + 1

8-bit Timer/Counter Register Description

TCCR0A – Timer/Counter Control Register A

OCRnx

OCFnx

Bit 7 6 5 4 3 2 1 0

0x24 (0x44)

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 TCCR0A

TOP

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate compare match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.

2552H–AVR–11/06

The FOC0A bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 55 and “Modes of Operation” on page 94.

Table 55. Waveform Generation Mode Bit Description

(1)

WGM01

Mode

Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-

(CTC0)

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM

2 1 0 CTC OCR0A Immediate MAX

3 1 1 Fast PWM 0xFF BOTTOM MAX

initions. However, the functionality and location of these bits are compatible with previous versions of the timer.

WGM00 (PWM0)

Timer/Counter Mode of Operation TOP

Update of OCR0A at

TOV0 Flag Set on

• Bit 5:4 – COM0A1:0: Compare Match Output Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 56 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM).

Table 56. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on compare match

1 0 Clear OC0A on compare match

1 1 Set OC0A on compare match

Table 57 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.

Table 57. Compare Output Mode, Fast PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

01Reserved

1 0 Clear OC0A on compare match, set OC0A at BOTTOM,

(non-inverting mode)

1 1 Set OC0A on compare match, clear OC0A at BOTTOM,

(inverting mode)

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 95 for more details.

(1)

Table 58 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode.

100

ATmega329/3290/649/6490

2552H–AVR–11/06

Rainbow Electronics ATmega3290PV User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Features (Continued)

Pin Configurations Figure 1. Pinout ATmega3290/6490

Disclaimer Typical values contained in this datasheet are based on simulations and characteriza-

Overview

Block Diagram

Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490

Pin Descriptions The following section describes the I/O-pin special functions.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter.

Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally

AREF This is the analog reference pin for the A/D Converter.

LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as

Resources A comprehensive set of development tools, application notes and datasheets are avail-

About Code Examples

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the

Architectural Overview Figure 4. Block Diagram of the AVR Architecture

AVR Status Register The Status Register contains information about the result of the most recently executed

General Purpose Register File

The X-register, Y-register, and Z-register

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for

Instruction Execution Timing

Reset and Interrupt Handling

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

AVR ATmega329/3290/649/6490 Memories

In-System Reprogrammable Flash Program Memory

SRAM Data Memory Figure 10 shows how the ATmega329/3290/649/6490 SRAM Memory is organized.

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

EEPROM Data Memory The ATmega329/3290/649/6490 contains 1/2K bytes of data EEPROM memory. It is

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

Preventing EEPROM Corruption

I/O Memory The I/O space definition of the ATmega329/3290/649/6490 is shown in “Register Sum-

General Purpose I/O Registers The ATmega329/3290/649/6490 contains three General Purpose I/O Registers. These

System Clock and Clock Options

Clock Systems and their Distribution

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as

Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed.

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can

Low-frequency Crystal Oscillator

Calibrated Internal RC Oscillator

External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in

Clock Output Buffer When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This

Timer/Counter Oscillator ATmega329/3290/649/6490 share the Timer/Counter Oscillator Pins (TOSC1 and

System Clock Prescaler The ATmega329/3290/649/6490 system clock can be divided by setting the Clock Pres-

Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that

Power Management and Sleep Modes

Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter

ADC Noise Reduction Mode

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter

Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter

Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,

Power Reduction Register

Minimizing Power Consumption

Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should

Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When

Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned

Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-

Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off.

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.

JTAG Interface and On-chip Debug System

Register Description

System Control and Reset

Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts exe-

Reset Sources The ATmega329/3290/649/6490 has five sources of reset:

Power-on Reset

External Reset An External Reset is generated by a low level on the RESET