– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– 4x25SegmentLCDDriver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 53 Programmable I/O Lines and 1 Input Line
– 64-lead TQFP
• Operating Voltage:
– 1.8 - 3.6V for ATmega169V
– 2.7 - 3.6V for ATmega169L
• Temperature Range:
–-10
°Cto50°C
• Speed Grade:
– 0 - 1 MHz for ATmega169V
– 0 - 4 MHz for ATmega169L
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega169V
ATmega169L
Advance
Information
Rev. 2514A–AVR–08/02
1
Pin ConfigurationsFigure 1. Pinout ATmega169
GND
AVCC
64
63
LCDCAP
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PF0 (ADC0)
PF1 (ADC1)
AREF
61
6018592058
62
INDEX CORNER
19
21
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
57225623552454255326522751
ATmega169
GND
PF7 (ADC7/TDI)
PF6 (ADC6/TDO)
28
VCC
29
PA0 (COM0)
PA1 (COM1)
50
31
30
PA2 (COM2)
49
PA3 (COM3)
48
PA4 (SEG0)
47
PA5 (SEG1)
46
PA6 (SEG2)
45
PA7 (SEG3)
44
43
PG2 (SEG4)
42
PC7 (SEG5)
41
PC6 (SEG6)
40
PC5 (SEG7)
PC4 (SEG8)
39
PC3 (SEG9)
38
PC2 (SEG10)
37
PC1 (SEG11)
36
PC0 (SEG12)
35
34
PG1 (SEG13)
33
PG0 (SEG14)
32
VCC
GND
(RESET) PG5
(T1/SEG24) PG3
(T0/SEG23) PG4
(OC2A/PCINT15) PB7
(TOSC1) XTAL1
(TOSC2) XTAL2
(ICP/SEG22) PD0
(SEG20) PD2
(INT0/SEG21) PD1
(SEG17) PD5
(SEG18) PD4
(SEG19) PD3
(SEG15) PD7
(SEG16) PD6
DisclaimerTypical values contained in this data sheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
2
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Overview
The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
VCC
GND
AVCC
AGND
AREF
DATA REGISTER
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
PORTF DRIVERS
PORTF
DATA DIR.
REG. PORTF
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
DATA REGISTER
PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
PA0 - PA7PF0 - PF7
PORTA DRIVERS
DATA DIR.
REG. PORTA
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
PORTC DRIVERS
DATA REGISTER
PORTC
CALIB. OSC
OSCILLATOR
TIMING AND
CONTROL
PC0 - PC7
DATA DIR.
REG. PORTC
CONTROLLER/
LCD
DRIVER
XTAL1
XTAL2
ANALOG
2514A–AVR–08/02
TOR
+
COMPARA
USART0
DATA REGISTER
PORTE
-
AVR CPU
SERIAL INTERFACE
PORTE DRIVERS
UNIVERSAL
DATA DIR.
REG. PORTE
STATUS
REGISTER
DATA REGISTER
PORTB
PORTB DRIVERS
PB0 - PB7PE0 - PE7
DATA DIR.
REG. PORTB
SPI
DATA REGISTER
PORTD
PORTD DRIVERS
PD0 - PD7
DATA DIR.
REG. PORTD
DATA REG.
PORTG
PORTG DRIVERS
PG0 - PG4
DATA DIR.
REG. PORTG
RESET
3
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega169 provides the following features: 16K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM,
53 general purpose I/O lines and one input line, 32 general purpose working registers, a
JTAG interface for Boundary-scan, On-chip Debugging support and programming, a
complete On-chip LCD controller with internal step-up voltage, three flexible
Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port,
and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Powersave mode, the asynchronous timer and the LCD controller continues to run, allowing
the user to maintain a timer base and operate the LCD display while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules
except asynchronous timer, LCD controller and ADC, to minimize switching noise during
ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low-power
consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer, or
by an On-chip Boot program running on the AVR core. The Boot program can use any
interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is
a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega169 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
4
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Pin Descriptions
VCCDigital supply voltage.
GNDGround.
Port A (PA7..PA0)Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega169 as listed
on page 57.
Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega169 as listed
on page 58.
Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega169 as listed on page
61.
Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega169 as listed
on page 63.
Port E (PE7..PE0)Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega169 as listed
on page 65.
Port F (PF7..PF0)Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
2514A–AVR–08/02
5
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset
occurs.
Port F also serves the functions of the JTAG interface.
Port G (PG5..PG0)Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). PG5 is
input only, the rest of the pins are bi-directional. The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G
pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
Port G also serves the functions of various special features of the ATmega169 as listed
on page 65.
RESET
XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2Output from the inverting Oscillator amplifier.
AVC CAVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally
AREFThis is the analog reference pin for the A/D Converter.
About Code
Examples
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table
16 on page 37. Shorter pulses are not guaranteed to generate a reset.
connected to V
nected to V
This documentation contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
, even if the ADC is not used. If the ADC is used, it should be con-
CC
through a low-pass filter.
CC
6
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
AVR CPU Core
IntroductionThis section discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals, and handle interrupts.
Architectural OverviewFigure 3. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
Data
SRAM
EEPROM
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
2514A–AVR–08/02
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File,
7
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and
the Application Program section. Both sections have dedicated Lock bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
ALU – Arithmetic Logic
Unit
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table. The interrupts have priority in accordance with their
Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as
the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition,
the ATmega169 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
8
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Status RegisterThe Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the Status Register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit76543210
ITHSVNZCSREG
Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W
InitialValue00000000
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as
described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the “Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
2514A–AVR–08/02
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
9
• Bit0–C:CarryFlag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
•One 8-bit output operand and one 8-bit result input
•Two 8-bit output operands and one 8-bit result input
•Two 8-bit output operands and one 16-bit result input
•One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4. AVR CPU General Purpose Working Registers
70Addr.
R00x00
R10x01
R20x02
…
R130x0D
GeneralR140x0E
PurposeR150x0F
WorkingR160x10
RegistersR170x11
…
R260x1AX-register Low Byte
R270x1BX-register High Byte
R280x1CY-register Low Byte
R290x1DY-register High Byte
R300x1EZ-register Low Byte
R310x1FZ-register High Byte
10
Most of the instructions operating on the Register File have direct access to all registers,
and most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
The X-register, Y-register, and
Z-register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the data space.
The three indirect address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
15XHXL0
X-register7070
R27 (0x1B)R26 (0x1A)
15YHYL0
Y-register7070
R29 (0x1D)R28 (0x1C)
15ZHZL0
Z-register7070
R31 (0x1F)R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set
reference for details).
Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locations to lower memory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above 0x60. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by
two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two when data is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit151413121110 9 8
SP15SP14SP13SP12SP11SP10SP9SP8SPH
SP7SP6SP5SP 4SP3SP2SP1SP0SPL
76543210
Read/WriteR/WR/WR/ WR/WR/WR/WR/WR/W
R/WR/WR/WR/WR/WR/WR/WR/W
InitialValue00000000
00000000
2514A–AVR–08/02
11
Instruction Execution
Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
, directly generated from the selected clock
CPU
source for the chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1T2T3T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination register.
Reset and Interrupt
Handling
Figure 7. Single Cycle ALU Operation
T1T2T3T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the Program Counter value, interrupts may be automatically disabled
when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memory Programming” on page 265 for details.
The lowest addresses in the program memory space are by default defined as the Reset
and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 45.
The list also determines the priority levels of the different interrupts. The lower the
address the higher is the priority level. RESET has the highest priority, and next is INT0
– the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of
the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).
Refer to “Interrupts” on page 45 for more information. The Reset Vector can also be
12
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see
“Boot Loader Support – Read-While-Write Self-Programming” on page 251.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the interrupt flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable
bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence..
Assembly Code Example
in r16, SREG
cli; disable interrupts during timed sequence
sbi EECR, EEMWE
sbi EECR, EEWE
out SREG, r16
; store SREG value
; start EEPROM write
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;
/*
disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE);
EECR |= (1<<EEWE);
SREG = cSREG;
/* store SREG value */
/* start EEPROM write */
/* restore SREG value (I-bit) */
2514A–AVR–08/02
13
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI();
_SLEEP();
/* note: will enter sleep before any pending interrupt(s) */
/* set Global Interrupt Enable */
/* enter sleep, waiting for interrupt */
Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in addition to the start-up time from
the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack
Pointer is incremented by two, and the I-bit in SREG is set.
14
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
AVR ATmega169
Memories
In-System
Reprogrammable Flash
Program Memory
This section describes the different memories in the ATmega169. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega169 features an EEPROM Memory for data storage. All three
memory spaces are linear and regular.
The ATmega169 contains 16K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is
organized as 8K x 16. For software security, the Flash Program memory space is
divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 1,000 write/erase cycles. The
ATmega169 Program Counter (PC) is 13 bits wide, thus addressing the 8K program
memory locations. The operation of Boot Program section and associated Boot Lock
bits for software protection are described in detail in “Boot Loader Support – ReadWhile-Write Self-Programming” on page 251. “Memory Programming” on page 265 contains a detailed description on Flash data serial downloading using the SPI pins or the
JTAG interface.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 12.
Figure 8. Program Memory Map
Program Memory
Application Flash Section
0x0000
2514A–AVR–08/02
Boot Flash Section
0x1FFF
15
SRAM Data MemoryFigure 9 shows how the ATmega169 SRAM Memory is organized.
The ATmega169 is a complex microcontroller with more peripheral units than can be
supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
The lower 1,280 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the
Register File, the next 64 location the standard I/O memory, then 160 locations of
Extended I/O memory, and the next 1024 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 1,024 bytes of internal data SRAM in the ATmega169 are all accessible
through all these addressing modes. The Register File is described in “General Purpose
Register File” on page 10.
Figure 9. Data Memory Map
Data Memory
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
32 Registers
(1024 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
0x04FF
16
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Data Memory Access TimesThis section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
10.
Figure 10. On-chip Data SRAM Access Cycles
T1T2T3
clk
CPU
Address
Compute Address
Address valid
Data
cycles as described in Figure
CPU
WR
Write
Data
RD
Memory Access Instruction
Next Instruction
Read
EEPROM Data MemoryThe ATmega169 contains 512 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM,
see page 279, page 283, and page 268 respectively.
EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, V
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page
21. for details on how to avoid problems in these situations.
is likely to rise or fall slowly on power-up/down. This
CC
2514A–AVR–08/02
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
17
The EEPROM Address
Register – EEARH and EEARL
Bit151413121110 9 8
–––––––EEAR8EEARH
EEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0EEARL
76543210
Read/WriteRRRRRRRR/W
R/WR/WR/WR/WR/WR/WR/WR/W
InitialValue0000 000X
XXXXXXXX
• Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega169 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address
in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
The EEPROM Data Register –
EEDR
The EEPROM Control
Register – EECR
Bit76543210
MSBLSBEEDR
Read/WriteR/WR/WR/WR/WR/WR/WR /WR/W
InitialValue0000 0000
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit76543 2 10
––––EERIEEEMWEEEWEEEREEECR
Read/WriteRRRRR/WR/WR/WR/W
InitialValue0000 00X0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega169 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEWE is cleared.
18
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is set, setting EEWE within four clock cycles will write data to the
EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.
When EEMWE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
• Bit 1 – EEWE: EEPROM Write Enable
TheEEPROMWriteEnableSignalEEWEisthewritestrobetotheEEPROM.When
address and data are correctly set up, the EEWE bit must be written to one to write the
value into the EEPROM. The EEMWE bit must be written to one before a logical one is
written to EEWE, otherwise no EEPROM write takes place. The following procedure
should be followed when writing the EEPROM (the order of steps 3 and 4 is not
essential):
1.Wait until EEWE becomes zero.
2.Wait until SPMEN in SPMCSR becomes zero.
3.Write new EEPROM address to EEAR (optional).
4.Write new EEPROM data to EEDR (optional).
5.Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The
software must check that the Flash programming is completed before initiating a new
EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing
the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
canbeomitted.See“Boot Loader Support – Read-While-Write Self-Programming” on
page 251 for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress, it is neither possible to read the EEPROM, nor to change the EEAR
Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical
programming time for EEPROM access from the CPU.
Table 1. EEPROM Programming Time.
2514A–AVR–08/02
SymbolNumber of Calibrated RC Oscillator CyclesTyp Programming Time
EEPROM write
(from CPU)
Note:1. Uses 1 MHz clock, independent of CKSEL Fuse settings.
84488.5 ms
19
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no Flash Boot Loader is present in the software. If such
code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
Wait for completion of previous write
/*
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
Write logical one to EEMWE */
/*
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
*/
20
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
inr16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
Start eeprom read by writing EERE */
/*
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
Preventing EEPROM
Corruption
2514A–AVR–08/02
During periods of low V
the EEPROM data can be corrupted because the supply volt-
CC,
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
V
reset Protection circuit can be used. If a reset occurs while a write operation is in
CC
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
21
I/O MemoryThe I/O space definition of the ATmega169 is shown in “Register Summary” on page
302.
All ATmega169 I/Os and peripherals are placed in the I/O space. All I/O locations may
be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the instruction set section for more details. When
using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be
used. When addressing I/O Registers as data space using LD and ST instructions, 0x20
must be added to these addresses. The ATmega169 is a complex microcontroller with
more peripheral units than can be supported within the 64 location reserved in Opcode
for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike
most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such status flags. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
General Purpose I/O RegistersThe ATmega169 contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and status flags. General Purpose I/O Registers within the address range 0x00 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
General Purpose I/O Register
2 – GPIOR2
General Purpose I/O Register
1 – GPIOR1
General Purpose I/O Register
0 – GPIOR0
Bit76543210
MSBLSBGPIOR2
Read/WriteR/WR/WR/WR/WR/WR/WR /WR/W
InitialValue0000 0000
Bit76543210
MSBLSBGPIOR1
Read/WriteR/WR/WR/WR/WR/WR/WR /WR/W
InitialValue0000 0000
Bit76543210
MSBLSBGPIOR0
Read/WriteR/WR/WR/WR/WR/WR/WR /WR/W
InitialValue0000 0000
22
ATmega169V/L
2514A–AVR–08/02
System Clock and
Clock Options
ATmega169V/L
Clock Systems and their
Distribution
Figure 11 presents the principal clock systems in the AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 32. The clock systems
are detailed below.
Figure 11. Clock Distribution
LCD Controller
Asynchronous
Timer/Counter
General I/O
Modules
clk
clk
ASY
CPU CoreRAM
I/O
AVR Clock
Control Unit
Source clock
Clock
Multiplexer
clk
CPU
clk
FLASH
Reset Logic
Watchdog Timer
Watchdog clock
Watchdog
Oscillator
Flash and
EEPROM
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
CPU
I/O
FLASH
Asynchronous Timer Clock –
clk
ASY
Timer/Counter
Oscillator
External Clock
Crystal
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
USART. The I/O clock is also used by the External Interrupt module, but note that some
external interrupts are detected by asynchronous logic, allowing such interrupts to be
detected even if the I/O clock is halted. Also note that start condition detection in the USI
module is carried out asynchronously when clk
is halted, enabling USI start condition
I/O
detection in all sleep modes.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with the CPU clock.
The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD
controller to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter
even when the device is in sleep mode. It also allows the LCD controller output to continue while the rest of the device is in sleep mode.
2514A–AVR–08/02
23
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
Clock SourcesThe device has the following clock source options, selectable by Flash Fuse bits as
shown below. The clock from the selected source is input to the AVR clock generator,
and routed to the appropriate modules.
Table 2. Device Clocking Options Select
Device Clocking OptionCKSEL3..0
External Crystal/Ceramic Resonator1111 - 1000
External Low-frequency Crystal0111 - 0100
Calibrated Internal RC Oscillator0010
External Clock0000
Reserved0011, 0001
Note:1. For all fuses “1” means unprogrammed while “0” means programmed.
(1)
The various choices for each clocking option is given in the following sections. When the
CPU wakes up from Power-down or Power-save, the selected clock source is used to
time the start-up, ensuring stable Oscillator operation before instruction execution starts.
When the CPU starts from reset, there is an additional delay allowing the power to reach
a stable level before commencing normal operation. The Watchdog Oscillator is used
for timing this real-time part of the start-up time. The number of WDT Oscillator cycles
used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is
voltage dependent as shown in “ATmega169 Typical Characteristics – Preliminary
Data” on page 301.
Table 3. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC= 5.0V)Typ Time-out (VCC= 3.0V)Number of Cycles
4.1 ms4.3 ms4K (4,096)
65 ms69 ms64K (65,536)
Default Clock SourceThe device is shipped with CKSEL = “0010”,SUT=“10”, and CKDIV8 programmed.
The default clock source setting is the Internal RC Oscillator with longest start-up time
and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or Parallel programmer.
24
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz
crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value
of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for
choosing capacitors for use with crystals are given in Table 4. For ceramic resonators,
the capacitor values given by the manufacturer should be used. For more information on
how to choose capacitors and other details on Oscillator operation, refer to the Multipurpose Oscillator Application Note.
Figure 12. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in
Table 4.
Table 4. Crystal Oscillator Operating Modes
CKSEL3..1Frequency Range
(2)
100
1010.9 - 3.012 - 22
1103.0 - 8.012 - 22
1118.0 -12 - 22
Notes:1. The frequency ranges are preliminary values. Actual values are TBD.
2. This option should not be used with crystals, only with ceramic resonators.
0.4 - 0.9–
(1)
(MHz)
Recommended Range for Capacitors C1
and C2 for Use with Crystals (pF)
2514A–AVR–08/02
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown
in Table 5.
25
Table 5. Start-up Times for the Crystal Oscillator Clock Selection
Start-up Time from
Power-down and
CKSEL0SUT1..0
000 258CK
001 258CK
0101KCK
0111KCK
1001KCK
1
1
1
Notes:1. These options should only be used when not operating close to the maximum fre-
0116K CK14CKCrystal Oscillator, BOD
1016K CK14CK + 4.1 msCrystal Oscillator, fast
1116K CK14CK + 65 msCrystal Oscillator,
quency of the device, and only if frequency stability at start-up is not important for the
application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating
close to the maximum frequency of the device, and if frequency stability at start-up is
not important for the application.
Power-save
(1)
(1)
(2)
(2)
(2)
Additional Delay
from Reset
(V
= 5.0V)Recommended Usage
CC
14CK + 4.1 msCeramic resonator, fast
rising power
14CK + 65 msCeramic resonator,
slowly rising power
14CKCeramic resonator,
BOD enabled
14CK + 4.1 msCeramic resonator, fast
rising power
14CK + 65 msCeramic resonator,
slowly rising power
enabled
rising power
slowly rising power
Low-frequency Crystal
Oscillator
To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency
crystal Oscillator must be selected by setting the CKSEL Fuses to “0100”, “0101”,“0110”,or“0111”. The crystal should be connected as shown in Figure 12. When this
Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 6 and CKSEL1..0 as shown in Table 7.
Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
SUT1..0Additional Delay from Reset (VCC= 5.0V)Recommended Usage
0014CKFast rising power or BOD enabled
0114CK + 4.1 msSlowly rising power
1014CK + 65 msStable frequency at start-up
11Reserved
26
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Table 7. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time from
CKSEL3..0
(1)
0100
010132K CKStable frequency at start-up
(1)
0110
011132K CKStable frequency at start-up
Note:1. These options should only be used if frequency stability at start-up is not important for
the application
Power-down and Power-saveRecommended Usage
1K CK
1K CK
Calibrated Internal RC
Oscillator
The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is
nominal value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the
device (depends on V
),theCKDIV8Fusemustbeprogrammedinordertodividethe
CC
internal frequency by 8 during start-up. The device is shipped with the CKDIV8 Fuse
programmed. See “System Clock Prescaler” on page 30. for more details. This clock
may be selected as the system clock by programming the CKSEL Fuses as shown in
Table 8. If selected, it will operate with no external components. During reset, hardware
loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives a frequency within ± 1%
of the nominal frequency. When this Oscillator is used as the chip clock, the Watchdog
Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more
information on the pre-programmed calibration value, see the section “Calibration Byte”
on page 268.
Note:1. The device is shipped with this option selected.
(1)
When this Oscillator is selected, start-up times are determined by the SUT Fuses as
shown in Table 9.
Table 9. Start-up times for the internal calibrated RC Oscillator clock selection
SUT1..0
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (VCC= 5.0V)Recommended Usage
2514A–AVR–08/02
006 CK14CKBOD enabled
016 CK14CK + 4.1 msFast rising power
(1)
10
11Reserved
Note:1. The device is shipped with this option selected.
6 CK14CK + 65 msSlowly rising power
27
Oscillator Calibration Register
– OSCCAL
Bit76543210
–CAL6CAL5CAL4CAL3CAL2CAL1CAL0OSCCAL
Read/WriteRR/WR/WR/WR/WR/WR/WR/W
Initial ValueDevice Specific Calibration Value
• Bits 6..0 – CAL6..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip
Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing nonzero values to this register will increase the frequency of the internal Oscillator. Writing
0x7F to the register gives the highest available frequency. The calibrated Oscillator is
used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash
write may fail. Note that the Oscillator is intended for calibration to 8.0 MHz. Tuning to
other values is not guaranteed, as indicated in Table 10.
Table 10. Internal RC Oscillator Frequency Range.
Min Frequency in Percentage of
OSCCAL Value
0x0050%100%
0x3F75%150%
0x7F100%200%
Nominal Frequency
Max Frequency in Percentage of
Nominal Frequency
28
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
External ClockTo drive the device from an external clock source, XTAL1 should be driven as shown in
Figure 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Figure 13. External Clock Drive Configuration
NC
EXTERNAL
CLOCK
SIGNAL
XTAL2
XTAL1
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 12.
Table 11. Crystal Oscillator Clock Frequency
CKSEL3..0Frequency Range
00000 - 16 MHz
Table 12. Start-up Times for the External Clock Selection
Start-up Time from Power-
SUT1..0
006 CK14CKBOD enabled
down and Power-save
Additional Delay from
Reset (VCC= 5.0V)Recommended Usage
016 CK14CK + 4.1 msFast rising power
106 CK14CK + 65 msSlowly rising power
11Reserved
When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the MCU. A variation in frequency of more
than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
required to ensure that the MCU is kept in Reset during such changes in the clock
frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of
the internal clock frequency while still ensuring stable operation. Refer to “System Clock
Prescaler” on page 30 for details.
Clock Output BufferWhen the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This
mode is suitable when chip clock is used to drive other circuits on the system. The clock
will be output also during reset and the normal operation of I/O pin will be overridden
when the fuse is programmed. Any clock source, including internal RC Oscillator, can be
selcted when CLKO serves as clock output. If the System Clock Prescaler is used, it is
the divided system clock that is output when the CKOUT Fuse is programmed.
29
2514A–AVR–08/02
Timer/Counter OscillatorATmega169 share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1
and XTAL2. This means that the Timer/Counter Oscillator can only be used when the
calibrated internal RC Oscillator is selected as system clock source. The Oscillator is
optimized for use with a 32.768 kHz watch crystal. See Figure 12 on page 25 for crystal
connection.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. See “Asynchronous operation of the Timer/Counter” on page
137 for futher description on selecting external clock as input instead of a 32 kHz crystal.
System Clock PrescalerThe ATmega169 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
, and clk
CPU
are divided by a factor as shown in Table 13.
FLASH
I/O
,clk
ADC
,
Clock Prescale Register –
CLKPR
Bit76543210
CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0CLKPR
Read/WriteR/WRRRR/WR/WR/WR/W
Initial Value0000See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKPCE bit.
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 13.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1.Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2.Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
30
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if
the selected clock source has a higher frequency than the maximum frequency of the
device at the present operating conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selcted clock source has a higher
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 13. Clock Prescaler Select
CLKPS3CLKPS2CLKPS1CLKPS0Clock Division Factor
00001
00012
00104
00118
010016
010132
011064
0111128
1000256
1001Reserved
1010Reserved
1011Reserved
1100Reserved
1101Reserved
1110Reserved
1111Reserved
2514A–AVR–08/02
31
Power Management
and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby
saving power. The AVR provides various sleep modes allowing the user to tailor the
power consumption to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one
and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR
Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Powersave, or Standby) will be activated by the SLEEP instruction. See Table 14 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes
up. The MCU is then halted for four cycles in addition to the start-up time, executes the
interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep.
If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset
Vector.
Figure 11 on page 23 presents the different clock systems in the ATmega169, and their
distribution. The figure is helpful in selecting an appropriate sleep mode.
Sleep Mode Control Register –
SMCR
The Sleep Mode Control Register contains control bits for power management.
These bits select between the five available sleep modes as shown in Table 14.
Table 14. Sleep Mode Select
SM2SM1SM0Sleep Mode
000Idle
001ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
111Reserved
(1)
32
Note:1. Standby mode is only recommended for use with external crystals or resonators.
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is
the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one
just before the execution of the SLEEP instruction and to clear it immediately after waking up.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Idle ModeWhen the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog
Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk
other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
CPU
and clk
, while allowing the
FLASH
ADC Noise Reduction
Mode
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI start condition detection, Timer/Counter2, LCD Controller, and the
Watchdog to continue operating (if enabled). This sleep mode basically halts clk
clk
, and clk
CPU
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, an LCD controller interrupt, USI start condition
interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external
level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise
Reduction mode.
, while allowing the other clocks to run.
FLASH
I/O
Power-down ModeWhen the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external
interrupts, the USI start condition detection, and the Watchdog continue operating (if
enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake
up the MCU. This sleep mode basically halts all generated clocks, allowing operation of
asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 75 for details.
,
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
24.
Power-save ModeWhen the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during
sleep. The device can wake up from either Timer Overflow or Output Compare event
from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in
TIMSK2, and the Global Interrupt Enable bit in SREG is set. It can also wake up from an
LCD controller interrupt.
If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended instead of Power-save mode.
33
2514A–AVR–08/02
The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. The clock source for the two modules can be selected
independent of each other. If neither the LCD controller nor the Timer/Counter2 is using
the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If neither
the LCD controller nor the Timer/Counter2 is using the synchronous clock, the clock
source is stopped during sleep. Note that even if the synchronous clock is running in
Power-save, this clock is only available for the LCD controller and Timer/Counter2.
Standby ModeWhen the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in six clock cycles.
Table 15 . Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock DomainsOscillatorsWake-up Sources
MainClock
Sleep Mode
clk
CPU
clk
FLASH
clkIOclk
ADC
clk
ASY
Source
Enabled
IdleXXXXX
Timer
Osc
Enabled
(2)
INT0
and Pin
Change
USI Start
Condition
LCD
Controller Timer2
SPM/
EEPROM
ReadyADC
Other
I/O
XX XXXXX
ADC Noise
ReductionXXXX
Power-downX
Power-saveXXX
Standby
(1)
XX
(2)
(3)
X
(3)
(3)
(3)
XX
X
XXX
X
(2)
(2)
X
XX
Notes:1. Only recommended with external crystal or resonator selected as clock source.
2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
Minimizing Power
Consumption
There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the
following modules may need special consideration when trying to achieve the lowest
possible power consumption.
Analog to Digital ConverterIf enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should
be disabled before entering any sleep mode. When the ADC is turned off and on again,
the next conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 191 for details on ADC operation.
Analog ComparatorWhen entering Idle mode, the Analog Comparator should be disabled if not used. When
entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In
other sleep modes, the Analog Comparator is automatically disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on
page 188 for details on how to configure the Analog Comparator.
34
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Brown-out DetectorIf the Brown-out Detector is not needed by the application, this module should be turned
off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in
all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 39 for details on how to configure the Brown-out Detector.
Internal Voltage ReferenceThe Internal Voltage Reference will be enabled when needed by the Brown-out Detec-
tion, the Analog Comparator or the ADC. If these modules are disabled as described in
the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up
before the output is used. If the reference is kept on in sleep mode, the output can be
used immediately. Refer to “Internal Voltage Reference” on page 41 for details on the
start-up time.
Watchdog TimerIf the Watchdog Timer is not needed in the application, the module should be turned off.
If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,
always consume power. In the deeper sleep modes, this will contribute significantly to
the total current consumption. Refer to “Watchdog Timer” on page 42 for details on how
to configure the Watchdog Timer.
Port PinsWhen entering a sleep mode, all port pins should be configured to use minimum power.
The most important is then to ensure that no pins drive resistive loads. In sleep modes
where both the I/O clock (clk
ers of the device will be disabled. This ensures that no power is consumed by the input
logic when not needed. In some cases, the input logic is needed for detecting wake-up
conditions, and it will then be enabled. Refer to the section “Digital Input Enable and
Sleep Modes” on page 54 for details on which pins are enabled. If the input buffer is
enabled and the input signal is left floating or have an analog signal level close to V
the input buffer will use excessive power.
) and the ADC clock (clk
I/O
) are stopped, the input buff-
ADC
CC
/2,
For analog input pins, the digital input buffer should be disabled at all times. An analog
signal level close to V
/2 on an input pin can cause significant current even in active
CC
mode. Digital input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to “Digital Input Disable Register 0 – DIDR0” on page
190 and “Digital Input Disable Register 1 – DIDR1” on page 208 for details.
On-chip Debug System
If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode,
the main clock source is enabled, and hence, always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
2514A–AVR–08/02
35
System Control and
Reset
Resetting the AVRDuring reset, all I/O Registers are set to their initial values, and the program starts exe-
cution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP
– Absolute Jump – instruction to the reset handling routine. If the program never
enables an interrupt source, the Interrupt Vectors are not used, and regular program
code can be placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the Boot section or vice versa. The
circuit diagram in Figure 14 shows the reset logic. Table 16 defines the electrical parameters of the reset circuitry.
The I/O ports of the AVR are immediately reset to their initial state when a reset source
goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the
internal reset. This allows the power to reach a stable level before normal operation
starts. The time-out period of the delay counter is defined by the user through the SUT
and CKSEL Fuses. The different selections for the delay period are presented in “Clock
Sources” on page 24.
Reset SourcesThe ATmega169 has five sources of reset:
•Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
•External Reset. The MCU is reset when a low level is present on the RESET
longer than the minimum pulse length.
•Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog is enabled.
•Brown-out Reset. The MCU is reset when the supply voltage V
Brown-out Reset threshold (V
•JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset
Register, one of the scan chains of the JTAG system. Refer to the section “IEEE
1149.1 (JTAG) Boundary-scan” on page 231 for details.
POT
).
pin for
is below the
) and the Brown-out Detector is enabled.
BOT
CC
36
ATmega169V/L
2514A–AVR–08/02
Figure 14. Reset Logic
Power-on Reset
Circuit
DATA BU S
MCU Status
Register (MCUSR)
JTRF
BORF
PORF
WDRF
EXTRF
ATmega169V/L
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
JTAG Reset
Register
Table 16. Reset Characteristics
Brown-out
Reset Circuit
Watchdog
Oscillator
Clock
Generator
CKSEL[3:0]
SUT[1:0]
(1)
CK
Delay Counters
TIMEOUT
SymbolParameterConditionMinTypMaxUnits
Power-on Reset Threshold
Voltage (rising)
V
POT
Power-on Reset Threshold
Voltage (falling)
(2)
TBDTBDTBDV
TBDTBDTBDV
2514A–AVR–08/02
V
t
RST
RST
RESET Pin Threshold VoltageTBDTBDTBDV
Minimum pulse width on RESET
Pin
Notes:1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below V
(falling)
TBDTBDTBDns
POT
37
Power-on ResetA Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 16. The POR is activated whenever V
is below the
CC
detection level. The POR circuit can be used to trigger the start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after V
again, without any delay, when V
External ResetAn External Reset is generated by a low level on the RESET pin. Reset pulses longer
than the minimum pulse width (see Table 16) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied
signal reaches the Reset Threshold Voltage – V
counter starts the MCU after the Time-out period – t
Figure 17. External Reset During Operation
CC
– on its positive edge, the delay
RST
– has expired.
TOUT
Brown-out DetectionATmega169 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V
level during operation by comparing it to a fixed trigger level. The trigger level for the
BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to
ensure spike free Brown-out Detection. The hysteresis on the detection level should be
interpreted as V
BOT+=VBOT+VHYST
Table 17. BODLEVEL Fuse Coding
BODLEVEL 2..0 FusesMin V
111BOD Disabled
1101.8
1004.3
011
010
001
000
Note:1. V
may be below nominal minimum operating voltage for some devices. For
BOT
devices where this is the case, the device is tested down to V
production test. This guarantees that a Brown-Out Reset will occur before V
to a voltage where correct operation of the microcontroller is no longer guaranteed.
ThetestisperformedusingBODLEVEL = 110forATmega169Vand
BODLEVEL = 101 for ATmega169L.
/2 and V
(1)
BOT
BOT-=VBOT-VHYST
Typ V
BOT
Reserved
/2.
Max V
CC=VBOT
BOT
Units
V1012.7
during the
drops
CC
CC
2514A–AVR–08/02
Table 18. Brown-out Characteristics
SymbolParameterMinTypMaxUnits
V
t
HYST
BOD
Brown-out Detector Hysteresis50mV
Min Pulse Width on Brown-out Resetns
39
When the BOD is enabled, and VCCdecreases to a value below the trigger level (V
BOT-
in Figure 18), the Brown-out Reset is immediately activated. When VCCincreases above
the trigger level (V
out period t
has expired.
TOUT
The BOD circuit will only detect a drop in V
for longer than t
BOD
in Figure 18), the delay counter starts the MCU after the Time-
BOT+
if the voltage stays below the trigger level
CC
given in Table 16.
Figure 18. Brown-out Reset During Operation
V
CC
RESET
TIME-OUT
INTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
Watchdog ResetWhen the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
t
. Refer to page 42 for details on operation of the Watchdog Timer.
TOUT
Figure 19. Watchdog Reset During Operation
CC
CK
MCU Status Register –
MCUSR
40
ATmega169V/L
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit76543210
–––JTRFWDRFBORFEXTRFPORFMCUSR
Read/WriteRRRR/WR/WR/WR/WR/W
Initial Value000See Bit Description
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
2514A–AVR–08/02
ATmega169V/L
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
To make use of the Reset flags to identify a reset condition, the user should read and
then reset the MCUSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the reset
flags.
Internal Voltage
Reference
Voltage Reference Enable
Signals and Start-up Time
ATmega169 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used.
The start-up time is given in Table 19. To save power, the reference is not always turned
on. The reference is on during the following situations:
1.When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2.When the bandgap reference is connected to the Analog Comparator (by setting
the ACBG bit in ACSR).
3.When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the
user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user
can avoid the three conditions above to ensure that the reference is turned off before
entering Power-down mode.
Table 19. Internal Voltage Reference Characteristics
SymbolParameterConditionMinTypMaxUnits
V
BG
t
BG
I
BG
Bandgap reference voltageTBDTBD1.1TBDV
Bandgap reference start-up timeTBD4070µs
Bandgap reference current
consumption
(1)
TBD10TBDµA
2514A–AVR–08/02
Note:1. Values are guidelines only. Actual values are TBD.
41
Watchdog TimerThe Watchdog Timer is clocked from a separate On-chip Oscillator which runs at
1 MHz. This is the typical value at V
at other V
levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset
CC
interval can be adjusted as shown in Table 21 on page 43. The WDR – Watchdog Reset
– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is
disabled and when a Chip Reset occurs. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another
Watchdog Reset, the ATmega169 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 21 on page 43.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out
period, two different safety levels are selected by the fuse WDTON as shown in Table
20. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer”
on page 44 for details.
Table 20. WDT Configuration as a Function of the Fuse Settings of WDTON
= 5V. See characterization data for typical values
CC
Safety
WDTON
Unprogrammed1DisabledTimed sequenceTimed sequence
Programmed2EnabledAlways enabledTimed sequence
Level
WDT Initial
State
How to Disable the
WDT
How to Change
Time-out
Figure 20. Watchdog Timer
WATCHDOG
OSCILLATOR
42
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Watchdog Timer Control
Register – WDTCR
Bit76543210
–––WDCEWDEWDP2WDP1WDP0WDTCR
Read/WriteRRRR/WR/WR/WR/WR/W
InitialValue0000 0000
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega169 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This
bit must also be set when changing the prescaler bits. See “Timed Sequences for
Changing the Configuration of the Watchdog Timer” on page 44.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:
1.In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE even though it is set to one before the disable operation starts.
2.Within the next four clock cycles, write a logic 0 to WDE. This disables the
Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the
Watchdog Timer” on page 44.
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
Timeout Periods are shown in Table 21.
Table 21. Watchdog Timer Prescale Select
Number of WDT
WDP2WDP1WDP0
00016K cycles17.1 ms16.3 ms
00132K cycles34.3 ms32.5 ms
01064K cycles68.5 ms65 ms
011128K cycles0.14 s0.13 s
100256K cycles0.27 s0.26 s
101512K cycles0.55 s0.52 s
1101,024K cycles1.1 s1.0 s
1112,048K cycles2.2 s2.1 s
Oscillator Cycles
Typical Time-out
at VCC=3.0V
Typical Time-out
at VCC=5.0V
2514A–AVR–08/02
43
The following code example shows one assembly and one C function for turning off the
WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during execution of these functions.
Assembly Code Example
WDT_off:
; Write logical one to WDCE and WDE
ldi r16, (1<<WDCE)|(1<<WDE)
out WDTCR, r16
; Turn off WDT
ldi r16, (0<<WDE)
out WDTCR, r16
ret
C Code Example
void WDT_off(void)
{
Write logical one to WDCE and WDE
/*
WDTCR = (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
Note:1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,
and “SBI” instructions must be replaced with instructions that allow access to
extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and
“CBR”.
(1)
(1)
*/
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels.
Separate procedures are described for each level.
Safety Level 1In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the
WDE bit to 1 without any restriction. A timed sequence is needed when changing the
Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an
enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed:
1.In the same operation, write a logic one to WDCE and WDE. A logic one must be
written to WDE regardless of the previous value of the WDE bit.
2.Within the next four clock cycles, in the same operation, write the WDE and
WDP bits as desired, but with the WDCE bit cleared.
Safety Level 2In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read
as one. A timed sequence is needed when changing the Watchdog Time-out period. To
change the Watchdog Time-out, the following procedure must be followed:
1.In the same operation, write a logical one to WDCE and WDE. Even though the
WDE always is set, the WDE must be written to one to start the timed sequence.
2.Within the next four clock cycles, in the same operation, write the WDP bits as
desired, but with the WDCE bit cleared. The value written to the WDE bit is
irrelevant.
44
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
InterruptsThis section describes the specifics of the interrupt handling as performed in
ATmega169. For a general explanation of the AVR interrupt handling, refer to “Reset
and Interrupt Handling” on page 12.
Notes:1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader
address at reset, see “Boot Loader Support – Read-While-Write Self-Programming”
on page 251.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of
the Boot Flash Section. The address of each Interrupt Vector will then be the address
in this table added to the start address of the Boot Flash Section.
2514A–AVR–08/02
45
Table 23 shows reset and Interrupt Vectors placement for the various combinations of
BOOTRST and IVSEL settings. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the
Interrupt Vectors are in the Boot section or vice versa.
Note:1. The Boot Reset Address is shown in Table 113 on page 263. For the BOOTRST
Fuse “1” means unprogrammed while “0” means programmed.
(1)
The most typical and general program setup for the Reset and Interrupt Vector
Addresses in ATmega169 is:
AddressLabels CodeComments
0x0000jmpRESET; Reset Handler
0x0002jmpEXT_INT0; IRQ0 Handler
0x0004jmpPCINT0; PCINT0 Handler
0x0006jmpPCINT1; PCINT0 Handler
0x0008jmpTIM2_COMP; Timer2 Compare Handler
0x000AjmpTIM2_OVF; Timer2 Overflow Handler
0x000CjmpTIM1_CAPT; Timer1 Capture Handler
0x000EjmpTIM1_COMPA; Timer1 CompareA Handler
0x0010jmpTIM1_COMPB; Timer1 CompareB Handler
0x0012jmpTIM1_OVF; Timer1 Overflow Handler
0x0014jmpTIM0_COMP; Timer0 Compare Handler
0x0016jmpTIM0_OVF; Timer0 Overflow Handler
0x0018jmpSPI_STC; SPI Transfer Complete Handler
0x001AjmpUSART0_RXC; USART0 RX Complete Handler
0x001CjmpUSART0_DRE; USART0,UDR Empty Handler
0x001EjmpUSART0_TXC; USART0 TX Complete Handler
0x0020jmpUSI_STRT; USI Start Condition Handler
0x0022jmpUSI_OVFL; USI Overflow Handler
0x0024jmpADC; ADC Conversion Complete Handler
0x0026jmpANA_COMP; Analog Comparator Handler
0x0028jmpEE_RDY; EEPROM Ready Handler
0x002AjmpSPM_RDY; SPM Ready Handler
0x002CjmpLCD_SOF; LCD Start of Frame Handler
;
0x002ERESET: ldir16, high(RAMEND); Main program start
0x002FoutSPH,r16Set Stack Pointer to top of RAM
0x0030ldir16, low(RAMEND)
0x0031outSPL,r16
0x0032sei; Enable interrupts
0x0033<instr>xxx
............
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ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and
the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels CodeComments
0x0000RESET: ldir16,high(RAMEND) ; Main program start
0x0001outSPH,r16; Set Stack Pointer to top of RAM
0x0002ldir16,low(RAMEND)
0x0003outSPL,r16
0x0004sei; Enable interrupts
0x0005<instr>xxx
;
.org 0x1C02
0x1C02jmpEXT_INT0; IRQ0 Handler
0x1C04jmpPCINT0; PCINT0 Handler
.........;
0x1C2CjmpSPM_RDY; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the
most typical and general program setup for the Reset and Interrupt Vector Addresses is:
AddressLabels CodeComments
.org 0x0002
0x0002jmpEXT_INT0; IRQ0 Handler
0x0004jmpPCINT0; PCINT0 Handler
.........;
0x002CjmpSPM_RDY; Store Program Memory Ready Handler
;
.org 0x1C00
0x1C00RESET: ldir16,high(RAMEND) ; Main program start
0x1C01outSPH,r16; Set Stack Pointer to top of RAM
0x1C02ldir16,low(RAMEND)
0x1C03outSPL,r16
0x1C04sei; Enable interrupts
0x1C05<instr>xxx
2514A–AVR–08/02
47
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:
0x1C2CjmpSPM_RDY; Store Program Memory Ready Handler
;
0x1C2ERESET: ldir16,high(RAMEND) ; Main program start
0x1C2FoutSPH,r16; Set Stack Pointer to top of RAM
0x1C30ldir16,low(RAMEND)
0x1C31outSPL,r16
0x1C32sei; Enable interrupts
0x1C33<instr>xxx
Moving Interrupts Between
Application and Boot Space
MCU Control Register –
MCUCR
The General Interrupt Control Register controls the placement of the Interrupt Vector
table.
Bit76543210
JTD––PUD––IVSELIVCEMCUCR
Read/WriteR/WRRR/WRRR/WR/W
InitialValue0 0000000
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot
Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support – Read-While-Write Self-Programming” on page 251 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed
to change the IVSEL bit:
1.Write the Interrupt Vector Change Enable (IVCE) bit to one.
2.Within four cycles, write the desired value to IVSEL while writing a zero to
IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four
cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If
Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section “Boot Loader Support – Read-While-Write Self-Programming” on page 251
for details on Boot Lock bits.
48
ATmega169V/L
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ATmega169V/L
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is
cleared by hardware four cycles after it is written or when IVSEL is written. Setting the
IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code
Example below.
Assembly Code Example
Move_interrupts:
; Enable change of Interrupt Vectors
ldi r16, (1<<IVCE)
out MCUCR, r16
; Move interrupts to Boot Flash section
ldi r16, (1<<IVSEL)
out MCUCR, r16
ret
C Code Example
void Move_interrupts(void)
{
Enable change of Interrupt Vectors
/*
MCUCR = (1<<IVCE);
/* Move interrupts to Boot Flash section */
MCUCR = (1<<IVSEL);
}
*/
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49
I/O-Ports
IntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The
same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough
to drive LED displays directly. All port pins have individually selectable pull-up resistors
with a supply-voltage invariant resistance. All I/O pins have protection diodes to both
V
and Ground as indicated in Figure 21. Refer to “Electrical Characteristics” on page
CC
296 for a complete list of parameters.
Figure 21. I/O Pin Equivalent Schematic
R
pu
Pxn
C
pin
All registers and bit references in this section are written in general form. A lower case
“x” represents the numbering letter for the port, and a lower case “n” represents the bit
number. However, when using the register or bit defines in a program, the precise form
must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally
as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 72.
Three I/O memory address locations are allocated for each port, one each for the Data
Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The
Port Input Pins I/O location is read only, while the Data Register and the Data Direction
Register are read/write. However, writing a logic one to a bit in the PINx Register, will
result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up
Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when
set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on
page 51. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described
in “Alternate Port Functions” on page 55. Refer to the individual module sections for a
full description of the alternate functions.
See Figure
"General Digital I/O" for
Logic
Details
50
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Note that enabling the alternate function of some of the port pins does not affect the use
of the other pins in the port as general digital I/O.
Ports as General Digital
I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a
functional description of one I/O-port pin, here generically called Pxn.
Note:1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk
, SLEEP, and PUD are common to all ports.
I/O
Configuring the PinEach port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“Register Description for I/O-Ports” on page 72, the DDxn bits are accessed at the
DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at
the PINx I/O address.
TheDDxnbitintheDDRxRegisterselectsthedirectionofthispin.IfDDxniswritten
logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up
resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic
zero or the pin has to be configured as an output pin. The port pins are tri-stated when
reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
2514A–AVR–08/02
51
Toggling the PinWriting a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
Switching Between Input and
Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =
0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in
the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 24 summarizes the control signals for the pin value.
Table 24. Port Pin Configurations
PUD
DDxnPORTxn
00XInputNoTri-state (Hi-Z)
010InputYes
011InputNoTri-state (Hi-Z)
10XOutputNoOutput Low (Sink)
11XOutputNoOutput High (Source)
(in MCUCR)I/OPull-upComment
Pxn will source current if ext. pulled
low.
ReadingthePinValueIndependent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
23 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 23. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
INSTRUCTIONS
XXXin r17, PINx
XXX
SYNC LATCH
PINxn
r17
0x000xFF
t
pd, max
t
pd, min
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ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a
single signal transition on the pin will be delayed between ½ and 1½ system clock
period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock
period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
0xFF
out PORTx, r16nopin r17, PINx
0x000xFF
t
pd
2514A–AVR–08/02
53
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The
resulting pin values are read back again, but as previously discussed, a
nop
instruction
is included to be able to read back the value recently assigned to some of the pins.
Assembly Code Example
...
Define pull-ups and set outputs high
;
;
Define directions for port pins
ldir16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldir17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
outPORTB,r16
outDDRB,r17
Insert nop for synchronization
;
nop
Read port pins
;
inr16,PINB
...
(1)
C Code Example
unsigned char i;
...
Define pull-ups and set outputs high
/*
Define directions for port pins
/*
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
Insert nop for synchronization
/*
_NOP();
Read port pins
/*
i = PINB;
...
*/
*/
*/
*/
Digital Input Enable and Sleep
Modes
54
ATmega169V/L
Note:1. For the assembly program, two temporary registers are used to minimize the time
from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,
defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
As shown in Figure 22, the digital input signal can be clamped to ground at the input of
the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, and Standby mode to avoid high
power consumption if some input signals are left floating, or have an analog signal level
close to V
CC
/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also
overridden by various other alternate functions as described in “Alternate Port Functions” on page 55.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the
external interrupt is
not
enabled, the corresponding External Interrupt Flag will be set
when resuming from the above mentioned Sleep mode, as the clamping in these sleep
mode produces the requested logic change.
2514A–AVR–08/02
ATmega169V/L
Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os. Figure
25 shows how the port pin control signals from the simplified Figure 22 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but
the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 25. Alternate Port Functions
1
0
1
0
Pxn
1
0
1
0
(1)
PUOExn
PUOVxn
DDOExn
DDOVxn
PVOExn
PVOVxn
DIEOExn
DIEOVxn
SLEEP
SYNCHRONIZER
SET
DLQ
Q
CLR
D
PINxn
PUD
D
Q
DDxn
Q
CLR
RESET
Q
D
PORTxn
Q
CLR
RESET
Q
Q
CLR
1
0
WDx
RDx
RRx
clk
RPx
PTOExn
WPx
WRx
I/O
DATA BU S
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:SLEEP CONTROL
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
clk
, SLEEP, and PUD are common to all ports. All other signals are unique for each
I/O
pin.
Table 25 summarizes the function of the overriding signals. The pin and port indexes
from Figure 25 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.
2514A–AVR–08/02
55
Table 25. Generic Description of Overriding Signals for Alternate Functions
Signal NameFull NameDescription
PUOEPull-up Override
Enable
PUOVPull-up Override
Value
DDOEData Direction
Override Enable
DDOVData Direction
Override Value
PVOEPort Value
Override Enable
PVOVPort Value
Override Value
PTOEPort Toggle
Override Enable
DIEOEDigital Input
Enable Override
Enable
If this signal is set, the pull-up enable is controlled by the
PUOV signal. If this signal is cleared, the pull-up is
enabled when {DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when
PUOV is set/cleared, regardless of the setting of the
DDxn, PORTxn, and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled
by the DDOV signal. If this signal is cleared, the Output
driver is enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled
when DDOV is set/cleared, regardless of the setting of
the DDxn Register bit.
If this signal is set and the Output Driver is enabled, the
port value is controlled by the PVOV signal. If PVOE is
cleared, and the Output Driver is enabled, the port Value
is controlled by the PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless
of the setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by
the DIEOV signal. If this signal is cleared, the Digital Input
Enable is determined by MCU state (Normal mode, sleep
mode).
DIEOVDigital Input
Enable Override
Value
DIDigital InputThis is the Digital Input to alternate functions. In the
AIOAnalog
Input/Output
If DIEOE is set, the Digital Input is enabled/disabled
when DIEOV is set/cleared, regardless of the MCU state
(Normal mode, sleep mode).
figure, the signal is connected to the output of the schmitt
trigger but before the synchronizer. Unless the Digital
Input is used as a clock source, the module with the
alternate function will use its own synchronizer.
This is the Analog Input/output to/from alternate
functions. The signal is connected directly to the pad, and
can be used bi-directionally.
The following subsections shortly describe the alternate functions for each port, and
relate the overriding signals to the alternate function. Refer to the alternate function
description for further details.
56
ATmega169V/L
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MCU Control Register –
MCUCR
Bit76543210
JTD––PUD––IVSELIVCEMCUCR
Read/WriteR/WRRR/WRRR/WR/W
Initial Value00000000
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn
and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See “Configuring the Pin” on page 51 for more details about this feature.
Alternate Functions of Port AThe Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller.
Table 26. Port A Pins Alternate Functions
Port PinAlternate Function
PA7SEG3 (LCD Front Plane 3)
PA6SEG2 (LCD Front Plane 2)
PA5SEG1 (LCD Front Plane 1)
PA4SEG0 (LCD Front Plane 0)
PA3COM3 (LCD Back Plane 3)
PA2COM2 (LCD Back Plane 2)
PA1COM1 (LCD Back Plane 1)
PA0COM0 (LCD Back Plane 0)
Table 27 and Table 28 relates the alternate functions of Port A to the overriding signals
shown in Figure 25 on page 55.
Table 27. Overriding Signals for Alternate Functions in PA7..PA4
Signal NamePA7/SEG3PA6/SEG2PA5/SEG1PA4/SEG0
PUOELCDENLCDENLCDENLCDEN
PUOV0000
DDOELCDENLCDENLCDENLCDEN
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOELCDENLCDENLCDENLCDEN
DIEOV0000
DI––––
AIOSEG3SEG2SEG1SEG0
2514A–AVR–08/02
57
Table 28. Overriding Signals for Alternate Functions in PA3..PA0
Signal NamePA3/COM3PA2/COM2PA1/COM1PA0/COM0
PUOELCDEN •
(LCDMUX>2)
PUOV0000
DDOELCDEN •
(LCDMUX>2)
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOELCDEN •
(LCDMUX>2)
DIEOV0000
DI––––
AIOCOM3COM2COM1COM0
LCDEN •
(LCDMUX>1)
LCDEN •
(LCDMUX>1)
LCDEN •
(LCDMUX>1)
LCDEN •
(LCDMUX>0)
LCDEN •
(LCDMUX>0)
LCDEN •
(LCDMUX>0)
Alternate Functions of Port BThe Port B pins with alternate functions are shown in Table 29.
Table 29. Port B Pins Alternate Functions
Port PinAlternate Functions
PB7
OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin
Change Interrupt15).
LCDEN
LCDEN
LCDEN
PB6
PB5
PB4
PB3MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt11).
PB2MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt10).
PB1SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt9).
PB0SS
OC1B/PCINT14 (Output Compare and PWM Output B for Timer/Counter1 or Pin
Change Interrupt14).
OC1A/PCINT13 (Output Compare and PWM Output A for Timer/Counter1 or Pin
Change Interrupt13).
OC0A/PCINT12 (Output Compare and PWM Output A for Timer/Counter0 or Pin
Change Interrupt12).
/PCINT8 (SPI Slave Select input or Pin Change Interrupt8).
The alternate pin configuration is as follows:
• OC2A/PCINT15, Bit 7
OC2, Output Compare Match A output: The PB7 pin can serve as an external output for
the Timer/Counter2 Output Compare A. The pin has to be configured as an output
(DDB7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM
mode timer function.
PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt source.
58
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ATmega169V/L
• OC1B/PCINT14, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output
(DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM
mode timer function.
PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.
• OC1A/PCINT13, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output
for the Timer/Counter1 Output Compare A. The pin has to be configured as an output
(DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM
mode timer function.
PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt source.
• OC0A/PCINT12, Bit 4
OC0A, Output Compare Match A output: The PB4 pin can serve as an external output
for the Timer/Counter0 Output Compare A . The pin has to be configured as an output
(DDB4 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM
mode timer function.
PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt source.
• MISO/PCINT11 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external interrupt source.
• MOSI/PCINT10 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external interrupt source.
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59
• SCK/PCINT9 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a Slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI is enabled as a Master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt
source.
• SS
/PCINT8 – Port B, Bit 0
: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured
SS
as an input regardless of the setting of DDB0. As a Slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit
PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt
source.
Table 30 and Table 31 relate the alternate functions of Port B to the overriding signals
shown in Figure 25 on page 55. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute
the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE
INPUT.
Table 30. Overriding Signals for Alternate Functions in PB7..PB4
Alternate Functions of Port CThe Port C has an alternate function as the SEG5:12 for the LCD Controller
Table 32. Port C Pins Alternate Functions
Port PinAlternate Function
PC7SEG5 (LCD Front Plane 5)
PC6SEG6 (LCD Front Plane 6)
PC5SEG7 (LCD Front Plane 7)
PC4SEG8 (LCD Front Plane 8)
PC3SEG9 (LCD Front Plane 9)
PC2SEG10 (LCD Front Plane 10)
PC1SEG11 (LCD Front Plane 11)
PC0SEG12 (LCD Front Plane 12)
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61
Table 33 and Table 34 relate the alternate functions of Port C to the overriding signals
shown in Figure 25 on page 55.
Table 33. Overriding Signals for Alternate Functions in PC7..PC4
Signal
NamePC7/SEG5PC6/SEG6PC5/SEG7PC4/SEG8
PUOELCDENLCDENLCDENLCDEN
PUOV0000
DDOELCDENLCDENLCDENLCDEN
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOELCDENLCDENLCDENLCDEN
DIEOV0000
DI––––
AIOSEG5SEG6SEG7SEG8
Table 34. Overriding Signals for Alternate Functions in PC3..PC0
Signal
NamePC3/SEG9PC2/SEG10PC1/SEG11PC0/SEG12
PUOELCDENLCDENLCDENLCDEN
PUOV0000
DDOELCDENLCDENLCDENLCDEN
DDOV0000
PVOE0000
PVOV0000
PTOE–– ––
DIEOELCDENLCDENLCDENLCDEN
DIEOV0000
DI–– ––
AIOSEG9SEG10SEG11SEG12
62
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Alternate Functions of Port DThe Port D pins with alternate functions are shown in Table 35.
Table 35. Port D Pins Alternate Functions
Port PinAlternate Function
PD7SEG15 (LCD front plane 15)
PD6SEG16 (LCD front plane 16)
PD5SEG17 (LCD front plane 17)
PD4SEG18 (LCD front plane 18)
PD3SEG19 (LCD front plane 19)
PD2SEG20 (LCD front plane 20)
PD1INT0/SEG21 (External Interrupt0 Input or LCD front plane 21)
PD0ICP/ SEG22 (Timer/Counter1 Input Capture Trigger or LCD front plane 22)
The alternate pin configuration is as follows:
• SEG15 - SEG20 – Port D, Bit 7:2
SEG15-SEG20, LCD front plane 15-20.
• INT0/SEG21 – Port D, Bit 1
INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt
source to the MCU.
SEG21, LCD front plane 21.
• ICP/SEG22 – Port D, Bit 0
ICP – Input Capture pin1: The PD0 pin can act as an Input Capture pin for
Timer/Counter1.
SEG22, LCD front plane 22
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63
Table 36 and Table 37 relates the alternate functions of Port D to the overriding signals
shown in Figure 25 on page 55.
Table 36. Overriding Signals for Alternate Functions PD7..PD4
Signal
NamePD7/SEG15PD6/SEG16PD5/SEG17PD4/SEG18
PUOELCDEN •
(LCDPM>1)
PUOV0000
DDOELCDEN •
(LCDPM>1)
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOELCDEN •
(LCDPM>1)
DIEOV0000
DI––––
AIOSEG15SEG16SEG17SEG18
LCDEN •
(LCDPM>1)
LCDEN •
(LCDPM>1)
LCDEN •
(LCDPM>1)
LCDEN •
(LCDPM>2)
LCDEN •
(LCDPM>2)
LCDEN •
(LCDPM>2)
LCDEN •
(LCDPM>2)
LCDEN •
(LCDPM>2)
LCDEN •
(LCDPM>2)
Table 37. Overriding Signals for Alternate Functions in PD3..PD0
Signal
NamePD3/SEG19PD2/SEG20PD1/INT0/SEG21PD0/ICP/SEG22
PUOELCDEN •
(LCDPM>3)
LCDEN •
(LCDPM>3)
LCDEN •
(LCDPM>4)
LCDEN •
(LCDPM>4)
64
PUOV0000
DDOELCDEN •
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOELCDEN •
DIEOV00LCDEN
DI––INT0 INPUTICP INPUT
AIO––
ATmega169V/L
(LCDPM>3)
(LCDPM>3)
LCDEN •
(LCDPM>3)
LCDEN •
(LCDPM>3)
LCDEN •
(LCDPM>4)
LCDEN + (INT0
ENABLE)
• (INT0
ENABLE)
LCDEN •
(LCDPM>4)
LCDEN •
(LCDPM>4)
0
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Alternate Functions of Port EThe Port E pins with alternate functions are shown in Table 38.
Table 38. Port E Pins Alternate Functions
Port PinAlternate Function
PE7
PE6DO/PCINT6 (USI Data Output or Pin Change Interrupt6)
PE5DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5)
PE4
PE3AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3)
PE2
PE1TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1)
PE0RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0)
PCINT7 (Pin Change Interrupt7)
CLKO (Divided System Clock)
USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or
Pin Change Interrupt4)
XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input
or Pin Change Interrupt2)
• PCINT7 – Port E, Bit 7
PCINT7, Pin Change Interrupt Source 7: The PE7 pin can serve as an external interrupt
source.
CLKO, Divided System Clock: The divided system clock can be output on the PE7 pin.
The divided system clock will be output if the CKOUT Fuse is programmed, regardless
of the PORTE7 and DDE7 settings. It will also be output during reset.
• DO/PCINT6 – Port E, Bit 6
DO, Universal Serial Interface Data output.
PCINT6, Pin Change Interrupt Source 6: The PE6 pin can serve as an external interrupt
source.
• DI/SDA/PCINT5 – Port E, Bit 5
DI, Universal Serial Interface Data input.
SDA, Two-wire Serial Interface Data:
PCINT5, Pin Change Interrupt Source 5: The PE5 pin can serve as an external interrupt
source.
• USCK/SCL/PCINT4 – Port E, Bit 4
USCK, Universal Serial Interface Clock.
SCL, Two-wire Serial Interface Clock.
PCINT4, Pin Change Interrupt Source 4: The PE4 pin can serve as an external interrupt
source.
• AIN1/PCINT3 – Port E, Bit 3
AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative
input of the Analog Comparator.
PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt
source.
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65
• XCK/AIN0/PCINT2 – Port E, Bit 2
XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the
clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the
USART operates in synchronous mode.
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive
input of the Analog Comparator.
PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt
source.
• TXD/PCINT1 – Port E, Bit 1
TXD0, UART0 Transmit pin.
PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt
source.
• RXD/PCINT0 – Por t E, Bit 0
RXD, USART Receive pin. Receive Data (Data input pin for the USART). When the
USART Receiver is enabled this pin is configured as an input regardless of the value of
DDE0. When the USART forces this pin to be an input, a logical one in PORTE0 will turn
on the internal pull-up.
PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt
source.
Table 39 and Table 40 relates the alternate functions of Port E to the overriding signals
shown in Figure 25 on page 55.
Table 39. Overriding Signals for Alternate Functions PE7..PE4
Signal
NamePE7/PCINT7
PUOE00USI_TWO-WIRE0
PUOV0000
DDOECKOUT
DDOV10(SDA
PVOECKOUT
PVOVclk
PTOE–– –USITC
DIEOEPCINT7 •
PCIE0
DIEOV1111
DIPCINT7
INPUT
AIO––––
(1)
(1)
I/O
PE6/DO/
PCINT6
0USI_TWO-WIREUSI_TWO-WIRE
USI_THREEWIRE
DO00
PCINT6 •
PCIE0
PCINT6
INPUT
PE5/DI/SDA/
PCINT5
+PORTE5) •
DDE5
USI_TWO-WIRE •
DDE5
(PCINT5 • PCIE0)
+ USISIE
DI/SDA INPUT
PCINT5 INPUT
PE4/USCK/SCL/
PCINT4
(USI_SCL_HOLD +
PORTE4
USI_TWO-WIRE •
DDE4
(PCINT4 • PCIE0) +
USISIE
USCKL/SCL INPUT
PCINT4 INPUT
) + DDE4
66
Note:1. CKOUT is one if the CKOUT Fuse is programmed
ATmega169V/L
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ATmega169V/L
Table 40. Overriding Signals for Alternate Functions in PE3..PE0
Note:1. AIN0D and AIN1D is described in “Digital Input Disable Register 0 – DIDR0” on page
PE3/AIN1/
PCINT3
PCIE0) +
(1)
AIN1D
190.
PE2/XCK/AIN0/
PCINT2
ENABLE
(PCINT2 • PCIE0) +
(1)
AIN0D
PE1/TXD/
PCINT1PE0/RXD/PCINT0
TXENRXEN
PCINT1 •
PCIE0
PCINT0 • PCIE0
INPUT
Alternate Functions of Port FThe Port F has an alternate function as analog input for the ADC as shown in Table 41.
If some Port F pins are configured as outputs, it is essential that these do not switch
when a conversion is in progress. This might corrupt the result of the conversion. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and
PF4(TCK) will be activated even if a reset occurs.
Table 41. Port F Pins Alternate Functions
Port PinAlternate Function
PF7ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
PF4ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
PF3ADC3 (ADC input channel 3)
PF2ADC2 (ADC input channel 2)
PF1ADC1 (ADC input channel 1)
PF0ADC0 (ADC input channel 0)
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7
.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin.
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67
• TCK, ADC6 – Por t F, Bit 6
ADC6, Analog to Digital Converter, Channel 6
.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register.
When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5
.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin.
• TDO, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4
.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3-0.
Table 42. Overriding Signals for Alternate Functions in PF7..PF4
Signal
NamePF7/ADC7/TDIPF6/ADC6/TDOPF5/ADC5/TMSPF4/ADC4/TCK
PUOEJTAGENJTAGENJTAGENJTAGEN
PUOV1011
DDOEJTAGENJTAGENJTAGENJTAGEN
DDOV0SHIFT_IR +
SHIFT_DR
PVOE0JTAGEN00
PVOV0TDO00
PTOE––– –
DIEOEJTAGENJTAGENJTAGENJTAGEN
DIEOV0000
DITDI–TMSTCK
AIOADC7 INPUTADC6 INPUTADC5 INPUTADC4 INPUT
00
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Table 43. Overriding Signals for Alternate Functions in PF3..PF0
Signal
NamePF3/ADC3PF2/ADC2PF1/ADC1PF0/ADC0
PUOE0000
PUOV0000
DDOE0000
DDOV0000
PVOE0000
PVOV0000
PTOE––––
DIEOE0000
DIEOV0000
DI––––
AIOADC3 INPUTADC2 INPUTADC1 INPUTADC0 INPUT
Alternate Functions of Port GThe alternate pin configuration is as follows:
Table 44. Port G Pins Alternate Functions
ATmega169V/L
Port PinAlternate Function
PG5RESET
PG4T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23)
PG3T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24)
PG2SEG4 (LCD Front Plane 4)
PG1SEG13 (LCD Front Plane 13)
PG0SEG14 (LCD Front Plane 14)
(Reset pin)
The alternate pin configuration is as follows:
• RESET
RESET
– Port G, Bit 5
, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a
input only I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset
as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is
connected to the pin, and the pin can not be used as an input I/O pin.
If PG5 is used as a Reset pin, then PING5 will read 0.
• T0/SEG23 – Port G, Bit 4
T0, Timer/Counter0 Counter Source.
SEG23, LCD front plane 23
2514A–AVR–08/02
• T1/SEG24 – Port G, Bit 3
T1, Timer/Counter1 Counter Source.
SEG24, LCD front plane 24
69
• SEG4 – Port G, Bit 2
SEG4, LCD front plane 4
• SEG13 – Port G, Bit 1
SEG13, Segment driver 13
• SEG14 – Port G, Bit 0
SEG14, LCD front plane 14
Table 44 and Table 45 relates the alternate functions of Port G to the overriding signals
shown in Figure 25 on page 55.
Table 45. Overriding Signals for Alternate Functions in PG5:4
Signal
NamePG5/RESETPG4/T0/SEG23
PUOE1LCDEN • (LCDPM>5)
PUOV10
DDOE0LCDEN • (LCDPM>5)
DDOV01
PVOE00
PVOV00
PTOE––– –
DIEOERSTDISBL
DIEOV10
DI–T0 INPUT
AIORESET INPUTSEG23
Note:1. When the RSTDISBL Fuse is “0” (programmed).
(1)
LCDEN • (LCDPM>5)
70
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Table 46. Overriding Signals for Alternate Functions in PG3:0
External InterruptsThe External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins
are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles.
Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. The
PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asynchronously. This implies
that these interrupts can be used for waking the part also from sleep modes other than
Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set
up as indicated in the specification for the External Interrupt Control Register A –
EICRA. When the INT0 interrupt is enabled and is configured as level triggered, the
interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT0 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 23. Low level interrupt on INT0 is detected
asynchronously. This implies that this interrupt can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes
except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the
required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up TIme, the MCU
will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23.
External Interrupt Control
Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense
control.
Bit76543210
––––––ISC01ISC00EICRA
Read/WriteRRRRRRR/WR/W
InitialValue0000 0000
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 47. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 47. Interrupt 0 Sense Control
ISC01ISC00Description
00The low level of INT0 generates an interrupt request.
01Any logical change on INT0 generates an interrupt request.
10The falling edge of INT0 generates an interrupt request.
11The rising edge of INT0 generates an interrupt request.
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75
External Interrupt Mask
Register – EIMSK
Bit76543210
PCIE1PCIE0
Read/WriteR/WR/WRRRRRR/W
InitialValue0 0000000
–––––INT0E IMSK
• Bit 7 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the
PCMSK1 Register.
• Bit 6 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0
Register.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the External Interrupt Control Register A (EICRA) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
External Interrupt Flag
Register – EIFR
Bit76543210
PCIF1PCIF0
Read/WriteR/WR/WRRRRRR/W
InitialValue0 0000000
–––––INTF0EIFR
• Bit 7 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 6 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
76
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• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt
is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt
on the corresponding I/O pin is disabled.
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is
enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on
the corresponding I/O pin is disabled.
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77
8-bit Timer/Counter0
with PWM
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The
main features are:
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)
OverviewA simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For the
actual placement of I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
page 88.
Figure 26. 8-bit Timer/Counter Block Diagram
TCCRn
count
clear
direction
BOTTOM
Timer/Counter
TCNTn
DATA BU S
=
OCRn
= 0
Control Logic
TOP
= 0xFF
Wavefo rm
Generation
Clock Select
Edge
Detector
( From Prescaler )
clk
Tn
TOVn
(Int.Req.)
Tn
OCn
(Int.Req.)
OCn
RegistersThe Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers.
Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer
Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T0 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
).
T0
The double buffered Output Compare Register (OCR0A) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare
pin (OC0A). See “Output Compare Unit” on page 80. for details. The compare match
78
ATmega169V/L
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event will also set the Compare Flag (OCF0A) which can be used to generate an Output
Compare interrupt request.
DefinitionsMany register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the
Output Compare unit channel, in this case channel A. However, when using the register
or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 48 are also used extensively throughout the document.
Table 48. Definitions
BOTTOMThe counter reaches the BOTTOM when it becomes 0x00.
MAXThe counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOPThe counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The
assignment is dependent on the mode of operation.
Timer/Counter Clock
Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select
(CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on
clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on
page 92.
Counter UnitThe main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 27 shows a block diagram of the counter and its surroundings.
Figure 27. Counter Unit Block Diagram
TOVn
top
(Int.Req.)
clk
Tn
Clock Select
Edge
Detector
( From Prescaler )
Tn
DATA B US
count
TCNTnControl Logic
clear
direction
bottom
Signal description (internal signals):
countIncrement or decrement TCNT0 by 1.
2514A–AVR–08/02
directionSelect between increment and decrement.
clearClear TCNT0 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clkT0in the following.
topSignalize that TCNT0 has reached maximum value.
bottomSignalize that TCNT0 has reached minimum value (zero).
79
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk
). clkT0can be generated from an external or internal
T0
clock source, selected by the Clock Select bits (CS02:0). When no clock source is
selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed
by the CPU, regardless of whether clk
is present or not. A CPU write overrides (has
T0
priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits
located in the Timer/Counter Control Register (TCCR0A). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the
Output Compare output OC0A. For more details about advanced counting sequences
and waveform generation, see “Modes of Operation” on page 83.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation
selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
Output Compare UnitThe 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match
will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled
(OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A flag is automatically cleared when the
interrupt is executed. Alternatively, the OCF0A flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal
to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the
Waveform Generator for handling the special cases of the extreme values in some
modes of operation (See “Modes of Operation” on page 83.).
Figure 28 shows a block diagram of the Output Compare unit.
Figure 28. Output Compare Unit, Block Diagram
DATA BU S
OCRnx
= (8-bit Comparator )
top
bottom
FOCn
Waveform Generator
WGMn1:0
COMnX1:0
TCNTn
OCFnx (Int.Req.)
OCnx
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The OCR0A Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR0A Buffer Register, and if double
buffering is disabled the CPU will access the OCR0A directly.
Force Output CompareIn non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare
match will not set the OCF0A flag or reload/clear the timer, but the OC0A pin will be
updated as if a real compare match had occurred (the COM0A1:0 bits settings define
whether the OC0A pin is set, cleared or toggled).
Compare Match Blocking by
TCNT0 Write
Using the Output Compare
Unit
All CPU write operations to the TCNT0 Register will block any compare match that
occur in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR0A to be initialized to the same value as TCNT0 without triggering an interrupt
when the Timer/Counter clock is enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT0 when using the Output
Compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT0 equals the OCR0A value, the compare match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value
equal to BOTTOM when the counter is downcounting.
The setup of the OC0A should be performed before setting the Data Direction Register
for the port pin to output. The easiest way of setting the OC0A value is to use the Force
Output Compare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its
value even when changing between Waveform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare
value. Changing the COM0A1:0 bits will take effect immediately.
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81
Compare Match Output
Unit
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next
compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 29
shows a simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0
bits are shown. When referring to the OC0A state, the reference is for the internal OC0A
Register, not the OC0A pin. If a system reset occur, the OC0A Register is reset to “0”.
Figure 29. Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCn
clk
I/O
Waveform
Generator
DQ
1
OCnx
DQ
PORT
DATA BU S
DQ
DDR
0
OCn
Pin
The general I/O port function is overridden by the Output Compare (OC0A) from the
Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as
output before the OC0A value is visible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state
before the output is enabled. Note that some COM0A1:0 bit settings are reserved for
certain modes of operation. See “8-bit Timer/Counter Register Description” on page 88.
Compare Output Mode and
Waveform Generation
82
ATmega169V/L
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and
PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator
that no action on the OC0A Register is to be performed on the next compare match. For
compare output actions in the non-PWM modes refer to Table 50 on page 89. For fast
PWM mode, refer to Table 51 on page 89, and for phase correct PWM refer to Table 52
on page 90.
A change of the COM0A1:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOC0A strobe bits.
2514A–AVR–08/02
ATmega169V/L
Modes of OperationThe mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and
Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output
Unit” on page 82.).
For detailed timing information refer to Figure 33, Figure 34, Figure 35 and Figure 36 in
“Timer/Counter Timing Diagrams” on page 87.
Normal ModeThe simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then
restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag
(TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The
TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV0
flag, the timer resolution can be increased by software. There are no special cases to
consider in the Normal mode, a new counter value can be written anytime.
Clear Timer on Compare
Match (CTC) Mode
The Output Compare unit can be used to generate interrupts at some given time. Using
the Output Compare to generate waveforms in Normal mode is not recommended,
since this will occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used
to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for
the counter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 30. The counter value
(TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and
then counter (TCNT0) is cleared.
Figure 30. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCn
(Toggle)
Perio d
14
23
(COMnx1:0 = 1)
2514A–AVR–08/02
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be
used for updating the TOP value. However, changing TOP to a value close to BOTTOM
when the counter is running with none or a low prescaler value must be done with care
since the CTC mode does not have the double buffering feature. If the new value written
83
to OCR0A is lower than the current value of TCNT0, the counter will miss the compare
match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle
its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the
data direction for the pin is set to output. The waveform generated will have a maximum
frequency of f
OC0=fclk_I/O
/2 when OCR0A is set to zero (0x00). The waveform frequency
is defined by the following equation:
f
f
OCnx
The
N
variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
Fast PWM ModeThe fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM
option by its single-slope operation. The counter counts from BOTTOM to MAX then
restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and
cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the
fast PWM mode can be twice as high as the phase correct PWM mode that use dualslope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in Figure 31. The TCNT0 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent compare matches between OCR0A and TCNT0.
Figure 31. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
OCn
OCn
Perio d
1
23
4567
(COMnx1:0 = 2)
(COMnx1:0 = 3)
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ATmega169V/L
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If
the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the
OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 51
on page 89). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or
clearing) the OC0A Register at the compare match between OCR0A and TCNT0, and
clearing (or setting) the OC0A Register at the timer clock cycle the counter is cleared
(changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f
f
OCnxP WM
The
N
variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating
a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM,
the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A
equal to MAX will result in a constantly high or low output (depending on the polarity of
the output set by the COM0A1:0 bits.)
clk_I/O
------------------=
N 256⋅
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved
by setting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The
waveform generated will have a maximum frequency of f
OC0=fclk_I/O
/2 when OCR0A is
set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double
buffer feature of the Output Compare unit is enabled in the fast PWM mode.
Phase Correct PWM ModeThe phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from
MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A)
is cleared on the compare match between TCNT0 and OCR0A while upcounting, and
set on the compare match while downcounting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency
than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase
correct PWM mode the counter is incremented until the counter value matches MAX.
When the counter reaches MAX, it changes the count direction. The TCNT0 value will
be equal to MAX for one timer clock cycle. The timing diagram for the phase correct
PWM mode is shown on Figure 32. The TCNT0 value is in the timing diagram shown as
a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.
2514A–AVR–08/02
85
Figure 32. Phase Correct PWM Mode, Timing Diagram
TCNTn
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
OCn
OCn
Period
123
(COMnx1:0 = 2)
(COMnx1:0 = 3)
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter
reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on
the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An
inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 52
on page 90). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or
setting) the OC0A Register at the compare match between OCR0A and TCNT0 when
the counter increments, and setting (or clearing) the OC0A Register at compare match
between OCR0A and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
f
f
OCnxPCPWM
clk_I/O
------------------=
N 510⋅
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
86
The extreme values for the OCR0A Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to
BOTTOM, the output will be continuously low and if set equal to MAX the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Timer/Counter Timing
Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0)istherefore
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set. Figure 33 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value in all modes
other than phase correct PWM mode.
Figure 33. Timer/Counter Timing Diagram, no Prescaling
clk
I/O
clk
Tn
(clk
/1)
I/O
TCNTnMAX - 1MAXBOTTOMBOTTOM + 1
TOVn
Figure 34 shows the same timing data, but with the prescaler enabled.
Figure 34. Timer/Counter Timing Diagram, with Prescaler (f
clk
I/O
clk
Tn
(clk
/8)
I/O
clk_I/O
/8)
TCNTn
TOVn
MAX - 1MAXBOTTOMBOTTOM + 1
Figure 35 shows the setting of OCF0A in all modes except CTC mode.
Figure 35. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
clk
I/O
clk
Tn
(clk
/8)
I/O
TCNTn
OCRnx
OCFnx
OCRnx - 1OCRnxOCRnx + 1OCRnx + 2
OCRnx Value
clk_I/O
/8)
2514A–AVR–08/02
87
Figure 36 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 36. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (f
clk
I/O
clk
Tn
(clk
/8)
I/O
TCNTn
(CTC)
clk_I/O
/8)
TOP - 1TOPBOTTOMBOTTOM + 1
8-bit Timer/Counter
Register Description
Timer/Counter Control
Register A – TCCR0A
OCRnx
OCFnx
Bit76543210
FOC0AWGM00COM0A1COM0A0WGM01CS02CS01CS00TCCR0
Read/WriteWR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
TOP
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0 is written when operating in PWM mode. When writing a logical one to the
FOC0A bit, an immediate compare match is forced on the Waveform Generation unit.
The OC0A output is changed according to its COM0A1:0 bits setting. Note that the
FOC0A bit is implemented as a strobe. Therefore it is the value present in the
COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0A as TOP.
88
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare
match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table
49 and “Modes of Operation” on page 83.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Table 49. Waveform Generation Mode Bit Description
WGM01
Mode
Note:1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
(CTC0)
000Normal0xFFImmediateMAX
101PWM, Phase Correct0xFFTOPBOTTOM
210CTCOCR0AImmediateMAX
311Fast PWM0xFFTOPMAX
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
WGM00
(PWM0)
Timer/Counter
Mode of OperationTOP
(1)
Update of
OCR0A at
TOV0 Flag
Set on
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 50 shows the COM0A1:0 bit functionality when the
WGM01:0 bits are set to a normal or CTC mode (non-PWM).
Table 50. Compare Output Mode, non-PWM Mode
COM01COM00Description
00Normal port operation, OC0A disconnected.
01Toggle OC0A on compare match
10Clear OC0A on compare match
11Set OC0A on compare match
Table 51 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Table 51. Compare Output Mode, Fast PWM Mode
COM01COM00Description
00Normal port operation, OC0A disconnected.
01Reserved
10Clear OC0A on compare match, set OC0A at TOP
11Set OC0A on compare match, clear OC0A at TOP
Note:1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 84 for more details.
(1)
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89
Table 52 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to
phase correct PWM mode.
10Clear OC0A on compare match when up-counting. Set OC0A on
compare match when downcounting.
11Set OC0A on compare match when up-counting. Clear OC0A on
compare match when downcounting.
Note:1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
the compare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 85 for more details.
(1)
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 53. Clock Select Bit Description
CS02CS01CS00Description
000No clock source (Timer/Counter stopped)
001clk
010clk
011clk
100clk
101clk
110External clock source on T0 pin. Clock on falling edge.
/(No prescaling)
I/O
/8 (From prescaler)
I/O
/64 (From prescaler)
I/O
/256 (From prescaler)
I/O
/1024 (From prescaler)
I/O
Timer/Counter Register –
TCNT0
90
ATmega169V/L
111External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will
clock the counter even if the pin is configured as an output. This feature allows software
control of the counting.
Bit76543210
TCNT0[7:0]TCNT0
Read/WriteR/WR/WR/WR/WR/WR/WR /WR/W
InitialValue0000 0000
The Timer/Counter Register gives direct access, both for read and write operations, to
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)
the compare match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a compare match between TCNT0
and the OCR0A Register.
2514A–AVR–08/02
ATmega169V/L
Output Compare Register A –
OCR0A
Timer/Counter 0 Interrupt
Mask Register – TIMSK0
Bit76543210
OCR0A[7:0]OCR0
Read/WriteR/WR/WR/WR/WR/WR/WR /WR/W
InitialValue0000 0000
The Output Compare Register A contains an 8-bit value that is continuously compared
with the counter value (TCNT0). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC0A pin.
Bit765432 10
––––––OCIE0ATOIE0TIMSK0
Read/WriteRRRRRRR/WR/W
InitialValue0000 0000
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one),
the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt
is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is
set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Timer/Counter 0 Interrupt Flag
Register – TIFR0
Bit76543210
––––––OCF0ATOV0TIFR0
Read/WriteRRRRRRR/WR/W
InitialValue0000 0000
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0
and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0A is
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the
Timer/Counter0 Compare match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0
(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the
Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is
set when Timer/Counter0 changes counting direction at 0x00.
2514A–AVR–08/02
91
Timer/Counter0 and
Timer/Counter1
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to
both Timer/Counter1 and Timer/Counter0.
Prescalers
Internal Clock SourceThe Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 =
1). This provides the fastest operation, with a maximum Timer/Counter clock frequency
equal to system clock frequency (f
caler can be used as a clock source. The prescaled clock has a frequency of either
f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
Prescaler ResetThe prescaler is free running, i.e., operates independently of the Clock Select logic of
the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the
prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler
will have implications for situations where a prescaled clock is used. One example of
prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >
CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program
execution. However, care must be taken if the other Timer/Counter that shares the
same prescaler also uses prescaling. A prescaler reset will affect the prescaler period
for all Timer/Counters it is connected to.
). Alternatively, one of four taps from the pres-
CLK_I/O
/1024.
CLK_I/O
External Clock SourceAn external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clk
/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin syn-
T1
chronization logic. The synchronized (sampled) signal is then passed through the edge
detector. Figure 37 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the
internal system clock (
clk
). The latch is transparent in the high period of the internal
I/O
system clock.
/clk
The edge detector generates one clk
T1
pulse for each positive (CSn2:0 = 7) or neg-
0
T
ative (CSn2:0 = 6) edge it detects.
Figure 37. T1/T0 Pin Sampling
Tn
LE
clk
I/O
DQDQ
DQ
Edge DetectorSynchronization
Tn_sync
(To Clock
Select Logic)
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system
clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for
at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock
pulse is generated.
92
Each half period of the external clock applied must be longer than one system clock
cycle to ensure correct sampling. The external clock must be guaranteed to have less
than half the system clock frequency (f
ATmega169V/L
ExtClk<fclk_I/O
/2) given a 50/50% duty cycle. Since
2514A–AVR–08/02
ATmega169V/L
the edge detector uses sampling, the maximum frequency of an external clock it can
detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal,
resonator, and capacitors) tolerances, it is recommended that maximum frequency of an
external clock source is less than f
An external clock source can not be prescaled.
clk_I/O
/2.5.
General Timer/Counter
Control Register – GTCCR
Figure 38. Prescaler for Timer/Counter0 and Timer/Counter1
clk
I/O
PSR10
T0
T1
Synchronization
Synchronization
clk
Clear
T1
(1)
clk
T0
Note:1. The synchronization logic on the input pins (T1/T0) is shown in Figure 37.
Bit76543210
TSM
Read/WriteRRRRRRR/WR/W
Initial Value00000000
–––––PSR2PSR10GTCCR
2514A–AVR–08/02
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the
corresponding prescaler reset signals asserted. This ensures that the corresponding
Timer/Counters are halted and can be configured to the same value without the risk of
one of them advancing during configuration. When the TSM bit is written to zero, the
PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting
simultaneously.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This
bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that
Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
93
16-bitTimer/Counter1The 16-bit Timer/Counter unit allows accurate program execution timing (event man-
agement), wave generation, and signal timing measurement. The main features are:
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
OverviewMost register and bit references in this section are written in general form. A lower case
“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the
precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value
and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 39. For the
actual placement of I/O pins, refer to “Pinout ATmega169” on page 2. CPU accessible
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “16-bit Timer/Counter Register Description”
on page 116.
94
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Figure 39. 16-bit Timer/Counter Block Diagram
Count
Clear
Direction
Timer/Counter
TCNTn
Control Logic
TOPBOTTOM
=
=
OCRnA
Fixed
TOP
Values
=
DATA B US
OCRnB
ICFn (Int.Req.)
ICRn
(1)
clk
Tn
=
0
Edge
Detector
TOVn
(Int.Req.)
Clock Select
Edge
Detector
( From Prescaler )
OCnA
(Int.Req.)
Wavefo rm
Generation
OCnB
(Int.Req.)
Wavefo rm
Generation
Noise
Canceler
Tn
OCnA
OCnB
( From Analog
Comparator Ouput )
ICPn
Note:1. Refer to Figure 1 on page 2, Table 28 on page 58, and Table 34 on page 62 for
RegistersThe
Register
accessing the 16-bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 97. The
8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to
Int.Req. in the figure) signals are all visible in the
All interrupts are individually masked with the
TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T1 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR1A/B) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform
Generator to generate a PWM or variable frequency output on the Output Compare pin
(OC1A/B). See “Output Compare Units” on page 103.. The compare match event will
TCCRnATCCRnB
Timer/Counter1 pin placement and description.
Timer/Counter
(TCNT1),
Output Compare Registers
(OCR1A/B), and
Input Capture
(ICR1) are all 16-bit registers. Special procedures must be followed when
Timer/Counter Control Registers
(TCCR1A/B) are
Timer Interrupt Flag Register
Timer Interrupt Mask Register
).
1
T
(TIFR1).
(TIMSK1).
2514A–AVR–08/02
95
also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output
Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external
(edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 188.) The Input Capture unit includes a
digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be
defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.
When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be
used for generating a PWM output. However, the TOP value will in this case be double
buffered allowing the TOP value to be changed in run time. If a fixed TOP value is
required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be
used as PWM output.
DefinitionsThe following definitions are used extensively throughout the section:
Table 54. Definitions
BOTTOMThe counter reaches the
MAXThe counter reaches its
The counter reaches the
TOP
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.
BOTTOM
MAX
TOP
when it becomes 0x0000.
imum when it becomes 0xFFFF (decimal 65535).
when it becomes equal to the highest value in the
CompatibilityThe 16-bit Timer/Counter has been updated and improved from previous versions of the
16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier
version regarding:
•All 16-bit Timer/Counter related I/O Register address locations, including Timer
Interrupt Registers.
•Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt
Registers.
•Interrupt Vectors.
The following control bits have changed name, but have same functionality and register
location:
•PWM10 is changed to WGM10.
•PWM11 is changed to WGM11.
•CTC1 is changed to WGM12.
96
The following bits are added to the 16-bit Timer/Counter Control Registers:
•FOC1A and FOC1B are added to TCCR1A.
•WGM13 is added to TCCR1B.
The 16-bit Timer/Counter has improvements that will affect the compatibility in some
special cases.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
Accessing 16-bit
Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR
CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or
write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the
high byte of the 16-bit access. The same temporary register is shared between all 16-bit
registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write
operation. When the low byte of a 16-bit register is written by the CPU, the high byte
stored in the temporary register, and the low byte written are both copied into the 16-bit
register in the same clock cycle. When the low byte of a 16-bit register is read by the
CPU, the high byte of the 16-bit register is copied into the temporary register in the
same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the
OCR1A/B 16-bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read,
the low byte must be read before the high byte.
The following code examples show how to access the 16-bit timer registers assuming
that no interrupts updates the temporary register. The same principle can be used
directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”,the
compiler handles the 16-bit access.
Assembly Code Examples
...
Set TCNT1to 0x01FF
;
ldi r17,0x01
ldi r16,0xFF
out TCNT
out TCNT
; Read TCNT
in r16,TCNT
in r17,TCNT
...
C Code Examples
unsigned int i;
...
/*
TCNT
/*
i = TCNT
...
1H,r17
1L,r16
1 into r17:r16
1L
1H
(1)
Set TCNT1to 0x01FF
1 = 0x1FF;
Read TCNT1into i
1;
(1)
*/
*/
2514A–AVR–08/02
Note:1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,
and “SBI” instructions must be replaced with instructions that allow access to
extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and
“CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt
code updates the temporary register by accessing the same or any other of the 16-bit
timer registers, then the result of the access outside the interrupt will be corrupted.
97
Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register
contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the
same principle.
Assembly Code Example
TIM16_ReadTCNT1:
Save global interrupt flag
;
in r18,SREG
Disable interrupts
;
cli
; Read TCNT
in r16,TCNT
in r17,TCNT
Restore global interrupt flag
;
out SREG,r18
ret
C Code Example
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
Save global interrupt flag
/*
sreg = SREG;
Disable interrupts
/*
_CLI();
Read TCNT1into i
/*
i = TCNT
Restore global interrupt flag
/*
SREG = sreg;
return i;
}
1 into r17:r16
(1)
1;
(1)
1L
1H
*/
*/
*/
*/
98
Note:1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,
and “SBI” instructions must be replaced with instructions that allow access to
extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and
“CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
ATmega169V/L
2514A–AVR–08/02
ATmega169V/L
The following code examples show how to do an atomic write of the TCNT1 Register
contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the
same principle.
Assembly Code Example
TIM16_WriteTCNT1:
Save global interrupt flag
;
in r18,SREG
Disable interrupts
;
cli
Set TCNT1to
;
out TCNT
out TCNT
;
out SREG,r18
ret
C Code Example
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/*
sreg = SREG;
/*
_CLI();
/*
TCNT
/*
SREG = sreg;
}
1H,r17
1L,r16
Restore global interrupt flag
(1)
Save global interrupt flag
Disable interrupts
Set TCNT1to i
1 =i;
Restore global interrupt flag
(1)
r17:r16
*/
*/
*/
*/
Reusing the Temporary High
Byte Register
2514A–AVR–08/02
Note:1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”,
and “SBI” instructions must be replaced with instructions that allow access to
extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and
“CBR”.
The assembly code example requires that the r17:r16 register pair contains the value to
be written to TCNT1.
If writing to more than one 16-bit register where the high byte is the same for all registers
written, then the high byte only needs to be written once. However, note that the same
rule of atomic operation described previously also applies in this case.
99
Timer/Counter Clock
Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the
(CS12:0) bits located in the
Timer/Counter control Register B
(TCCR1B). For details on
Clock Select
clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on
page 92.
Counter UnitThe main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional
counter unit. Figure 40 shows a block diagram of the counter and its surroundings.
Figure 40. Counter Unit Block Diagram
DATA B US (8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Count
TCNTnH (8-bit)TCNTnL (8-bit)
TCNTn (16-bit Counter)
Clear
Direction
Control Logic
TOPBOTTOM
Signal description (internal signals):
CountIncrement or decrement TCNT1 by 1.
clk
Tn
Clock Select
Edge
Detector
( From Prescaler )
Tn
DirectionSelect between increment and decrement.
ClearClear TCNT1 (set all bits to zero).
clk
1
T
Timer/Counter clock.
TOPSignalize that TCNT1 has reached maximum value.
BOTTOMSignalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations:
(TCNT1H) containing the upper eight bits of the counter, and
Counter Low
Counter High
(TCNT1L)
containing the lower eight bits. The TCNT1H Register can only be indirectly accessed
by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU
accesses the high byte temporary register (TEMP). The temporary register is updated
with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the
temporary register value when TCNT1L is written. This allows the CPU to read or write
the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described
in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each
internal clock source, selected by the
timer clock
(clk
). The clk
1
T
Clock Select
can be generated from an external or
1
T
bits (CS12:0). When no clock source
is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be
accessed by the CPU, independent of whether clk
is present or not. A CPU write over-
1
T
rides (has priority over) all counter clear or count operations.
100
The counting sequence is determined by the setting of the
bits (WGM13:0) located in the
TCCR1B). There are close connections between how the counter behaves (counts) and
ATmega169V/L
Waveform Generation mode
Timer/Counter Control Registers
A and B (TCCR1A and
2514A–AVR–08/02
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