Rainbow Electronics ATmega163L User Manual
Features
• High-performance, Low-power AVR
– 130 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 8 MIPS Throughput at 8 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
• Self-programming In-System Programmable Flash Memory
– 16K Bytes with Optional Boot Block (256 - 2K Bytes)
Endurance: 1,000 Write/Erase Cycles
– Boot Section Allows Reprogramming of Program Code without External
Programmer
– Optional Boot Code Section with Independent Lock Bits
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1024 Bytes Internal SRAM
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Clock with Separate Oscillator and Counter Mode
– Three PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented 2-wire Serial Interface
– Programmable Serial UART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Four Sleep Modes: Idle, ADC Noise Reduction, Power Save, and Power-Down
• Power Consumption at 4 MHz, 3.0V, 25°C
– Active 50 mA
– Idle Mode 1.9 mA
– Power-down Mode < 1 µA
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP and 44-pin TQFP
• Operating Voltages
– 2.7 - 5.5V (ATmega163L)
– 4.0 - 5.5V (ATmega163)
• Speed Grades
– 0 - 4 MHz (ATmega163L)
– 0 - 8 MHz (ATmega163)
®
8-bit Microcontroller
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega163
ATmega163L
Advance
Information
Rev. 1142A–10/00
1
Pin Configurations
(SDA)
(SCL)
(SDA)
(SCL)
2
ATmega163(L)
ATmega163(L)
Description
The ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architecture. By executing powerful instructions in a single clock cycle, the ATmega163 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Figure 1. Block Diagram
PA0 - PA7
VCC
PC0 - PC7
GND
AVCC
AGND
AREF
DATA REGISTER
INTERNAL
REFERENCE
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PORTA DRIVERS
PORTA
ANALOG MUX
REG. PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
DATA DIR.
ADC
8-BIT DATA BUS
PORTC DRIVERS
DATA REGISTER
PORTC
2-WIRE SERIAL
INTERFACE
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
INTERNAL
CALIBRATED
OSCILLATOR
DATA DIR.
REG. PORTC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
XTAL1
XTAL2
RESET
PROGRAMMING
LOGIC
DATA REGISTER
+
-
ANALOG
COMPARATOR
PORTB
PORTB DRIVERS
SPI
PB0 - PB7
DATA DIR.
REG. PORTB
UART
DATA REGISTER
PORTD
PORTD DRIVERS
PD0 - PD7
DATA DIR.
REG. PORTD
3
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The ATmega163 provides the following features: 16K bytes of In-System Self-Programmable Flash, 512 bytes EEPROM,
1024 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, three flexible timer/counters with
compare modes, internal and external interrupts, a byte oriented 2-wire Serial Interface, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, a programmable serial UART, an SPI serial port, and four software
selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the asynchronous timer
oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction Mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching
noise during ADC conversions.
The on-chip ISP Flash can be programmed through an SPI serial interface or a conventional programmer. By installing a
self-programming boot loader, the microcontroller can be updated within the application without any external components.
The boot program can use any interface to download the application program in the Application Flash memory. By combining an 8-bit CPU with In-System self-programmable Flash on a monolithic chip, the Atmel ATmega163 is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega163 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC
Digital supply voltage
GND
Digital ground
Port A (PA7..PA0)
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up
resistors (selected for each bit). The Port A output buffers can sink 20mA and can drive LED displays directly. When pins
PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers can
sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port
B also serves the functions of various special features of the ATmega83/163 as listed on page 100. The Port B pins are
tristated when a reset condition becomes active, even if the clock is not running.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers can
sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The
Port C pins are tristated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of various special features of the ATmega163 as listed on page 107.
4
ATmega163(L)
ATmega163(L)
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers can
sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port
D also serves the functions of various special features of the ATmega163 as listed on page 110. The Port D pins are
tristated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. A low level on this pin for more than 500 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
AVCC
This is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC
is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. See page 90 for details on operation of the ADC.
AREF
This is the analog reference input pin for the A/D Converter. For ADC operations, a voltage in the range 2.5V to AV
be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND.
CC
can
Clock Options
The device has the following clock source options, selectable by Flash fuse bits as shown:
Table 1. Device Clocking Options Select
Device Clocking Option CKSEL3..0
External Crystal/Ceramic Resonator 1111 - 1010
External Low-frequency Crystal 1001 - 1000
External RC Oscillator 0111 - 0101
Internal RC Oscillator 0100 - 0010
External Clock 0001 - 0000
Note: “1” means unprogrammed, “0” means programmed.
The various choices for each clocking option give different start-up times as shown in Table 5 on page 22.
Internal RC Oscillator
The internal RC oscillator option is an on-chip oscillator running at a fixed frequency of nominally 1 MHz. If selected, the
device can operate with no external components. The device is shipped with this option selected. See “EEPROM
Read/Write Access” on page 53 for information on calibrating this oscillator.
5
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used.
Figure 2. Oscillator Connections
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 3.
Figure 3. External Clock Drive Configuration
External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 4 can be used. For details on how to
choose R and C, see Table 63 on page 140.
Figure 4. External RC Configuration
CC
V
R
C
NC
XTAL2
XTAL1
GND
Timer Oscillator
For the Timer Oscillator pins, PC6(TOSC1) and PC7(TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The oscillator is optimized for use with a 32,768 Hz watch crystal. Applying an external clock
source to the PC6 (TOSC1) pin is not recommended.
6
ATmega163(L)
ATmega163(L)
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for look-up tables in
Flash program memory. These added function registers are the 16-bits X-register, Y-register, and Z-register.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 5 shows the ATmega163 AVR Enhanced RISC microcontroller
architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowest Data Space addresses ($00 - $1F), allowing them
to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/Dconverters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following
those of the register file, $20 - $5F.
Figure 5. The ATmega163 AVR RISC Architecture
8K X 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
AVR ATmega163 Architecture
Data Bus 8-bit
Program
Counter
Direct Addressing
Indirect Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
1024 x 8
Data
SRAM
512 x 8
EEPROM
Interrupt
Unit
SPI
Unit
Serial
UART
2-Wire Serial
Interface
8-bit
Timer/Counter
16-bit
Timer/Counter
with PWM
8-bit
Timer/Counter
with PWM
Watchdog
Timer
A/D Converter
32
I/O Lines
Analog
Comparator
7
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is
in-system re-programmable Flash memory.
With the jump and call instructions, the whole 8K word address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section (256 to 2048 bytes, see page 115) and
the Application Program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section is allowed only in the Boot program section.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 11-bit stack pointer SP is read/write accessible in the I/O space.
The 1024 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the
higher the priority.
Figure 6. Memory Maps
Program Memory
Application Flash Section
Boot Flash Section
$0000
$1FFF
8
ATmega163(L)
ATmega163(L)
The General Purpose Register File
Figure 7 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7. AVR CPU General Purpose Working Registers
70Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a
register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND, and OR and all other operations between two
registers or on a single register apply to the entire register file.
As shown in Figure 7, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X, Y, and Z registers can be set to index any register in the file.
The X-register, Y-register, And Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers
for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as:
Figure 8. The X, Y, and Z Registers
15 XH XL 0
X - register 70 0 7 0
R27 ($1B) R26 ($1A)
15 YH YL 0
Y - register 70 0 7 0
R29 ($1D) R28 ($1C)
15 ZH ZL 0
Z - register 70 0 7 0
R30 ($1F) R31 ($1E)
9
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and
decrement (see the descriptions for the different instructions).
The ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into
three main categories - arithmetic, logical, and bit-functions.
ATmega163 also provides a powerful multiplier supporting
both signed/unsigned multiplication and fractional format. See the Instruction Set section for a detailed description.
The In-System Self-programmable Flash Program Memory
The ATmega163 contains 16K bytes on-chip In-System Self-Programmable Flash memory for program storage. Since all
instructions are 16- or 32-bit words, the Flash is organized as 8K x 16. The Flash Program memory space is divided in two
sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 1000 write/erase cycles. The ATmega163 Program Counter (PC) is 13 bits
wide, thus addressing the 8192 program memory locations. The operation of Boot Program section and associated Boot
Lock Bits for software protection are described in detail on page 115. See also page 132 for a detailed description on Flash
data serial downloading.
Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory
instruction description).
See also page 11 for the different program memory addressing modes.
The SRAM Data Memory
Figure 9 shows how the ATmega163 SRAM Memory is organized.
Figure 9. SRAM Organization
Register File
R0
R1
R2
...
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
Data Address Space
$0000
$0001
$0002
...
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$045E
$045F
10
ATmega163(L)
ATmega163(L)
The lower 1120 Data Memory locations address the Register file, the I/O Memory, and the internal data SRAM. The first 96
locations address the Register File + I/O Memory, and the next 1024 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with
Pre-Decrement, and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O registers, and the 1024 bytes of internal data SRAM in the ATmega163
are all accessible through all these addressing modes.
The Program and Data Addressing Modes
The ATmega163 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the
program memory (Flash) and data memory (SRAM, Register File, and I/O Memory). This section describes the different
addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction
word. To simplify, not all figures show the exact location of the addressing bits.
Register Direct, Single Register Rd
Figure 10. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd And Rr
Figure 11. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
11
I/O Direct
Figure 12. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Data Direct
Figure 13. Direct Data Addressing
16 LSBs
20 19
16
31
OP Rr/Rd
15 0
Data Space
$0000
$045F
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register.
Data Indirect With Displacement
Figure 14. Data Indirect with Displacement
15
Y OR Z - REGISTER
15
OP an
Data Space
0
05610
$0000
$045F
Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction
word.
12
ATmega163(L)
Data Indirect
Figure 15. Data Indirect Addressing
ATmega163(L)
015
X, Y OR Z - REGISTER
Operand address is the contents of the X, Y, or the Z-register.
Data Indirect With Pre-decrement
Figure 16. Data Indirect Addressing With Pre-decrement
015
X, Y OR Z - REGISTER
-1
Data Space
Data Space
$0000
$045F
$0000
$045F
The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y
or the Z-register.
Data Indirect With Post-increment
Figure 17. Data Indirect Addressing With Post-increment
Data Space
015
X, Y OR Z - REGISTER
1
$0000
$045F
The X, Y, or the Z-register is incremented after the operation. Operand address is the content of the X, Y, or the Z-register
prior to incrementing.
13
Constant Addressing Using The LPM and SPM Instructions
Figure 18. Code Memory Constant Addressing
$1FFF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 8K). For LPM, the
LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared.
Indirect Program Addressing, IJMP and ICALL
Figure 19. Indirect Program Memory Addressing
$1FFF
Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Zregister).
Relative Program Addressing, RJMP and RCALL
Figure 20. Relative Program Memory Addressing
1
$1FFF
Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.
14
ATmega163(L)
ATmega163(L)
The EEPROM Data Memory
The ATmega163 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single
bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described on page 53 specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For the SPI data downloading, see page 132 for a detailed description.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the main oscillator for the chip. No internal clock
division is used.
Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 21. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 22 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 22. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described in Figure 23.
15
Figure 23. On-chip Data SRAM Access Cycles
T1 T2 T3 T4
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address
Address
I/O Memory
The I/O space definition of the ATmega163 is shown in the following table:
Table 2. ATmega163 I/O Space
I/O Address (SRAM Address) Name Function
$3F ($5F) SREG Status REGister
$3E ($5E) SPH Stack Pointer High
$3D ($5D) SPL Stack Pointer Low
$3B ($5B) GIMSK General Interrupt MaSK Register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt MaSK Register
Write
Read
$38 ($58) TIFR Timer/Counter Interrupt Flag Register
$37 ($57) SPMCR SPM Control Register
$36 ($56) TWCR 2-wire Serial Interface Control Register
$35 ($55) MCUCR MCU general Control Register
$34 ($54) MCUSR MCU general Status Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$31 ($51) OSCCAL Oscillator Calibration Register
$30 ($50) SFIOR Special Function I/O Register
$2F ($4F) TCCR1A Timer/Counter1 Control Register A
$2E ($4E) TCCR1B Timer/Counter1 Control Register B
$2D ($4D) TCNT1H Timer/Counter1 High-byte
$2C ($4C) TCNT1L Timer/Counter1 Low-byte
$2B ($4B) OCR1AH Timer/Counter1 Output Compare Register A High-byte
$2A ($4A) OCR1AL Timer/Counter1 Output Compare Register A Low-byte
$29 ($49) OCR1BH Timer/Counter1 Output Compare Register B High-byte
16
ATmega163(L)
Table 2. ATmega163 I/O Space (Continued)
I/O Address (SRAM Address) Name Function
$28 ($48) OCR1BL Timer/Counter1 Output Compare Register B Low-byte
$27 ($47) ICR1H T/C 1 Input Capture Register High-byte
$26 ($46) ICR1L T/C 1 Input Capture Register Low-byte
$25 ($45) TCCR2 Timer/Counter2 Control Register
$24 ($44) TCNT2 Timer/Counter2 (8-bit)
$23 ($43) OCR2 Timer/Counter2 Output Compare Register
$22 ($42) ASSR Asynchronous Mode Status Register
$21 ($41) WDTCR Watchdog Timer Control Register
$20 ($40) UBRRHI UART Baud Rate Register High-byte
$1F ($3F) EEARH EEPROM Address Register High-byte
$1E ($3E) EEARL EEPROM Address Register Low-byte
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$1B ($3B) PORTA Data Register, Port A
ATmega163(L)
$1A ($3A) DDRA Data Direction Register, Port A
$19 ($39) PINA Input Pins, Port A
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
$15 ($35) PORTC Data Register, Port C
$14 ($34) DDRC Data Direction Register, Port C
$13 ($33) PINC Input Pins, Port C
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0F ($2F) SPDR SPI I/O Data Register
$0E ($2E) SPSR SPI Status Register
$0D ($2D) SPCR SPI Control Register
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) UCSRA UART Control and Status Register A
$0A ($2A) UCSRB UART Control and Status Register B
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR Analog Comparator Control and Status Register
$07 ($27) ADMUX ADC Multiplexer Select Register
$06 ($26) ADCSR ADC Control and Status Register
$05 ($25) ADCH ADC Data Register High
17
Table 2. ATmega163 I/O Space (Continued)
I/O Address (SRAM Address) Name Function
$04 ($24) ADCL ADC Data Register Low
$03 ($23) TWDR 2-wire Serial Interface Data Register
$02 ($22) TWAR 2-wire Serial Interface (Slave) Address Register
$01 ($21) TWSR 2-wire Serial Interface Status Register
$00 ($20) TWBR 2-wire Serial Interface Bit Rate Register
Note: Reserved and unused locations are not shown in the table.
All ATmega163 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT
instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the
address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details.
When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to these addresses. All I/O register addresses throughout this document are shown
with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
The I/O and peripherals control registers are explained in the following sections.
The Status Register - SREG
The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 - I: Global Interrupt Enable
•
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is
then performed in the interrupt mask registers. If the global interrupt enable register is cleared (zero), none of the interrupts
are enabled independent of the values of the interrupt mask registers. The I-bit is cleared by hardware after an interrupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts.
Bit 6 - T: Bit Copy Storage
•
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A
bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
Bit 5 - H: Half Carry Flag
•
The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed
information.
Bit 4 - S: Sign Bit, S = N=⊕ V
•
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set Description for detailed information.
•
Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
18
ATmega163(L)
ATmega163(L)
Bit 2 - N: Negative Flag
•
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for
detailed information.
•
Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Bit 0 - C: Carry Flag
•
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
The Stack Pointer - SP
The ATmega163 Stack Pointer is implemented as two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D).
As the ATmega163 data memory has $460 locations, 11 bits are used.
Bit 151413121110 9 8
$3E ($5E) - - - - - SP10 SP9 SP8 SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R R R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
00000000
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are
enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed
onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack
with subroutine call and interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
Reset and Interrupt Handling
The ATmega163 provides 17 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set
(one) together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The
complete list of vectors is shown in Table 3. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request
0, etc.
19
Table 3. Reset and Interrupt Vectors
Vector No. Program Source Interrupt Definition
Address
1$000
2 $002 INT0 External Interrupt Request 0
3 $004 INT1 External Interrupt Request 1
4 $006 TIMER2 COMP Timer/Counter2 Compare Match
5 $008 TIMER2 OVF Timer/Counter2 Overflow
6 $00A TIMER1 CAPT Timer/Counter1 Capture Event
7 $00C TIMER1 COMPA Timer/Counter1 Compare Match A
8 $00E TIMER1 COMPB Timer/Counter1 Compare Match B
9 $010 TIMER1 OVF Timer/Counter1 Overflow
10 $012 TIMER0 OVF Timer/Counter0 Overflow
11 $014 SPI, STC Serial Transfer Complete
12 $016 UART, RXC UART, Rx Complete
13 $018 UART, UDRE UART Data Register Empty
14 $01A UART, TXC UART, Tx Complete
15 $01C ADC ADC Conversion Complete
(1)
RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
16 $01E EE_RDY EEPROM Ready
17 $020 ANA_COMP Analog Comparator
18 $022 TWSI 2-wire Serial Interface
Note: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Sup-
port” on page 115.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega163 is:
Address Labels Code Comments
$000 jmp RESET ; Reset Handler
$002 jmp EXT_INT0 ; IRQ0 Handler
$004 jmp EXT_INT1 ; IRQ1 Handler
$006 jmp TIM2_COMP ; Timer2 Compare Handler
$008 jmp TIM2_OVF ; Timer2 Overflow Handler
$00a jmp TIM1_CAPT ; Timer1 Capture Handler
$00c jmp TIM1_COMPA ; Timer1 CompareA Handler
$00e jmp TIM1_COMPB ; Timer1 CompareB Handler
$010 jmp TIM1_OVF ; Timer1 Overflow Handler
$012 jmp TIM0_OVF ; Timer0 Overflow Handler
$014 jmp SPI_STC ; SPI Transfer Complete Handler
$016 jmp UART_RXC ; UART RX Complete Handler
$018 jmp UART_DRE ; UDR Empty Handler
$01a jmp UART_TXC ; UART TX Complete Handler
$01c jmp ADC ; ADC Conversion Complete Interrupt Handler
$01e jmp EE_RDY ; EEPROM Ready Handler
$020 jmp ANA_COMP ; Analog Comparator Handler
$022 jmp TWSI ; 2-wire Serial Interface Interrupt Handler
20
ATmega163(L)
ATmega163(L)
;
$024 MAIN: ldi r16,high(RAMEND); Main program start
$025 out SPH,r16 ; Set stack pointer to top of RAM
$026 ldi r16,low(RAMEND)
$027 out SPL,r16
... ... ...
When the BOOTRST fuse is programmed and the boot section size set to 512 bytes, the most typical and general program
setup for the Reset and Interrupt Vector Addresses in ATmega163 is:
Address Labels Code Comments
$002 jmp EXT_INT0 ; IRQ0 Handler
... ... ...
$022 jmp TWSI ; 2-wire Serial Interface Interrupt Handler
;
$024 MAIN: ldi r16,high(RAMEND); Main program start
$025 out SPH,r16 ; Set stack pointer to top of RAM
$026 ldi r16,low(RAMEND)
$027 out SPL,r16
$028 <instr> xxx
;
.org $1f00
$1f00 jmp RESET ; Reset Handler
Reset Sources
The ATmega163 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET pin for more than 500 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage V
is below the brown-out reset threshold (V
CC
BOT
).
During reset, all I/O registers are set to their initial values, and the program starts execution from address $000 (unless the
BOOTRST fuse is programmed, as explained above). The instruction placed in this address location must be a JMP absolute jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the
reset logic. Table 4 and Table 5 define the timing and electrical parameters of the reset circuitry.
21
Figure 24. Reset Logic
DATA BU S
MCU Status
Register (MCUSR)
BORF
PORF
WDRF
EXTRF
BODEN
BODLEVEL
100-500kΩ
SPIKE
FILTER
Table 4. Reset Characteristics (VCC = 5.0V)
Brown-Out
Reset Circuit
Clock
Generator
CKSEL[3:0]
(1)
CK
Delay Counters
TIMEOUT
Symbol Parameter Condition Min Typ Max Units
V
POT
V
RST
Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V
Power-on Reset Threshold Voltage (falling)
RESET Pin Threshold Voltage - - 0.85 V
(2)
0.4 0.6 0.8 V
CC
Brown-out Reset Threshold Voltage (BODLEVEL = 1) 2.5 2.7 2.9
V
BOT
(BODLEVEL = 0) 3.6 4.0 4.4
Notes: 1. Values are guidelines only. Actual values are TBD.
2. The Power-on Reset will not work unless the supply voltage has been below V
Table 5. Reset Delay Selections
(1)
POT
(falling).
V
V
CKSEL
(2)
Start-up Time, VCC = 2.7V,
BODLEVEL Unprogrammed
Start-up Time, VCC = 4.0V,
BODLEVEL Programmed Recommended Usage
(3)
0000 4.2 ms + 6 CK 5.8 ms + 6 CK Ext. Clock, fast rising power
0001 30 µs + 6 CK
(6)
0010
67 ms + 6 CK 92 ms + 6 CK Int. RC Oscillator, slowly rising power
(4)
10 µs + 6 CK
(5)
Ext. Clock, BOD enabled
0011 4.2 ms + 6 CK 5.8 ms + 6 CK Int. RC Oscillator, fast rising power
0100 30 µs + 6 CK
(4)
10 µs + 6 CK
(5)
Int. RC Oscillator, BOD enabled
0101 67 ms + 6 CK 92 ms + 6 CK Ext. RC Oscillator, slowly rising power
0110 4.2 ms + 6 CK 5.8 ms + 6 CK Ext. RC Oscillator, fast rising power
22
ATmega163(L)
ATmega163(L)
Table 5. Reset Delay Selections
CKSEL
(2)
0111 30 µs + 6 CK
Start-up Time, VCC = 2.7V,
BODLEVEL Unprogrammed
(1)
(Continued)
(4)
Start-up Time, VCC = 4.0V,
BODLEVEL Programmed Recommended Usage
10 µs + 6 CK
(5)
Ext. RC Oscillator, BOD enabled
(3)
1000 67ms + 32K CK 92 ms + 32K CK Ext. Low-frequency Crystal
1001 67 ms + 1K CK 92 ms + 1K CK Ext. Low-frequency Crystal
1010 67 ms + 16K CK 92 ms + 16K CK Crystal Oscillator, slowly rising power
1011 4.2 ms + 16K CK 5.8 ms + 16K CK Crystal Oscillator, fast rising power
1100 30 µs + 16K CK
(4)
10 µs + 16K CK
(5)
Crystal Oscillator, BOD enabled
1101 67 ms + 1K CK 92 ms + 1K CK Ceramic Resonator/Ext. Clock, slowly rising power
1110 4.2 ms + 1K CK 5.8 ms + 1K CK Ceramic Resonator, fast rising power
1111 30 µs + 1K CK
(4)
10 µs + 1K CK
(5)
Ceramic Resonator, BOD enabled
Notes: 1. On power-up, the start-up time is increased with typ. 0.6 ms.
2. ‘1’ means unprogrammed, ‘0’ means programmed.
3. For possible clock selections, see “Clock Options” on page 5.
4. When BODEN is programmed, add 100 µs.
5. When BODEN is programmed, add 25 µs.
6. Default value.
Table 5 shows the start-up times from reset. When the CPU wakes up from power down or power save, only the clock
counting part of the start-up time is used. The watchdog oscillator is used for timing the real-time part of the start-up time.
The number of WDT oscillator cycles used for each time-out is shown in Table 6.
The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The
device is shipped with CKSEL = ‘0010’ (Int. RC Oscillator, slowly rising power).
Table 6. Number of Watchdog Oscillator Cycles
BODLEVEL Vcc condition Time-out Number of cycles
Unprogrammed 2.7V 30 µs 8
Unprogrammed 2.7V 130 µs 32
Unprogrammed 2.7V 4.2 ms 1K
Unprogrammed 2.7V 67 ms 16K
Programmed 4.0V 10 µs 8
Programmed 4.0V 35 µs 32
Programmed 4.0V 5.8 ms 4K
Programmed 4.0V 92 ms 64K
Note: The bod-level fuse can be used to select start-up times even if the Brown-out detection is disabled (BODEN fuse
unprogrammed).
Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in Table 4. The
POR is activated whenever V
is below the detection level. The POR circuit can be used to trigger the start-up reset, as
CC
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. Reaching the power-on reset threshold
voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after V
rise. The
CC
time-out period of the delay counter can be defined by the user through the CKSEL fuses. The different selections for the
delay period are presented in Table 5. The RESET signal is activated again, without any delay, when the V
decreases
CC
below detection level.
23
Figure 25. MCU Start-up, RESET
VCC
RESET
TIME-OUT
INTERNAL
RESET
Tied to VCC.
V
POT
V
RST
t
TOUT
Figure 26. MCU Start-up, RESET
VCC
RESET
TIME-OUT
INTERNAL
RESET
Extended Externally
V
POT
V
RST
t
TOUT
External Reset
An external reset is generated by a low level on the RESET
pin. Reset pulses longer than 500 ns will generate a reset,
even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage - V
on its positive edge, the delay timer starts the MCU after the Time-out period t
RST
TOUT
has
expired.
Figure 27. External Reset During Operation
24
ATmega163(L)
ATmega163(L)
Brown-out Detection
ATmega163 has an on-chip brown-out detection (BOD) circuit for monitoring the V
circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and V
to a value below the trigger level, the brown-out reset is immediately activated. When V
the brown-out reset is deactivated after a delay. The delay is defined by the user in the same way as the delay of POR signal, in Table 5. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL
unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis of 50 mV to ensure spike free
brown-out detection.
The BOD circuit will only detect a drop in V
if the voltage stays below the trigger level for longer than 9 µs for trigger level
CC
4.0V, 21 µs for trigger level 2.7V (typical values).
Figure 28. Brown-out Reset During Operation
level during the operation. The BOD
CC
increases above the trigger level,
CC
decreases
CC
V
BOT+
t
TOUT
The hysteresis on V
BOT
: V
TIME-OUT
INTERNAL
BOT+
VCC
RESET
RESET
= V
+ 25 mV, V
BOT
BOT-
V
BOT-
= V
BOT
- 25 mV
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this
pulse, the delay timer starts counting the Time-out period t
. Refer to page 51 for details on operation of the Watchdog
TOUT
Timer.
Figure 29. Watchdog Reset During Operation
1 CK Cycle
25
MCU Status Register - MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit 76543210
$34 ($54) - - - - WDRF BORF EXTRF PORF MCUSR
Read/Write R R R R R/W R/W R/W R/W
Initial value 0 0 0 0 See bit description
Bits 7..4 - Res: Reserved Bits
•
These bits are reserved bits in the ATmega163 and always read as zero.
•
Bit 3 - WDRF: Watchdog Reset Flag
This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
Bit 2 - BORF: Brown-out Reset Flag
•
This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
•
Bit 1 - EXTRF: External Reset Flag
• This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.
Bit 0 - PORF: Power-on Reset Flag
•
This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as
possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by
examining the reset flags.
Internal Voltage Reference
ATmega163 features an internal bandgap reference with a nominal voltage of 1.22 V. This reference is used for Brown-Out
Detection, and it can be used as an input to the Analog Comparator and ADC. The 2.56 V reference to the ADC is also generated from the internal bandgap reference.
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The maximum start-up time is TBD.
To save power, the reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODEN fuse)
2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the reference to start up before
the output from the Analog Comparator is used. The bandgap reference uses typically 10 µA, and to reduce power consumption in Power Down mode, the user can avoid the three conditions above to ensure that the reference is turned off
before entering Power Down mode.
Interrupt Handling
The ATmega163 has two 8-bit Interrupt Mask control registers: GIMSK - General Interrupt Mask register and TIMSK Timer/Counter Interrupt Mask register.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software must set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction RETI - is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set
and remembered until the interrupt is enabled, or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt
flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
26
ATmega163(L)
ATmega163(L)
Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is
present.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. After 4 clock cycles the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program
Counter (13 bits) is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes 3
clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the
interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by 4 clock cycles.
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes)
is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When AVR exits from
an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is
served.
The General Interrupt Mask Register - GIMSK
Bit 7 6 5 4 3 2 1 0
$3B ($5B) INT1 INT0 - - - - - - GIMSK
Read/Write R/W R/W R R R R R R
Initial value 0 0 x 0 0 0 0 0
Bit 7 - INT1: External Interrupt Request 1 Enable
•
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.
The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether
the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause
an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is
executed from program memory address $004. See also “External Interrupts”.
Bit 6 - INT0: External Interrupt Request 0 Enable
•
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated.
The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether
the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from program memory address $002. See also “External Interrupts.”
Bits 5 - Res: Reserved Bits
•
This bit is reserved in the ATmega163 and the read value is undefined.
Bits 4..0 - Res: Reserved Bits
•
These bits are reserved bits in the ATmega163 and always read as zero.
The General Interrupt Flag Register - GIFR
Bit 7 6 5 4 3 2 1 0
$3A ($5A) INTF1 INTF0 - - - - - - GIFR
Read/Write R/W R/W R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 - INTF1: External Interrupt Flag1
•
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $004. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when
INT1 is configured as a level interrupt.
27
Bit 6 - INTF0: External Interrupt Flag0
•
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when
INT0 is configured as a level interrupt.
Bits 5..0 - Res: Reserved Bits
•
These bits are reserved bits in the ATmega163 and always read as zero.
The Timer/Counter Interrupt Mask Register - TIMSK
Bit 7 6 5 4 3 2 1 0
$39 ($59) OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 - TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
•
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e.
when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
•
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is
enabled. The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter2 occurs, i.e. when the
TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 5 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
•
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event
Interrupt is enabled. The corresponding interrupt (at vector $00A) is executed if a capture triggering event occurs on PD6
(ICP), i.e. when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 4 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
•
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match
interrupt is enabled. The corresponding interrupt (at vector $00C) is executed if a CompareA match in Timer/Counter1
occurs, i.e. when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
•
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match
interrupt is enabled. The corresponding interrupt (at vector $00E) is executed if a CompareB match in Timer/Counter1
occurs, i.e. when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
•
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $010) is executed if an overflow in Timer/Counter1 occurs, i.e. when the
TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 1 - Res: Reserved Bit
•
This bit is a reserved bit in the ATmega163 and always reads as zero.
Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
•
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $012) is executed if an overflow in Timer/Counter0 occurs, i.e. when the
TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
28
ATmega163(L)
ATmega163(L)
The Timer/Counter Interrupt Flag Register - TIFR
Bit 7 6 5 4 3 2 1 0
$38 ($58) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 - TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial value 0 0 0 0 0 0 x 0
Bit 7 - OCF2: Output Compare Flag 2
•
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output
Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare
match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
Bit 6 - TOV2: Timer/Counter2 Overflow Flag
•
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG Ibit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt
is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.
Bit 5 - ICF1: Input Capture Flag 1
•
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the
input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logic one to the flag.
Bit 4 - OCF1A: Output Compare Flag 1A
•
The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1 and the data in OCR1A - Output
Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare
match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1A Compare match Interrupt is executed.
Bit 3 - OCF1B: Output Compare Flag 1B
•
The OCF1B bit is set (one) when a compare match occurs between the Timer/Counter1 and the data in OCR1B - Output
Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare
match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1B Compare match Interrupt is executed.
Bit 2 - TOV1: Timer/Counter1 Overflow Flag
•
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in
SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow
Interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
Bit 1 - Res: Reserved Bit
•
This bit is a reserved bit in the ATmega163 and the read value is undefined.
•
Bit 0 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG Ibit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt
is executed.
External Interrupts
The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the interrupts will trigger even if
the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external
interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the
MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt
will trigger as long as the pin is held low.
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MCU Control Register - MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit 76543210
$35 ($55) - SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000
Bit 7 - Res: Reserved Bit
•
This bit is a reserved bit in the ATmega163 and always reads as zero.
•
Bit 6 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just
before the execution of the SLEEP instruction.
Bits 5,4 - SM1/SM0: Sleep Mode Select bits 1 and 0
•
These bits select between the three available sleep modes as shown in Table 7.
Table 7. Sleep Mode Select
SM1 SM0 Sleep Mode
00Idle
0 1 ADC Noise Reduction
1 0 Power-down
11Power Save
•
Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 8. The value on
the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
Table 8. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any logical change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.
Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
•
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are
set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9. The value on the INT0
pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period
will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the
low level must be held until the completion of the currently executing instruction to generate an interrupt.
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ATmega163(L)
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