Rainbow Electronics ATmega161L User Manual

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32x8GeneralPurposeWorkingRegisters – Fully Static Operation – Up to 8 MIPS Throughput at 8 MHz – On-chip 2-cycle Multiplier

• Program and Data Memories

– 16K Bytes of Non-volatile In-System Programmable Flash Endurance: 1,000

Write/Erase Cycles

– Optional Boot Code Memory with Independent Lock bits Self-programming of

Program and Data Memories

– 512 Bytes of Non-volatile In-System Programmable EEPROM Endurance: 100,000

Write/Erase Cycles – 1K Byte of Internal SRAM – Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and PWM – Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,

Capture Modes and Dual 8-, 9-, or 10-bit PWM – Dual Programmable Serial UARTs – Master/Slave SPI Serial Interface – Real-time Counter with Separate Oscillator – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset – External and Internal Interrupt Sources – Three Sleep Modes: Idle, Power-save and Power-down

• Power Comsumption at 4 MHz, 3.0V, 25°C

–Active3.0mA – Idle Mode 1.2 mA – Power-down Mode < 1 µA

• I/O and Packages

– 35 Programmable I/O Lines – 40-lead PDIP and 44-lead TQFP

• Operating Voltages

– 2.7V - 5.5V for the ATmega161L – 4.0V - 5.5V for the ATmega161

• Speed Grades

– 0 - 4 MHz for the ATmega161L – 0 - 8 MHz for the ATmega161

• Commercial and Industrial Temperature Ranges

8-bit Microcontroller

8-bit Microcontroller with 16K Bytes of In-System Programmable Flash

ATmega161 ATmega161L

Disclaimer

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

Rev. 1228C–AVR–08/02

Pin Configuration

PDIP

(OC0/T0) PB0 (OC2/T1) PB1

(RXD1/AIN0) PB2

(TXD1/AIN1) PB3

(SS) PB4 (MOSI) PB5 (MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

(TXD0) PD1

(INT0) PD2 (INT1) PD3

(TOSC1) PD4

(OC1A/TOSC2) PD5

(WR) PD6

(RD) PD7

XTAL2 XTAL1

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

(MOSI) PB5 (MISO) PB6

(SCK) PB7

RESET

(RXD0) PD0

NC*

(TXD0) PD1

(INT0) PD2 (INT1) PD3

(TOSC1) PD4

(OCIA/TOSC2) PD5

TQFP

PB4 (SS)

PB3 (TXD1/AIN1)

PB2 (RXD1/AIN0)

PB1 (OC2/T1)

PB0 (OC0/T0)

NC*

4443424140393837363534

1 2 3 4 5 6 7 8 9 10 11

1213141516171819202122

NC*

GND

XTAL2

XTAL1

(RD) PD7

(WR) PD6

VCC

PA0 (AD0)

PA1 (AD1)

(A8) PC0

(A9) PC1

(A10) PC2

PA2 (AD2)

PA3 (AD3)

33 32 31 30 29 28 27 26 25 24 23

(A11) PC3

(A12) PC4

PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) NC* PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13)

* NC = Do not connect (Can be used in future devices)

ATmega161(L)

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ATmega161(L)

Description The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega161 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code-efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega161 provides the following features: 16K bytes of In-System or Selfprogrammable Flash, 512 bytes EEPROM, 1K byte of SRAM, 35 general purpose I/O lines, 32 general purpose working registers, Real-time Counter, three flexible Timer/Counters with Compare modes, internal and external interrupts, two programmable serial UARTs, programmable Watchdog Timer with internal Oscillator, an SPI serial port and three software-selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register and SRAM contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the timer Oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip Flash Program memory can be reprogrammed using the Self-programming capability through the Boot Block and an ISP through the SPI port, or by using a conventional non-volatile Memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel ATmega161 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications.

The ATmega161 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators and evaluation kits.

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Block Diagram Figure 1. The ATmega161 Block Diagram

PA0-PA7

VCC

PC0-PC7

GND

PORTA DRIVERS

DATA REGISTER

PORTA

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA DIR.

REG. PORTA

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

ALU

STATUS

X Y Z

DATA REGISTER

8-BIT DATA BUS

PORTC DRIVERS

PORTC

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

DATA DIR.

REG. PORTC

OSCILLATOR

TIMING AND

CONTROL

XTAL1

XTAL2

RESET

PROGRAMMING

TOR

ARA

ANALOG

COMP

LOGIC

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

PORTB DRIVERS

PB0 - PB7

SPI

DATA REGISTER

PORTD

PORTD DRIVERS

UARTS

REG. PORTD

PD0 - PD7

DATA DIR.

DATA REG.

PORTE

PORTE DRIVERS

PE0 - PE2

DATA DIR

REG. PORTE

ATmega161(L)

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ATmega161(L)

Pin Descriptions

VCC Supply voltage.

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors

(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port A serves as a Multiplexed Address/Data port when using external memory interface.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output

buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega161 as listed on page 92.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output

buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves as an address high output when using external memory interface.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output

buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega161 as listed on page 101.

Port E (PE2..PE0) Port E is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port E output

buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega161 as listed on page 107.

RESET

Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can

be configured for use as an on-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

Figure 2. Oscillator Connections

Figure 3. External Clock Drive Configuration

EXTERNAL

OSCILLATOR

SIGNAL

XTAL2

XTAL1

GND

XTAL2

XTAL1

GND

ATmega161(L)

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ATmega161(L)

Architectural Overview

The fast-access Register File concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the Register File, the operation is executed and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the ATmega161 AVR RISC microcontroller architecture.

Figure 4. The ATmega161 AVR RISC Architecture

Data Bus 8-bit

8K x 16

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Status

and Control

32 x 8

General

Purpose

Registers

ALU

Indirect Addressing

1024 x 8

Data

SRAM

Interrupt

Unit

SPI

Unit

Serial UART0

Serial UART1

8-bit

Timer/Counter

with PWM

and RTC

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

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512 x 8

EEPROM

I/O Lines

Watchdog

Timer

Analog

Comparator

In addition to the register operation, the conventional Memory Addressing modes can be used on the Register File. This is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters, and other I/O functions. The I/O memory can be accessed directly or as the Data Space locations following those of the Register File, $20 - $5F.

The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The Program memory is executed with a two-stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is Self-programmable Flash memory.

With the jump and call instructions, the whole 8K word address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM and, consequently, the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP (Stack Pointer) in the reset routine (before subroutines or interrupts are executed). The 16-bit Stack Pointer is read/write accessible in the I/O space.

The 1K byte data SRAM can be easily accessed through the five different Addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

ATmega161(L)

1228C–AVR–08/02

Figure 5. Memory Maps

ATmega161(L)

Program Memory

Program Flash

(8K x 16)

$000

Data Memory

32 Gen. Purpose

Working Registers

64 I/O Registers

Internal SRAM

(1024 x 8)

External SRAM

(0 - 63K x 8)

$0000

$001F $0020

$005F $0060

$045F $0460

$1FFF

$FFFF

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All the different interrupts have a separate Interrupt Vector in the Interrupt Vector table at the beginning of the Program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

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The General Purpose Register File

Figure 6 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6. AVR CPU General Purpose Working Registers

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register Low Byte

R27 $1B X-register High Byte

R28 $1C Y-register Low Byte

R29 $1D Y-register High Byte

R30 $1E Z-register Low Byte

R31 $1F Z-register High Byte

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register, and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File – R16..R31. The general SBC, SUB, CP, AND, and OR, and all other operations between two registers or on a single register apply to the entire Register File.

The X-register, Y-register and Z-register

As shown in Figure 6, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file.

The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as:

Figure 7. X-, Y-, and Z-registers

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

ATmega161(L)

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ATmega161(L)

In the different Addressing modes, these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).

ALU – Arithmetic Logic Unit

Self-programmable Flash Program Memory

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the Register File are executed. The ALU operations are divided into three main categories – arithmetic, logical and bit functions. ATmega161 also provides a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the Instruction Set section for a detailed description.

The ATmega161 contains 16K bytes of On-chip Self-programmable and In-System Programmable Flash memory for program storage. Since all instructions are 16- or 32-bit words, the Flash is organized as 8K x 16. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATmega161 Program Counter (PC) is 13 bits wide, thus addressing the 8,192 Program memory locations.

See page 110 for a detailed description of Flash data downloading.

See page 13 for the different Program Memory Addressing modes.

EEPROM Data Memory The ATmega161 contains 512 bytes of data EEPROM memory. It is organized as a sep-

arate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles per location. The interface between the EEPROM and the CPU is described on page 60, specifying the EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control Register.

For the SPI data downloading, see page 125 for a detailed description.

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SRAM Data Memory Figure 8 shows how the ATmega161 SRAM memory is organized.

Figure 8. SRAM Organization

R0 $0000

R1 $0001

R2 $0002

……

R29 $001D

R30 $001E

R31 $001F

I/O Registers

$00 $0020

$01 $0021

$02 $0022

……

$3D $005D

$3E $005E

$3F $005F

Internal SRAM

$0060

$0061

…

$045E

$045F

The lower 1120 Data memory locations address the Register File, the I/O memory and the internal data SRAM. The first 96 locations address the Register File and I/O memory and the next 1K locations address the internal data SRAM. An optional external Data memory device can be placed in the same SRAM memory space. This memory device will occupy the locations following the internal SRAM and up to as much as 64K - 1, depending on external memory size.

When the addresses accessing the Data memory space exceed the internal data SRAM locations, the memory device is accessed using the same instructions as for the internal data SRAM access. When the internal data space is accessed, the read and write strobe pins (RD

and WR) are inactive during the whole access cycle. External memory operation is enabled by setting the SRE bit in the MCUCR Register. See “Interface to External Memory” on page 84 for details.

Accessing external memory takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH, and POP take one additional clock cycle. If the Stack is placed in external memory, interrupts, subroutine calls and returns take two clock cycles extra because the 2byte Program Counter is pushed and popped. When external memory interface is used with wait state, two additional clock cycles are used per byte. This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns will need four clock cycles more than specified in the Instruction Set manual.

ATmega161(L)

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ATmega161(L)

The five different Addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect Addressing Pointer Registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode features a 63-address locations reach from the base address given by the Y- or Z-register.

When using Register Indirect Addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented and incremented.

The 32 general purpose working registers, 64 I/O Registers and the 1K byte of internal data SRAM in the ATmega161 are all accessible through all these Addressing modes.

See the next section for a detailed description of the different Addressing modes.

Program and Data Addressing Modes

Register Direct, Single Register Rd

Register Direct, Two Registers Rd and Rr

The ATmega161 AVR RISC microcontroller supports powerful and efficient Addressing modes for access to the Program memory (Flash) and Data memory (SRAM, Register File and I/O memory). This section describes the different Addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.

Figure 9. Direct Single Register Addressing

OP d

The operand is contained in register d (Rd).

Figure 10. Direct Register Addressing, Two Registers

15 9 5 4 0

OP r d

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Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O Direct Figure 11. I/O Direct Addressing

nOP

Operand address is contained in six bits of the instruction word. n is the destination or Source Register Address.

Data Direct Figure 12. Direct Data Addressing

OP Rr/Rd

15 0

20 19

16 LSBs

I/O MEMORY

Data Space

$0000

$FFFF

A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.

ATmega161(L)

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ATmega161(L)

Data Indirect with

Figure 13. Data Indirect with Displacement

Displacement

Y OR Z - REGISTER

OP an

Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.

Data Indirect Figure 14. Data Indirect Addressing

X, Y, OR Z - REGISTER

Data Space

$0000

05610

$FFFF

Data Space

$0000

015

Data Indirect with Predecrement

$FFFF

Operand address is the contents of the X-, Y-, or Z-register.

Figure 15. Data Indirect Addressing with Pre-decrement

Data Space

$0000

015

X, Y, OR Z - REGISTER

-1

$FFFF

The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register.

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Data Indirect with Postincrement

Figure 16. Data Indirect Addressing with Post-increment

Data Space

$0000

015

X, Y, OR Z - REGISTER

$FFFF

The X-, Y-, or Z-register is incremented after the operation. Operand address is the contents of the X-, Y-, or Z-register prior to incrementing.

Constant Addressing Using the LPM Instruction

Indirect Program Addressing, IJMP and ICALL

Figure 17. Code Memory Constant Addressing

PROGRAM MEMORY

15 1 0

Z-REGISTER

$000

$1FFF

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 8K), the LSB selects Low byte if cleared (LSB = 0) or High byte if set (LSB = 1).

Figure 18. Indirect Program Memory Addressing

PROGRAM MEMORY

15 0

Z-REGISTER

$000

$1FFF

ATmega161(L)

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ATmega161(L)

Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

Relative Program Addressing, RJMP and RCALL

Direct Program Addressing, JMP and CALL

Figure 19. Relative Program Memory Addressing

15 12 11

OP k

PROGRAM MEMORY

$000

$1FFF

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

Figure 20. Direct Program Addressing

15 0

21 20

16 LSBs

PROGRAM MEMORY

$0000

Memory Access Times and Instruction Execution Timing

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$1FFF

Program execution continues at the address immediate in the instruction words.

This section describes the general access timing concepts for instruction execution and internal memory access.

TheAVRCPUisdrivenbytheSystemClockØ, directly generated from the external clock crystal for the chip. No internal clock division is used.

Figure 21 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power unit.

Figure 21. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 22 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register.

Figure 22. Single Cycle ALU Operation

T1 T2 T3 T4

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described in Figure 23.

Figure 23. On-chip Data SRAM Access Cycles

T1 T2 T3 T4

System Clock Ø

Address

Data

Prev. Address

Address

Write

Read

ATmega161(L)

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ATmega161(L)

l/O Memory The I/O space definition of the ATmega161 is shown in Table 1.

Table 1. ATmega161 I/O Space

I/O Address

(SRAM Address) Name Function

$3F($5F) SREG Status REGister

$3E ($5E) SPH Stack Pointer High

$3D ($5D) SPL Stack Pointer Low

$3B ($5B) GIMSK General Interrupt MaSK Register

$3A ($5A) GIFR General Interrupt Flag Register

$39 ($59) TIMSK Timer/Counter Interrupt MaSK Register

$38 ($58) TIFR Timer/Counter Interrupt Flag Register

$37 ($57) SPMCR Store Program Memory Control Register

$36 ($56) EMCUCR Extended MCU general Control Register

$35 ($55) MCUCR MCU general Control Register

$34 ($54) MCUSR MCU general Status Register

$33 ($53) TCCR0 Timer/Counter0 Control Register

$32 ($52) TCNT0 Timer/Counter0 (8-bit)

$31 ($51) OCR0 Timer/Counter0 Output Compare Register

$30 ($50) SFIOR Special Function IO Register

$2F ($4F) TCCR1A Timer/Counter1 Control Register A

(1)

$2E ($4E) TCCR1B Timer/Counter1 Control Register B

$2D ($4D) TCNT1H Timer/Counter1 High Byte

$2C ($4C) TCNT1L Timer/Counter1 Low Byte

$2B ($4B) OCR1AH Timer/Counter1 Output Compare RegisterA High Byte

$2A ($4A) OCR1AL Timer/Counter1 Output Compare RegisterA Low Byte

$29 ($49) OCR1BH Timer/Counter1 Output Compare RegisterB High Byte

$28 ($48) OCR1BL Timer/Counter1 Output Compare RegisterB Low Byte

$27 ($47) TCCR2 Timer/Counter2 Control Register

$26 ($46) ASSR Asynchronous mode StatuS Register

$25 ($45) ICR1H Timer/Counter1 Input Capture Register High Byte

$24 ($44) ICR1L Timer/Counter1 Input Capture Register Low Byte

$23 ($43) TCNT2 Timer/Counter2 (8-bit)

$22 ($42) OCR2 Timer/Counter2 Output Compare Register

$21 ($41) WDTCR Watchdog Timer Control Register

$20 ($40) UBRRHI UART Baud Register HIgh

$1F ($3F) EEARH EEPROM Address Register High

$1E ($3E) EEARL EEPROM Address Register Low

$1D ($3D) EEDR EEPROM Data Register

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Table 1. ATmega161 I/O Space

I/O Address

(SRAM Address) Name Function

$1C ($3C) EECR EEPROM Control Register

$1B($3B) PORTA Data Register, Port A

$1A ($3A) DDRA Data Direction Register, Port A

$19 ($39) PINA Input Pins, Port A

$18 ($38) PORTB Data Register, Port B

$17 ($37) DDRB Data Direction Register, Port B

$16 ($36) PINB Input Pins, Port B

$15 ($35) PORTC Data Register, Port C

$14 ($34) DDRC Data Direction Register, Port C

$13 ($33) PINC Input Pins, Port C

$12 ($32) PORTD Data Register, Port D

$11 ($31) DDRD Data Direction Register, Port D

$10 ($30) PIND Input Pins, Port D

$0F ($2F) SPDR SPI I/O Data Register

$0E ($2E) SPSR SPI Status Register

(1)

(Continued)

$0D ($2D) SPCR SPI Control Register

$0C ($2C) UDR0 UART0 I/O Data Register

$0B ($2B) UCSR0A UART0 Control and Status Register

$0A ($2A) UCSR0B UART0 Control and Status Register

$09 ($29) UBRR0 UART0 Baud Rate Register

$08 ($28) ACSR Analog Comparator Control and Status Register

$07 ($27) PORTE Data Register, Port E

$06 ($26) DDRE Data Direction Register, Port E

$05 ($25) PINE Input Pins, Port E

$03 ($23) UDR1 UART1 I/O Data Register

$02 ($22) UCSR1A UART1 Control and Status Register

$01 ($21) UCSR1B UART1 Control and Status Register

$00 ($20) UBRR1 UART1 Baud Rate Register

Note: 1. Reserved and unused locations are not shown in this table.

ATmega161(L)

1228C–AVR–08/02

ATmega161(L)

All ATmega161 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as SRAM, $20 must be added to this address. All I/O Register addresses throughout this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the Flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and Peripherals Control Registers are explained in the following sections.

Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

Bit 76543210

$3F ($5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

InitialValue00000000

• Bit 7

– I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6

– T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5

– H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. See the Instruction Set description for detailed information.

• Bit 4

– S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set description for detailed information.

• Bit 3

– V: Two’s Complement Overflow Flag

1228C–AVR–08/02

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information.

• Bit 1

– Z: Zero Flag

The Zero Flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set description for detailed information.

• Bit 0

– C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Stack Pointer – SP The ATmega161 Stack Pointer is implemented as two 8-bit registers in the I/O space

locations $3E ($5E) and $3D ($5D). As the ATmega161 supports up to 64-Kbyte memory, all 16 bits are used.

Bit 151413121110 9 8

$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

InitialValue00000000

00000000

Reset and Interrupt Handling

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when data is pushed onto the Stack with the PUSH instruction, and it is decremented by 2 when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the Stack with the POP instruction, and it is incremented by 2 when an address is popped from the Stack with return from subroutine RET or return from interrupt (RETI).

The ATmega161 provides 20 different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of Vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0) and so on.

ATmega161(L)

1228C–AVR–08/02

ATmega161(L)

Table 2. Reset and Interrupt Vectors

(1)

Vector

No. Program Address Source Interrupt Definition

1 $000 RESET External Pin, Power-on Reset and

Watchdog Reset

2 $002 INT0 External Interrupt Request 0

3 $004 INT1 External Interrupt Request 1

4 $006 INT2 External Interrupt Request 2

5 $008 TIMER2 COMP Timer/Counter2 Compare Match

6 $00a TIMER2 OVF Timer/Counter2 Overflow

7 $00c TIMER1 CAPT Timer/Counter1 Capture Event

8 $00e TIMER1 COMPA Timer/Counter1 Compare Match A

9 $010 TIMER1 COMPB Timer/Counter1 Compare Match B

10 $012 TIMER1 OVF Timer/Counter1 Overflow

11 $014 TIMER0 COMP Timer/Counter0 Compare Match

12 $016 TIMER0 OVF Timer/Counter0 Overflow

13 $018 SPI, STC Serial Transfer Complete

14 $01a UART0, RX UART0, Rx Complete

15 $01c UART1, RX UART1, Rx Complete

16 $01e UART0, UDRE UART0 Data Register Empty

17 $020 UART1, UDRE UART1 Data Register Empty

18 $022 UART0, TX UART0, Tx Complete

19 $024 UART1, TX UART1, Tx Complete

20 $026 EE_RDY EEPROM Ready

21 $028 ANA_COMP Analog Comparator

Note: 1. If BOOTRST fuse is programmed, the Reset Vector is located on program address

$1e00, see Table 39 on page 112 for details.

The most typical and general program setup for the Reset and Interrupt Vector addresses are:

Address Labels Code Comments

$000 jmp RESET ; Reset Handler

$002 jmp EXT_INT0 ; IRQ0 Handler

$004 jmp EXT_INT1 ; IRQ1 Handler

$006 jmp EXT_INT2 ; IRQ2 Handler

$008 jmp TIM2_COMP ; Timer2 Compare Handler

$00a jmp TIM2_OVF ; Timer2 Overflow Handler

$00c jmp TIM1_CAPT ; Timer1 Capture Handler

$00e jmp TIM1_COMPA ; Timer1 CompareA Handler

$010 jmp TIM1_COMPB ; Timer1 CompareB Handler

$012 jmp TIM1_OVF ; Timer1 Overflow Handler

$014 jmp TIM0_COMP ; Timer0 Compare Handler

$016 jmp TIM0_OVF ; Timer0 Overflow Handler

$018 jmp SPI_STC; ; SPI Transfer Complete Handler

1228C–AVR–08/02

$01a jmp UART_RXC0 ; UART0 RX Complete Handler

$01c jmp UART_RXC1 ; UART1 RX Complete Handler

$01e jmp UART_DRE0 ; UDR0 Empty Handler

$020 jmp UART_DRE1 ; UDR1 Empty Handler

$022 jmp UART_TXC0 ; UART0 TX Complete Handler

$024 jmp UART_TXC1 ; UART1 TX Complete Handler

$026 jmp EE_RDY ; EEPROM Ready Handler

$028 jmp ANA_COMP ; Analog Comparator Handler

;

$02a MAIN: ldi r16,high(RAMEND) ; Main program start

$02b out SPH,r16

$02c ldi r16,low(RAMEND)

$02d out SPL,r16

$02e <instr> xxx

…… ……

When the BOOTRST fuse is programmed, the most typical and general program setup for the Reset and Interrupt Vector addresses are:

Address Labels Code Comments

.org $002 ; Reset is located at $1e000

$002 jmp EXT_INT0 ; IRQ0 Handler

$004 jmp EXT_INT1 ; IRQ1 Handler

$006 jmp EXT_INT2 ; IRQ2 Handler

$008 jmp TIM2_COMP ; Timer2 Compare Handler

$00a jmp TIM2_OVF ; Timer2 Overflow Handler

$00c jmp TIM1_CAPT ; Timer1 Capture Handler

$00e jmp TIM1_COMPA ; Timer1 CompareA Handler

$010 jmp TIM1_COMPB ; Timer1 CompareB Handler

$012 jmp TIM1_OVF ; Timer1 Overflow Handler

$014 jmp TIM0_COMP ; Timer0 Compare Handler

$016 jmp TIM0_OVF ; Timer0 Overflow Handler

$018 jmp SPI_STC; ; SPI Transfer Complete Handler

$01a jmp UART_RXC0 ; UART0 RX Complete Handler

$01c jmp UART_RXC1 ; UART1 RX Complete Handler

$01e jmp UART_DRE0 ; UDR0 Empty Handler

$020 jmp UART_DRE1 ; UDR1 Empty Handler

$022 jmp UART_TXC0 ; UART0 TX Complete Handler

$024 jmp UART_TXC1 ; UART1 TX Complete Handler

$026 jmp EE_RDY ; EEPROM Ready Handler

$028 jmp ANA_COMP ; Analog Comparator Handler

;

$02a MAIN: ldi r16,high(RAMEND); Main program start

$02b out SPH,r16

$02c ldi r16,low(RAMEND)

$02d out SPL,r16

$02e <instr> xxx

;

.org $1e00 $1e00 jmp RESET ; Reset handler …… ……

ATmega161(L)

1228C–AVR–08/02

Reset Sources The ATmega161 has three sources of Reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V

POT

• External Reset. The MCU is reset when a low level is present on the RESET

more than 500 ns.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and

the Watchdog is enabled.

During Reset, all I/O Registers are then set to their initial values and the program starts execution from address $000. The instruction placed in address $000 must be a JMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used and regular program code can be placed at these locations. The circuit diagram in Figure 24 shows the Reset Logic. Table 3 and Table 4 define the timing and electrical parameters of the reset circuitry.

Figure 24. Reset Logic

DATA BU S

MCU Status

ATmega161(L)

pin for

PORF

WDRF

EXTRF

CKSEL[2:0]

Delay Counters

Full

1228C–AVR–08/02

Table 3. Reset Characteristics (V

=5.0V)

(1)

Symbol Parameter Min Typ Max Units

POT

RST

Power-on Reset Threshold Voltage (rising) 1.0 1.4 1.8 V

Power-on Reset Threshold Voltage (falling)

RESET Pin Threshold Voltage 0.85 V

(1)

0.4 0.6 0.8 V

Note: 1. The Power-on Reset will not work unless the supply voltage has been below V

(falling).

‘

Table 4. Reset Delay Selections

CKSEL [2:0]

Start-up Time, VCC=2.7V, SUT Unprogrammed

(3)

Start-up Time, VCC=4.0V, SUT Programmed

Recommended

(1)

Usage

000 4.2 ms + 6 CK 5.8 ms + 6 CK External Clock, Fast

Rising Power

001 30 µs + 6 CK 10 µs + 6 CK External Clock

(2)

010 67 ms + 16K CK 92 ms + 16K CK Crystal Oscillator,

Slowly Rising Power

011 4.2 ms + 16K CK 5.8 ms + 16K CK Crystal Oscillator,

Fast Rising Power

100 30 µs + 16K CK 10 µs + 16K CK Crystal Oscillator

101 67 ms + 1K CK 92 ms + 1K CK Ceramic

Resonator/External Clock, Slowly Rising Power

POT

(2)

110 4.2 ms + 1K CK 5.8 ms + 1K CK Ceramic Resonator,

Fast Rising Power

111 30 µs + 1K CK 10 µs + 1K CK Ceramic

Resonator

(2)

Notes: 1. The CKSEL fuses control only the start-up time. The Oscillator is the same for all

selections. On Power-up, the real-time part of the start-up time is increased with typ.

0.6 ms.

2. External Power-on Reset.

3. Table 4 shows the Start-up Times from Reset. From sleep, only the clock counting part of the start-up time is used. The Watchdog Oscillator is used for timing the realtime part of the start-up time. The number WDT Oscillator cycles used for each timeout is shown in Table 5.

Table 5. Number of Watchdog Oscillator Cycles

SUT Time-out Number of Cycles

Unprogrammed 4.2 ms (at V

Unprogrammed 67 ms (at V

Programmed 5.8 ms (at V

Programmed 92 ms (at V

=2.7V) 1K

= 2.7V) 16K

=4.0V) 4K

= 4.0V) 64K

The frequency of the Watchdog Oscillator is voltage-dependent as shown in the Electrical Characteristics section. The device is shipped with CKSEL = 010.

ATmega161(L)

1228C–AVR–08/02

ATmega161(L)

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is nominally 1.4V (rising V the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes a delay counter, which determines the delay, for which the device is kept in RESET after V the delay counter can be defined by the user through the CKSEL fuses. The eight different selections for the delay period are presented in Table 4. The RESET signal is activated again, without any delay, when the V

). The POR is activated whenever VCCis below

rise. The time-out period of

decreases below detection level.

Figure 25. MCU Start-up, RESET

VCC

RESET

TIME-OUT

INTERNAL

RESET

POT

RST

TOUT

Tied to V

Figure 26. MCU Start-up, RESET Controlled Externally

VCC

RESET

TIME-OUT

POT

RST

TOUT

1228C–AVR–08/02

INTERNAL

RESET

External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer

than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. When the applied signal reaches the Reset Threshold Voltage (V Time-out period (t

TOUT

) on its positive edge, the delay timer starts the MCU after the

RST

) has expired.

Figure 27. External Reset during Operation

Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period (t

). Refer to page 58 for details on operation of the Watchdog.

TOU T

Figure 28. Watchdog Reset during Operation

ATmega161(L)

1228C–AVR–08/02

ATmega161(L)

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit 76543210

$34 ($54) ––––WDRF – EXTRF PORF MCUSR

Read/Write R R R R R/W R R/W R/W

Initial Value 0 0 0 0 See Bit Description

• Bits 7..4

– Res: Reserved Bits

These bits are reserved bits in the ATmega161 and always read as zero.

• Bit 3

– WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is cleared by a Power-on Reset or by writing a logical “0” to the Flag.

• Bit 2

– Res: Reserved Bit

This bit are reserved bit in the ATmega161 and always read as zero.

• Bit 1

– EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is cleared by a Power-on Reset or by writing a logical “0” to the Flag.

• Bit 0

– PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is cleared only by writing a logical “0” to the Flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then clear the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

Interrupt Handling The ATmega161 has two 8-bit Interrupt Mask Control Registers; GIMSK (General Inter-

rupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the Flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag will be set and remembered until the interrupt is enabled or the Flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.

1228C–AVR–08/02

Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is present.

Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by software.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this four-clock-cycle period, the Program Counter (13 bits) is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in Sleep mode, the interrupt execution response time is increased by four clock cycles.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I-Flag in SREG is set. When AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

General Interrupt Mask Register – GIMSK

Bit 76543210

$3B ($5B) INT1 INT0 INT2 –––––GIMSK

Read/Write R/W R/W RRRRRR

InitialValue00000000

• Bit 7

– INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or is level-sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from Program memory address $004. See also “External Interrupts”.

• Bit 6

– INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or is level-sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from Program memory address $002. See also “External Interrupts.”

• Bit 5 – INT2: External Interrupt Request 2 Enable

When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control2 bit (ISC02 in the Extended MCU Control Register [EMCUCR]) defines whether the external interrupt is activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an interrupt request even if INT2 is configured as an output. The corresponding interrupt of External Interrupt Request 2 is executed from Program memory address $006. See also “External Interrupts.”

ATmega161(L)

1228C–AVR–08/02

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