Rainbow Electronics ATmega128RFA1 User Manual

ATmega128RFA1

Features

• High Performance, Low Power AVR® 8-Bit Microcontroller

• Advanced RISC Architecture

- 135 Powerful Instructions – Most Single Clock Cycle Execution

- 32x8 General Purpose Working Registers

- Fully Static Operation

- Up to 16 MIPS Throughput at 16 MHz and 1.8V

- On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

- 128K Bytes of In-System Self-Programmable Flash

• Endurance: 2000 Write/Erase Cycles @ 85°C

- 4K Bytes EEPROM

• Endurance: 2000 Write/Erase Cycles @ 85°C

- 16K Bytes Internal SRAM

• JTAG (IEEE std. 1149.1 compliant) Interface

- Boundary-scan Capabilities According to the JTAG Standard

- Extensive On-chip Debug Support

- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface

• Peripheral Features

- Multiple Timer/Counter & PWM channels

- Real Time Counter with Separate Oscillator

- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor

- Master/Slave SPI Serial Interface

- Two Programmable Serial USART

- Byte Oriented 2-wire Serial Interface

• Advanced Interrupt Handler

• Watchdog Timer with Separate On-Chip Oscillator

• Power-on Reset and Low Current Brown-Out Detector

• Advanced Power Save Modes

• Fully integrated Low Power Transceiver for 2.4 GHz ISM Band

- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s

- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm

- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)

- 32 Bit IEEE 802.15.4 Symbol Counter

- Baseband Signal Processing

- SFR-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation

- Antenna Diversity and TX/RX control

- TX/RX 128 Byte Frame Buffer

• Hardware Security (AES, True Random Generator)

• Integrated Crystal Oscillators (32.768 kHz & 16 MHz)

• I/O and Package

- 38 Programmable I/O Lines

- 64-pad QFN (RoHS/Fully Green)

• Temperature Range: -40°C to 85°C Industrial

• Supply voltage range 1.8V to 3.6V with integrated voltage regulators

• Ultra Low Power consumption (1.8 to 3.6V) for Rx/Tx & AVR: <18.6 mA

- CPU Active Mode (16MHz): 4.1 mA

- 2.4GHz Transceiver: RX_ON 12.5 mA / TX 14.5 mA (maximum TX output power)

- Deep Sleep Mode: <250nA @ 25°C

• Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V

8-bit Microcontroller with Low Power

2.4GHz Transceiver for ZigBee and IEEE 802.15.4

ATmega128RFA1

PRELIMINARY

Applications

• ZigBee® / IEEE 802.15.4-2006/2003™ – Full And Reduced Function Device (FFD/RFD)

• General Purpose 2.4GHz ISM Band Transceiver with Microcontroller

• RF4CE, SP100, WirelessHART™, ISM Applications and IPv6 / 6LoWPAN

8266A-MCU Wireless-12/09

ATmega128RFA1

1 Pin Configurations

The large center pad underneath the QFN/MLF package is made of metal and internally connected

to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the

62 61 60 59 58 57 64 63

17 18 19 20 21 23 22 24 25 26

[PD3:TXD1:INT3]

[PD2:RXD1:INT2]

[PD1:SDA:INT1]

[PD0:SCL:INT0]

[DVSS]

[DEVDD]

[DVDD]

[DVSS:DSVSS]

[PG5:OC0B]

[PG4:TOSC1]

[PG3:TOSC2]

[PD7:T0]

[PD6:T1]

[PD5:XCK1]

[PD4:ICP1]

[PF2:ADC2:DIG2]

[PF3:ADC3:DIG4]

[PF4:ADC4:TCK]

[PF5:ADC5:TMS]

[PF6:ADC6:TDO]

[PF7:ADC7:TDI]

[AVSS_RFP]

[AVSS_RFN]

[PG0:DIG3]

[PG1:DIG1]

[PG2:AMR]

Figure 1-1. Pinout ATmega128RFA1

[PF1:ADC1]

[PF0:ADC0]

[AREF]

[AVSS:ASVSS]

[EVDD]

[AVDD]

[RFP]

[RFN]

[TST]

[RSTN]

[RSTON]

Index corner

Exposed paddle: [AVSS]

ATmega128RFA1

[XTAL2]

[AVSS]

[DVSS]

[XTAL1]

56 55 54 53 52 51

[DEVDD]

[PE7:ICP3:INT7:CLKO]

[PE6:T3:INT6]

[PE5:OC3C:INT5]

[PE4:OC3B:INT4]

[PE3:OC3A:AIN1]

50 49

[PE2:XCK0:AIN0]

[PE1:TXD0]

[PE0:RXD0:PCINT8]

[DVSS]

[DEVDD]

[PB7:OC0A:OC1C:PCINT7]

[PB6:OC1B:PCINT6]

[PB5:OC1A:PCINT5]

[PB4:OC2A:PCINT4]

[PB3:MISO:PDO:PCINT3]

[PB2:MOSI:PDI:PCINT2]

[PB1:SCK:PCINT1]

[PB0:SSN:PCINT0]

[DVSS]

[DEVDD]

[CLKI]

31 32

2 Disclaimer

Note:

center pad is left unconnected, the package might loosen from the board

Typical values contained in this datasheet are based on simulation and characterization results of other AVR microcontrollers and radio transceivers manufactured in a similar process technology. Minimum and Maximum values will be available after the device is characterized.

8266A-MCU Wireless-12/09

ATmega128RFA1

3 Overview

The ATmega128RFA1 is a low-power CMOS 8 bit microcontroller based on the AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz ISM band. It is derived from the ATmega1281 microcontroller and the AT86RF231 radio transceiver.

By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The radio transceiver provides high data rates from 250 kb/s up to 2 Mb/s, frame handling, outstanding receiver sensitivity and high transmit output power enabling a very robust wireless communication.

3.1 Block Diagram

Figure 3-1 Block Diagram

8266A-MCU Wireless-12/09

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two independent registers can be accessed with one single instruction executed in one clock cycle. The resulting architecture is very code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The system includes internal voltage regulation and an advanced power management. Distinguished by the small leakage current it allows an extended operation time from battery.

The radio transceiver is a fully integrated ZigBee solution using a minimum number of external components. It combines excellent RF performance with low cost, small size and low current consumption. The radio transceiver includes a crystal stabilized fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread

ATmega128RFA1

Spectrum Signal (DSSS) processing with spreading and despreading. The device is fully compatible with IEEE802.15.4-2006/2003 and ZigBee standards.

The ATmega128RFA1 provides the following features: 128 kbytes of In-System Programmable (ISP) Flash with read-while-write capabilities, 4 kbytes EEPROM, 16 kbytes SRAM, up to 35 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), 6 flexible Timer/Counters with compare modes and PWM, USART, a byte oriented 2-wire Serial Interface, a 8 channel, 10 bit analog to digital converter (ADC) with an optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, a SPI serial port, IEEE std.

1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and 6 software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the RC oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main RC oscillator and the asynchronous timer continue to run.

Typical supply current of the microcontroller with CPU clock set to 16MHz and the radio transceiver for the most important states is shown in the

Figure 3-2 below.

Figure 3-2 Radio transceiver and microcontroller (16MHz) supply current

1.8V

3.0V

3.6V

16,6mA

18,6mA

I(DEVDD,EVDD) [mA]

The transmit output power is set to maximum. If the radio transceiver is in SLEEP mode the current is dissipated by the AVR microcontroller only.

In Deep Sleep mode all major digital blocks with no data retention requirements are disconnected from main supply providing a very small leakage current. Watchdog timer, MAC symbol counter and 32.768kHz oscillator can be configured to continue to run.

250nA

Deep Sleep SLEEP TRX_OFF RX_LISTEN TX_ACT

4,1mA

Radio Transceiver State

4,7mA

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system

8266A-MCU Wireless-12/09

ATmega128RFA1

trough an SPI serial interface, by a conventional nonvolatile memory programmer, or by on on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the boot Flash section will continue to run while the application Flash section is updated, providing true Read-While-Write operation. By combining an 8 bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128RFA1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

3.2 Pin Descriptions

3.2.1 EVDD

3.2.2 DEVDD

3.2.3 AVDD

3.2.4 DVDD

3.2.5 DVSS

3.2.6 AVSS

3.2.7 Port B (PB7...PB0)

The ATmega128RFA1 AVR is supported with a full suite of program and system development tools including: C compiler, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

External analog supply voltage;

External digital supply voltage;

Regulated analog supply voltage (internally generated);

Regulated digital supply voltage (internally generated);

Digital ground;

Analog ground;

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also provides functions of various special features of the ATmega128RFA1.

3.2.8 Port D (PD7...PD0)

3.2.9 Port E (PE7...PE0)

8266A-MCU Wireless-12/09

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also provides functions of various special features of the ATmega128RFA1.

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also provides functions of various special features of the ATmega128RFA1.

ATmega128RFA1

3.2.10 Port F (PF7...PF0)

Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also provides functions of various special features of the ATmega128RFA1.

3.2.11 Port G (PG5…PG0)

3.2.12 AVSS_RFP

3.2.13 AVSS_RFN

3.2.14 RFP

3.2.15 RFN

3.2.16 RSTN

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. However the driver strength of PG3 and PG4 is reduced compared to the other port pins. The output voltage drop (VOH, VOL) is higher while the leakage current is smaller. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also provides functions of various special features of the ATmega128RFA1.

AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.

AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.

RFP is the positive terminal for the bi-directional, differential RF I/O port.

RFN is the negative terminal for the bi-directional, differential RF I/O port.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

3.2.17 RSTON

Reset output. A low level on this pin indicates a reset initiated by the internal reset sources or the pin RSTN.

3.2.18 XTAL1

Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.

3.2.19 XTAL2

Output of the inverting 16MHz crystal oscillator amplifier;

3.2.20 AREF

Reference voltage output of the A/D Converter. In general this pin is left open.

3.2.21 TST

Programming and test mode enable pin;

3.2.22 CLKI

Input to the clock system. If selected, it provides the operating clock of the microcontroller.

3.3 Compatibility to ATmega1281/2561

The basic AVR feature set of the ATmega128RFA1 is derived from the ATmega1281/2561. Address locations and names of the implemented modules and

8266A-MCU Wireless-12/09

ATmega128RFA1

registers are unchanged as long as it fits the target application of a very small and power efficient radio system. In addition, several new features were added.

Backward compatibility of the ATmega128RFA1 to the ATmega1281/2561 is provided in most cases. However some incompatibilities between the microcontrollers exist.

3.3.1 Port A and Port C

Port A and Port C are not implemented. The associated registers are available but will not provide any port control. Remaining ports are kept at their original address location to not require changes of existing software packages.

3.3.2 External Memory Interface

The alternate pin function “External Memory interface” using Port A and Port C is not implemented due to the missing ports.

The large internal data memory (SRAM) does not require an external memory and the associated parallel interface. It keeps the system radiation (EMC) at a very small level to provide very high sensitivity at the antenna input.

3.3.3 High Voltage Programming Mode

Alternate pin function BS2 (high voltage programming) of pin PA0 is mapped to a different pin. Entering the parallel programming mode is controlled by the TST pin.

3.3.4 AVR Oscillators and External Clock

The AVR microcontroller can utilize the high performance crystal oscillator of the

2.4GHz transceiver connected to the pins XTAL1 and XTAL2. An external clock can be applied to the microcontroller using the clock input CLKI.

3.3.5 Analog Frontend

The ATmega128RFA1 has a new A/D converter. Software compatibility is basically assured. Nevertheless to benefit from the higher conversion speeds and the better performance some changes are required.

4 Resources

A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com.

5 About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

6 Data Retention

8266A-MCU Wireless-12/09

Reliability Qualification results show that the projected data retention failure rate for the given ambient temperature is less than TBD PPM

ATmega128RFA1

• over 10 years at 85°C

• TBD years at 25°C.

8266A-MCU Wireless-12/09

ATmega128RFA1

7 AVR CPU Core

7.1 Introduction

7.2 Architectural Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculation, control peripherals, and handle interrupts.

Figure 7-1.Block Diagram of the AVR Architecture

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Data Bus 8-bit

Status

and Control

32 x 8

General

Purpose

Registrers

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Direct Addressing

ALU

Indirect Addressing

Data

SRAM

Analog

Comparator



I/O Module1



I/O Module 2

8266A-MCU Wireless-12/09

I/O Module n

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

ATmega128RFA1

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega128RFA1 has Extended I/O space from 0x60 - 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

7.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

8266A-MCU Wireless-12/09

ATmega128RFA1

7.4 Status Register

7.4.1 SREG – Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

Bit 7 6 5 4 3 2 1 0

$3F ($5F) I T H S V N Z C SREG

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I - Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 – T - Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source

and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

• Bit 5 – H - Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the

Instruction Set Description for detailed information.

• Bit 4 – S - Sign Bit The S-bit is always an exclusive or between the negative flag N and the two's

complement overflow flag V. See the Instruction Set Description for detailed information.

• Bit 3 – V - Two's Complement Overflow Flag The two's complement overflow flag V supports two's complement arithmetics. See the

Instruction Set Description for detailed information.

• Bit 2 – N - Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic

operations. See the Instruction Set Description for detailed information.

• Bit 1 – Z - Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations.

See the Instruction Set Description for detailed information.

8266A-MCU Wireless-12/09

• Bit 0 – C - Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction

Set Description for detailed information. Note that the status register is not automatically

ATmega128RFA1

stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

7.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 7-1 below shows the structure of the 32 general purpose working registers in the

CPU.

Figure 7-1. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 7-1 above on page 12, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Zpointer registers can be set to index any register in the file.

7.5.1 The X-register, Y-register, and Z-register

The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-2

on page 13.

8266A-MCU Wireless-12/09

ATmega128RFA1

7.6 Stack Pointer

Figure 7-2. The X-, Y-, Z-registers

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

7.6.1 SPH – Stack Pointer High

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer is the last address of the internal SRAM.

The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

When the FLASH memory exceeds 128Kbyte one additional cycle is required. In this case the Stack Pointer is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt and is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

Bit 7 6 5 4 3 2 1 0

$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 1 0 0 0 0 1

8266A-MCU Wireless-12/09

The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

• Bit 7:0 – SP15:8 - Stack Pointer High Byte

ATmega128RFA1

7.6.2 SPL – Stack Pointer Low

Bit 7 6 5 4 3 2 1 0

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

Read/Write RW RW RW RW RW RW RW RW Initial Value 1 1 1 1 1 1 1 1

• Bit 7:0 – SP7:0 - Stack Pointer Low Byte

7.6.3 RAMPZ – Extended Z-pointer Register for ELPM/SPM

Bit 7 6 5 4 3 2 1 0

$3B ($5B) Res5 Res4 Res3 Res2 Res1 Res0 RAMPZ1 RAMPZ0 RAMPZ

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL. Note that LPM is not affected by the RAMPZ setting.

• Bit 7:2 – Res5:0 - Reserved For compatibility with future devices, be sure to write these bits to zero.

• Bit 1:0 – RAMPZ1:0 - Extended Z-Pointer Value These two bits represent the MSB's of the Z-Pointer.

Table 7-2 RAMPZ Register Bits

RAMPZ1:0 0 Default value of Z-pointer MSB's.

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-3 below. Note that LPM is not affected by the RAMPZ setting.

Figure 7-3. The Z-pointer used by ELPM and SPM

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero.

8266A-MCU Wireless-12/09

ATmega128RFA1

7.7 Instruction Execution Timing

Figure 7-4. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 7-5 below shows the internal timing concept for the Register File. In a single

clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

Figure 7-5. Single Cycle ALU operation

clk

CPU

T1 T2 T3 T4

Total Execution Time

ALU Operation Execute

Result Write Back

7.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section "Memory Programming" on page 464 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on

page 211. The list also determines the priority levels of the different interrupts. The

lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to "Interrupts" on page 211 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see "Memory Programming" on page 464.

clk

CPU

8266A-MCU Wireless-12/09

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested

ATmega128RFA1

interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

8266A-MCU Wireless-12/09

ATmega128RFA1

7.8.1 Interrupt Response Time

Assembly Code Example

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

8266A-MCU Wireless-12/09

ATmega128RFA1

8 AVR Memories

This section describes the different memories in the ATmega128RFA1. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega128RFA1 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

8.1 In-System Reprogrammable Flash Program Memory

The ATmega128RFA1 contains 128K bytes On-chip In-System Reprogrammable Flash memory for program storage, see 32 bits wide, the Flash is 16 bit wide. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 2000 write/erase cycles. The ATmega128RFA1 Program Counter (PC) is 16 bits wide, thus addressing the required program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in "Boot Loader Support –

Read-While-Write Self-Programming" on page 450. "Memory Programming" on page 464 contains a detailed description on Flash data serial downloading using the SPI pins

or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description and ELPM – Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in "Instruction

Execution Timing" on page 15.

Figure 8-6 below. Since all AVR instructions are 16 or

Figure 8-6. Program Flash Memory Map

Program Memory

8.2 SRAM Data Memory

Application Flash Section

$0000

Boot Flash Section

Figure 8-7 on page 19 shows how the ATmega128RFA1 SRAM Memory is organized.

The ATmega128RFA1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 – $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory and the following locations address the internal data SRAM.

8266A-MCU Wireless-12/09

ATmega128RFA1

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the internal data SRAM in the ATmega128RFA1 are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page 12.

Figure 8-7. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

416 Ext I/O Reg.

Internal SRAM

(16K x 8)

$0000 - $001F $0020 - $005F $0060 - $01FF

$0200

$41FF

8.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. Access to the internal data SRAM is performed in two clk

Figure 8-8 on page 20.

8266A-MCU Wireless-12/09

$FFFF

CPU

cycles as described in

ATmega128RFA1

Figure 8-8. On-Chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

Address

Data

Compute Address

Address valid

Data

Write

Read

8.3 EEPROM Data Memory

The ATmega128RFA1 contains 4Kbyte of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 2000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see "Serial Downloading" on page 477, "Programming via the JTAG Interface" on page

481, and "Programming the EEPROM" on page 491 respectively.

8.3.1 EEPROM Read Write Access

The EEPROM Access Registers are accessible in the I/O space, see "EEPROM

The write access time for the EEPROM is given in Table 8-3 below. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, DVDD is likely to rise or fall slowly on powerup/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See "Preventing EEPROM

Corruption" on page 22 for details on how to avoid problems in these situations.

Memory Access Instruction

Next Instruction



In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See the description of the EEPROM Control Register for details on this,

"EEPROM Register Description" on page 23.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

The calibrated Oscillator is used to time the EEPROM accesses. The following table lists the typical programming time for EEPROM access from the CPU.

Table 8-3. EEPROM Programming Time

Symbol Typical Programming time

EEPROM write (from CPU) 4ms

EEPROM erase (from CPU) 8ms

8266A-MCU Wireless-12/09

ATmega128RFA1

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

8266A-MCU Wireless-12/09

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

ATmega128RFA1

Assembly Code Example

sbic EECR,EEPE

rjcmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

8.3.2 Preventing EEPROM Corruption

During periods of low DEVDD, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

8266A-MCU Wireless-12/09

ATmega128RFA1

8.4 EEPROM Register Description

8.4.1 EEARH – EEPROM Address Register High Byte

Bit 7 6 5 4 3 2 1 0

$22 ($42) Res3 Res2 Res1 Res0 EEAR11 EEAR10 EEAR9 EEAR8 EEARH

Read/Write R R R R RW RW RW RW Initial Value 0 0 0 0 X X X X

The EEPROM Address Registers EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

• Bit 7:4 – Res3:0 - Reserved

• Bit 3:0 – EEAR11:8 - EEPROM Address

8.4.2 EEARL – EEPROM Address Register Low Byte

Bit 7 6 5 4 3 2 1 0

$21 ($41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Read/Write RW RW RW RW RW RW RW RW Initial Value X X X X X X X X

• Bit 7:0 – EEAR7:0 - EEPROM Address

8.4.3 EEDR – EEPROM Data Register

Bit 7 6 5 4 3 2 1 0

$20 ($40) EEDR7:0 EEDR

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

8266A-MCU Wireless-12/09

• Bit 7:0 – EEDR7:0 - EEPROM Data

ATmega128RFA1

8.4.4 EECR – EEPROM Control Register

Bit 7 6 5 4 3 2 1 0

$1F ($3F) Res1 Res0 EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R RW RW RW RW RW RW Initial Value 0 0 X X 0 0 X 0

• Bit 7:6 – Res1:0 - Reserved

• Bit 5:4 – EEPM1:0 - EEPROM Programming Mode

The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in the following table. While EEPE is set, any write to EEPM1:0 will be ignored. During reset, the EEPM1:0 bits will be reset to 0 unless the EEPROM is busy programming.

Table 8-4 EEPM Register Bits

EEPM1:0

• Bit 3 – EERIE - EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.

Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE - EEPROM Master Write Enable The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be

written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

0x00 Erase and Write in one operation (Atomic

Operation)

0x01 Erase only

0x02 Write only

0x03 Reserved for future use

• Bit 1 – EEPE - EEPROM Programming Enable The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When

address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be adopted when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

8266A-MCU Wireless-12/09

ATmega128RFA1

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted.

Caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE - EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM nor to change the EEAR Register.

8.5 I/O Memory

The Input/Output (I/O) space definition of the ATmega128RFA1 is shown in "Register

Summary" on page 496.

All ATmega128RFA1 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the AVR instruction set for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega128RFA1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits may not be modified. Reserved registers and I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The control registers of I/O and peripherals are explained in later sections.

8266A-MCU Wireless-12/09

ATmega128RFA1

8.6 General Purpose I/O Registers

The ATmega128RFA1 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

8.6.1 GPIOR0 – General Purpose IO Register 0

Bit 7 6 5 4 3 2 1 0

$1E ($3E) GPIOR07:00 GPIOR0

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The three General Purpose I/O Registers can be used for storing any information.

• Bit 7:0 – GPIOR07:00 - General Purpose I/O Register 0 Value

8.6.2 GPIOR1 – General Purpose IO Register 1

Bit 7 6 5 4 3 2 1 0

$2A ($4A) GPIOR17:10 GPIOR1

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The three General Purpose I/O Registers can be used for storing any information.

• Bit 7:0 – GPIOR17:10 - General Purpose I/O Register 1 Value

8.6.3 GPIOR2 – General Purpose I/O Register 2

Bit 7 6 5 4 3 2 1 0

$2B ($4B) GPIOR27:20 GPIOR2

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The three General Purpose I/O Registers can be used for storing any information.

• Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value

8.7 Other Port Registers

The inherited control registers of missing ports located in the I/O space are kept in the ATmega128RFA1. They can be used as general purpose I/O registers for storing any information. Registers placed in the address range 0x00 – 0x1F are directly bitaccessible using the SBI, CBI, SBIS and SBIC instructions.

8266A-MCU Wireless-12/09

ATmega128RFA1

8.7.1 PORTA – Port A Data Register

Bit 7 6 5 4 3 2 1 0

$02 ($22) PORTA7:0 PORTA

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The PORTA register can be used as a General Purpose I/O Register for storing any information.

• Bit 7:0 – PORTA7:0 - Port A Data Register Value

8.7.2 DDRA – Port A Data Direction Register

Bit 7 6 5 4 3 2 1 0

$01 ($21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The DDRA register can be used as a General Purpose I/O Register for storing any information.

• Bit 7:0 – DDA7:0 - Port A Data Direction Register Value

8.7.3 PINA – Port A Input Pins Address

Bit 7 6 5 4 3 2 1 0

$00 ($20) PINA7:0 PINA

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The PINA register is reserved for interal use and cannot be used as a General Purpose I/O Register.

• Bit 7:0 – PINA7:0 - Port A Input Pins

8.7.4 PORTC – Port C Data Register

Bit 7 6 5 4 3 2 1 0

$08 ($28) PORTC7:0 PORTC

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The PORTC register can be used as a General Purpose I/O Register for storing any information.

• Bit 7:0 – PORTC7:0 - Port C Data Register Value

8266A-MCU Wireless-12/09

ATmega128RFA1

8.7.5 DDRC – Port C Data Direction Register

Bit 7 6 5 4 3 2 1 0

$07 ($27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0

The DDRC register can be used as a General Purpose I/O Register for storing any information.

• Bit 7:0 – DDC7:0 - Port C Data Direction Register Value

8.7.6 PINC – Port C Input Pins Address

Bit 7 6 5 4 3 2 1 0

$06 ($26) PINC7:0 PINC

Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0

The PINC register is reserved for interal use and cannot be used as a General Purpose I/O Register.

• Bit 7:0 – PINC7:0 - Port C Input Pins

8266A-MCU Wireless-12/09

ATmega128RFA1

9 Low-Power 2.4 GHz Transceiver

9.1 Features

• High performance RF-CMOS 2.4 GHz radio transceiver targeted for IEEE

802.15.4™, ZigBee™, IPv6 / 6LoWPAN, RF4CE, SP100, WirelessHART™ and ISM applications

• Outstanding link budget (103.5 dB):

o Receiver sensitivity -100 dBm o Programmable output power from -17 dBm up to +3.5 dBm

• Ultra-low current consumption:

o TRX_OFF = 0.4 mA o RX_ON = 12.5 mA o BUSY_TX = 14.5 mA (at max. transmit power of +3.5 dBm)

• Optimized for low BoM cost and ease of production:

o Few external components necessary (crystal, capacitors and

o Excellent ESD robustness

• Easy to use interface:

o Registers and frame buffer access from software o Dedicated radio transceiver interrupts

• Radio transceiver features:

o 128 byte FIFO (SRAM) for data buffering o Integrated RX/TX switch o Fully integrated, fast settling PLL to support frequency hopping o Battery monitor o Fast wake-up time < 0.25 ms

• Special IEEE 802.15.4 2006 hardware support:

o FCS computation and clear channel assessment (CCA) o RSSI measurement, energy detection and link quality indication

• MAC hardware accelerator:

o Automated acknowledgement, CSMA-CA and frame

o Automatic address filtering o Automated FCS check

• Extended Feature Set Hardware Support:

o AES 128 bit hardware accelerator o RX/TX indication (external RF front-end control) o RX antenna diversity o Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s o True random number generation for security applications

• Compliant to IEEE 802.15.4-2006, IEEE 802.15.4-2003 and RF4CE

• Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210

antenna)

retransmission

8266A-MCU Wireless-12/09

ATmega128RFA1

The ATmega128RFA1 features a low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate

2.4 GHz ISM band applications. The radio transceiver is a true peripheral block of the AVR microcontroller. All RF-critical components except the antenna, crystal and decoupling capacitors are integrated on-chip. Therefore, the ATmega128RFA1 is particularly suitable for applications like:

• 2.4 GHz IEEE 802.15.4 and ZigBee systems

• 6LoWPAN and RF4CE systems

• Wireless sensor networks

• Industrial control, sensing and automation (SP100, WirelessHART)

• Residential and commercial automation

• Health care

• Consumer electronics

• PC peripherals

9.2 General Circuit Description

This radio transceiver is part of a system-on-chip solution with an AVR® microcontroller. It comprises a complex peripheral component containing the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. The number of external components for the transceiver operation is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed.

The ATmega128RFA1 block diagram is shown in

Figure 9-9. Transceiver Block Diagram

DIG3/4

RFP

RFN

LNA

DIG1/2

Analog Domain Digital Domain

ext. PA and Power

Control

PLL PA

PPF BPF Limiter

Antenna Diversity

Figure 9-9 below.

XTAL1

XOSC

XTAL2

AVREG

Configuration Registers

TX Data

FTN, BATMON

AGC

ADC

RSSI

TX BBP

Frame

Buffer

RX BBP

DVREG

µC

Interface

AES

Control Logic

Data

Interrupts

Address

Control

8266A-MCU Wireless-12/09

+ 494 hidden pages