Rainbow Electronics ATmega128L User Manual
Features
• High-performance, Low-power AVR
• Advanced RISC Architecture
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 128K Bytes of In-System Reprogrammable Flash
Endurance: 1,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– 4K Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 4K Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented 2-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
• I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP
• Operating Voltages
– 2.7 - 5.5V for ATmega128L
– 4.5 - 5.5V for ATmega128
• Speed Grades
– 0 - 8 MHz for ATmega128L
– 0 - 16 MHz for ATmega128
®
8-bit Microcontroller
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Preliminary
Rev. 2467B-09/01
1
Pin Configurations Figure 1. Pinout ATmega128
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PEN
RXD0/(PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(IC3/INT7) PE7
(SS) PB0
(SCK) PB1
(MOSI) PB2
(MISO) PB3
(OC0) PB4
(OC1A) PB5
(OC1B) PB6
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
VCC
GND
XTAL2
RESET
TOSC2/PG3
TOSC1/1PG4
(OC2/OC1C) PB7
XTAL1
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(T1) PD6
(IC1) PD4
(XCK1) PD5
49
48
PA3 (AD3)
47
PA4 (AD4)
46
PA5 (AD5)
45
PA6 (AD6)
44
PA7 (AD7)
43
PG2(ALE)
42
PC7 (A15)
41
PC6 (A14)
40
PC5 (A13)
39
PC4 (A12)
38
PC3 (A11)
37
PC2 (A10)
36
PC1 (A9)
35
PC0 (A8)
34
PG1(RD)
33
PG0(WR)
32
(T2) PD7
Overview The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2
ATmega128(L)
2467B–09/01
Block Diagram
Figure 2. Block Diagram
ATmega128(L)
VCC
GND
AVCC
AGND
AREF
PEN
DATA REGISTER
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
PORTF DRIVERS
PORTF
DATA DIR.
REG. PORTF
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
DATA REGISTER
PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PA0 - PA7PF0 - PF7
PORTA DRIVERS
DATA DIR.
REG. PORTA
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
PORTC DRIVERS
DATA REGISTER
PORTC
CALIB. OSC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
PC0 - PC7
DATA DIR.
REG. PORTC
XTAL1
XTAL2
RESET
TOR
ANALOG
COMPARA
DATA REGISTER
+
-
USART0
PORTE
CONTROL
LINES
DATA DIR.
REG. PORTE
PORTE DRIVERS
ALU
STATUS
REGISTER
DATA REGISTER
PORTB
PORTB DRIVERS
PB0 - PB7PE0 - PE7
DATA DIR.
REG. PORTB
EEPROM
SPI
DATA REGISTER
PORTD
PORTD DRIVERS
PD0 - PD7
USART1
DATA DIR.
REG. PORTD
2-WIRE SERIAL
INTERFACE
DATA REG.
PORTG
DATA DIR.
REG. PORTG
PORTG DRIVERS
PG0 - PG4
2467B–09/01
3
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53
general-purpose I/O lines, 32 general purpose working registers, Real Time Counter
(RTC), four flexible timer/counters with compare modes and PWM, 2 USARTs, a byte
oriented 2-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input
stage with programmable gain, programmable Watchdog Timer with internal oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and six software selectable
power saving modes. The Idle mode stops the CPU while allowing the SRAM,
timer/counters, SPI port, and interrupt system to continue functioning. The Power-down
mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction Mode stops the CPU and all I/O modules
except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption.
In Extended Standby mode, both the main oscillator and the asynchronous timer continue to run.
ATmega103 and ATmega128 Compatibility
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The on-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an on-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is
a powerful microcontroller that provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
The ATmega128 is a highly complex microcontroller where the number of I/O locations
supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward
compatibility with the ATmega103, all I/O locations present in ATmega103 have the
same location in ATmega128. Most additional I/O locations are added in an Extended
I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These
location can be reached by using LD/LDS/LDD and ST/STS/STD instruction only, not by
using IN and OUT instruction. The relocation of the internal RAM space may still be a
problem for ATmega103 users. Also, the increased number of interrupt vectors might be
a problem if the code uses absolute addresses. To solve these problems, an
ATmega103 compatibility mode can be selected by programming the fuse M103C. In
this mode, none of the functions in the Extended I/O space are in use, so the internal
RAM is located as in ATmega103. Also, the extended interrupt vectors are removed.
4
ATmega128(L)
2467B–09/01
ATmega128(L)
The ATmega128 is 100% pin compatible with ATmega103, and can replace the
ATmega103 on current Printed Circuit Boards. The application note “Replacing
ATmega103 by ATmega128” describes what the user should be aware of replacing the
ATmega103 by an ATmega128.
ATmega103 Compatibility Mode
By programming the M103C fuse, the ATmega128 will be compatible with the
ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode,
these features are listed below:
• One USART instead of two, asynchronous mode only. Only the 8 least significant
bits of the Baud Rate Register is available.
• One 16 bits Timer/Counter with 2 compare registers instead of two 16-bit
Timer/Counters with 3 compare registers.
• 2-wire serial interface is not supported.
• Port G serves alternate functions only (not a general I/O port).
• Port F serves as digital input only in addition to analog input to the ADC.
• Boot Loader capabilities is not supported.
• It is not possible to adjust the frequency of the internal calibrated RC oscillator.
• The External Memory Interface can not release any Address pins for general I/O,
neither configure different wait-states to different External Memory Address
sections.
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port A pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega128 as listed
page 68.
on
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega128 as listed
page 69.
on
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
2467B–09/01
5
Port C also serves the functions of special features of the ATmega128 as listed on page
72
. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not
tri-stated when a reset condition becomes active.
Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega128 as listed
page 73.
on
Port E (PE7..PE0) Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each
bit). The Port E output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega128 as listed
page 76.
on
Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output
buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port F pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port F pins are tri-stated when a reset condition becomes
active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input Port only.
Port G (PG4..PG0) Port G is a 5-bit bidirectional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port G pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features.
The port G pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the
external memory as well as input to the 32 kHz oscillator, and the pins are initialized to
PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active,
even if the clock is not running. PG3 and PG4 are oscillator pins.
RESET
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in
19 on page 46
. Shorter pulses are not guaranteed to generate a reset.
Table
6
ATmega128(L)
2467B–09/01
ATmega128(L)
XTAL2 Output from the inverting oscillator amplifier.
AVCC This is the supply voltage pin for Port F and the A/D Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
AREF This is the analog reference pin for the A/D Converter.
PEN This is a programming enable pin for the serial programming mode. By holding this pin
low during a power-on reset, the device will enter the serial programming mode. PEN
has no function during normal operation.
About Code Examples
This datasheet contains simple code examples that briefly show how to use various
parts of the device. These code examples assume that the part specific header file is
included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
2467B–09/01
7
AVR CPU Core
Introduction This chapter discusses the AVR core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to
access memories, perform calculations, control peripherals and handle interrupts.
Architectural Overview Figure 3. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Indirect Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Data
SRAM
EEPROM
I/O Lines
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module1
I/O Module 2
I/O Module n
In order to maximize performance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable Flash memory.
The fast-access Register file contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register file, the
operation is executed, and the result is stored back in the Register file – in one clock
cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be used as an address pointer for look up tables in flash program memory. These added function registers are the 16-bit X-register, Y-register and
Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
8
ATmega128(L)
2467B–09/01
ATmega128(L)
an arithmetic operation, the Status Register is updated to reflect information about the
result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions,
able to directly address the whole address space. Most AVR instructions have a single
16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and
the Application Program section. Both sections have dedicated Lock Bits for write and
read/write protection. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot program section.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The stack pointer SP is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All interrupts have a separate interrupt
vector in the interrupt vector table. The interrupts have priority in accordance with their
interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses which can be accessed directly, or as the
Data Space locations following those of the Register file, $20 - $5F. In addition, the
ATmega128 has Extended I/O space from $60 - $FF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between
general-purpose registers or between a register and an immediate are executed. The
ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsigned multiplication and fractional format. See the “Instruc-
tion Set” section for a detailed description.
Status Register The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditional operations. Note that the status register is updated after all ALU
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The status register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
The AVR status register – SREG – is defined as:
Bit 76543210
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
2467B–09/01
9
• Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global
interrupt enable register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared in software with the SEI and CLI instructions, as
described in the instruction set reference.
• Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source or
destination for the operated bit. A bit from a register in the Register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register file by the BLD instruction.
• Bit 5 - H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry is
useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 - S: Sign Bit, S = N
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 - N: Negative Flag
⊕ V
General Purpose Register File
The negative flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Description” for detailed information.
• Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
The Register file is optimized for the AVR Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
10
ATmega128(L)
2467B–09/01
ATmega128(L)
Figure 4. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
Most of the instructions operating on the Register file have direct access to all registers,
and most of them are single cycle instructions.
X-register, Y-register and Zregister
As shown in
Figure 4, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X, Y, and Z pointer registers can be set to
index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for indirect addressing of the Data Space.
The three indirect address registers X, Y, and Z are described in
Figure 5.
Figure 5. The X, Y and Z Registers
15 XH XL 0
X - register 7 0 7 0
R27 ($1B) R26 ($1A)
15 YH YL 0
Y - register 7 0 7 0
R29 ($1D) R28 ($1C)
15 ZH ZL 0
Z - register 7 0 7 0
R31 ($1F) R30 ($1E)
2467B–09/01
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set
Reference for details).
11
Stack Pointer The stack is mainly used for storing temporary data, for storing local variables and for
storing return addresses after interrupts and subroutine calls. The stack pointer register
always points to the top of the stack. Note that the stack is implemented as growing from
higher memory locations to lower memory locations. This implies that a stack PUSH
command decreases the stack pointer.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the Stack with the PUSH instruction, and it is decremented by two
when the return address is pushed onto the Stack with subroutine call or interrupt. The
Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented by two when data is popped from the Stack with return
from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH register will not be present.
Bit 151413121110 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
00000000
RAM Page Z Select Register – RAMPZ
Bit 7 6 5 4 3 2 1 0
– –– – – – – – RAMPZ0 RAMPZ
Read/Write R R R R R R R R/W
Initial value 0 0 0 0 0 0 0 0
• Bits 7..2 - Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.
• Bit 1 - RAMPZ0: Extended RAM Page Z-pointer
The RAMPZ register is normally used to select which 64K RAM Page is accessed by the
Z pointer. As the ATmega128 does not support more than 64K of SRAM memory, this
register is used only to select which page in the program memory is accessed when the
ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects:
RAMPZ0 = 0: Program memory address $0000- $7FFF (lower 64K bytes) is
accessed by ELPM/SPM
RAMPZ0 = 1: Program memory address $8000- $FFFF (higher 64K bytes) is
accessed by ELPM/SPM
Note that LPM is not affected by the RAMPZ setting.
12
ATmega128(L)
2467B–09/01
ATmega128(L)
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The
AVR CPU is driven by the CPU clock clk
, directly generated from the selected clock
CPU
source for the chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7 shows the internal timing concept for the Register file. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 7. Single Cycle ALU Operation
T1 T2 T3 T4
Reset and Interrupt Handling
clk
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
CPU
The AVR provides several different interrupt sources. These interrupts and the separate
reset vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together
with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Depending on the program counter value, interrupts may be automatically disabled
when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section
“Memory Programming” on page 279 for details.
The lowest addresses in the program memory space are by default defined as the Reset
and Interrupt vectors. The complete list of vectors is shown in
“Interrupts” on page 54.
The list also determines the priority levels of the different interrupts. The lower the
address the higher is the priority level. RESET has the highest priority, and next is INT0
– the External Interrupt Request 0. The interrupt vectors can be moved to the start of the
boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).
Refer to
“Interrupts” on page 54 for more information. The Reset vector can also be
moved to the start of the boot Flash section by programming the BOOTRST fuse, see
“Boot Loader Support – Read-While-Write Self-Programming” on page 266.
2467B–09/01
13
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts
are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the interrupt flag. For these interrupts, the Program Counter is vectored to the
actual interrupt vector in order to execute the interrupt handling routine, and hardware
clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit
is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
14
ATmega128(L)
2467B–09/01
ATmega128(L)
Assembly Code Example
sei ; set global interrupt enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set global interrupt enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles
minimum. After 4 clock cycles, the program vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this
jump takes 3 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by 4
clock cycles. This increase comes in addition to the start-up time from the selected
sleep mode.
A return from an interrupt handling routine takes 4 clock cycles. During these 4-clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer
is incremented by 2, and the I-bit in SREG is set.
2467B–09/01
15
AVR ATmega128 Memories
This section describes the different memories in the ATmega128. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega128 features an EEPROM Memory for data storage. All three
memory spaces are linear and regular.
In-System Reprogrammable Flash Program Memory
The ATmega128 contains 128K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is
organized as 64K x 16. For software security, the Flash Program memory space is
divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 1,000 write/erase cycles. The
ATmega128 Program Counter (PC) is 16 bits wide, thus addressing the 64K program
memory locations. The operation of Boot Program section and associated Boot Lock
Bits for software protection are described in detail in
While-Write Self-Programming” on page 266
tains a detailed description on Flash data serial downloading using the SPI pins or the
JTAG interface.
Constant tables can be allocated within the entire program memory address space (see
the LPM – Load Program Memory and ELPM – Extended Load Program Memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in
tion Timing” on page 13
Figure 8. Program Memory Map
.
Program Memory
. “Memory Programming” on page 279 con-
“Boot Loader Support – Read-
“Instruction Execu-
$0000
16
Application Flash Section
Boot Flash Section
$FFFF
ATmega128(L)
2467B–09/01
ATmega128(L)
SRAM Data Memory The ATmega128 supports two different configurations for the SRAM data memory as
listed in
Table 1. Memory Configurations
Configuration Internal SRAM Data Memory External SRAM Data Memory
Normal Mode 4096 up to 64K
Table 1.
ATmega103 Compatibility
Mode
Figure 9 shows how the ATmega128 SRAM Memory is organized.
The ATmega128 is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the
ATmega128 is in the ATmega103 compatibility mode.
In normal mode, the first 4352 Data Memory locations address both the Register file, the
I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 4096 locations address the internal data
SRAM.
In ATmega103 compatibility mode, the first 4096 Data Memory locations address both
the Register file, the I/O Memory and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O memory, and the next
4000 locations address the internal data SRAM.
An optional external data SRAM can be used with the ATmega128. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. The Register file, I/O, Extended I/O
and Internal SRAM uses the occupies the lowest 4352 bytes in normal mode, and the
lowest 4096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so
when using 64KB (65536 bytes) of External Memory, 61184 Bytes of External Memory
are available in normal mode, and 61440 Bytes in ATmega103 compatibility mode. See
“External Memory Interface” on page 24 for details on how to take advantage of the
external memory map.
4000 up to 64K
2467B–09/01
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR
register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH and POP take one additional clock cycle. If the stack is placed in external SRAM,
interrupts, subroutine calls and returns take three clock cycles extra because the twobyte program counter is pushed and popped, and external memory access does not
take advantage of the internal pipe-line memory access. When external SRAM interface
is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupt, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.
17
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register file, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4096 bytes of internal data SRAM in the ATmega128 are all accessible through all these addressing
modes. The Register file is described in
“General Purpose Register File” on page 10.
Figure 9. Data Memory Map
Memory Configuration A
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
(4096 x 8)
External SRAM
(0 - 64K x 8)
$0000 - $001F
$0020 - $005F
$0060 - $00FF
$0100
$10FF
$1100
$FFFF
Memory Configuration B
Data Memory
32 Registers
64 I/O Registers
Internal SRAM
(4000 x 8)
External SRAM
(0 - 64K x 8)
$0000 - $001F
$0020 - $005F
$0060
$0FFF
$1000
$FFFF
Data Memory Access Times This section describes the general access timing concepts for internal memory access.
18
The internal data SRAM access is performed in two clk
10
ATmega128(L)
.
cycles as described in Figure
CPU
2467B–09/01
Figure 10. On-chip Data SRAM Access Cycles
T1 T2 T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
ATmega128(L)
Write
Read
Memory access instruction
Next instruction
EEPROM Data Memory The ATmega128 contains 4K bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI and JTAG data downloading to the EEPROM, see
page 292 and page 297 respectively.
EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in
ever, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In
heavily filtered power supplies, V
is likely to rise or fall slowly on power-up/down. This
CC
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used.
23.
for details on how to avoid problems in these situations.
See “Preventing EEPROM Corruption” on page
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
Table 2. A self-timing function, how-
EEPROM Address Register – EEARH and EEARL
2467B–09/01
Bit 151413121110 9 8
––––EEAR11 EEAR10 EEAR9 EEAR8 EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543210
Read/Write R R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 X X X X
XXXXXXXX
• Bits 15..12 - Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.
19
EEPROM Data Register – EEDR
EEPROM Control Register – EECR
• Bits 11..0 - EEAR11..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address
in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 4096. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit 76543210
MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
• Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit 76543210
––––EERIE EEMWE EEWE EERE
Read/Write R R R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 X 0
EECR
• Bits 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEWE is cleared.
• Bit 2 - EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will
write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to
one will have no effect. When EEMWE has been written to one by software, hardware
clears the bit to zero after four clock cycles. See the description of the EEWE bit for an
EEPROM write procedure.
• Bit 1 - EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE,
otherwise no EEPROM write takes place. The following procedure should be followed
when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
20
ATmega128(L)
2467B–09/01
ATmega128(L)
The EEPROM can not be programmed during a CPU write to the Flash memory. The
software must check that the Flash programming is completed before initiating a new
EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing
the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2
can be omitted. See
page 266
for details about boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be
modified, causing the interrupted EEPROM access to fail. It is recommended to have
the global interrupt flag cleared during the 4 last steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the next instruction is
executed.
• Bit 0 - EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
“Boot Loader Support – Read-While-Write Self-Programming” on
The user should poll the EEWE bit before starting the read operation. If a write operation
is in progress, it is neither possible to read the EEPROM, nor to change the EEAR
register.
The calibrated oscillator is used to time the EEPROM accesses.
Table 2 lists the typical
programming time for EEPROM access from the CPU.
Table 2. EEPROM Programming Time.
Symbol
EEPROM Write
(from CPU)
Number of Calibrated
RC Oscillator Cycles
Approximately 8300 7.5 ms 9.0 ms
Min Programming
Time
Max Programming
Time
The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The
examples also assume that no flash boot loader is present in the software. If such code
is present, the EEPROM write function must also wait for any ongoing SPM command to
finish.
2467B–09/01
21
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
22
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during
execution of these functions.
ATmega128(L)
2467B–09/01
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
ATmega128(L)
Preventing EEPROM Corruption
During periods of low V
the EEPROM data can be corrupted because the supply volt-
CC,
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too
low. First, a regular write sequence to the EEPROM requires a minimum voltage to
operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the
supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design
recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low
Reset Protection circuit can be used. If a reset occurs while a write operation is in
V
CC
progress, the write operation will be completed provided that the power supply voltage is
sufficient.
2467B–09/01
23
I/O Memory The I/O space definition of the ATmega128 is shown in “Register Summary” on page
323
.
All ATmega128 I/Os and peripherals are placed in the I/O space. All I/O locations may
be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data
between the 32 general purpose working registers and the I/O space. I/O registers
within the address range $00 - $1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the instruction set chapter for more details. When
using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be
used. When addressing I/O registers as data space using LD and ST instructions, $20
must be added to these addresses. The ATmega128 is a complex microcontroller with
more peripheral units than can be supported within the 64 location reserved in Opcode
for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM,
only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O
space is replaced with SRAM locations when the ATmega128 is in the ATmega103
compatibility mode.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a one back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The I/O and peripherals control registers are explained in later sections.
External Memory Interface
Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal
With all the features the External Memory Interface provides, it is well suited to operate
as an interface to memory devices such as external SRAM and Flash, and peripherals
such as LCD-display, A/D, and D/A. The main features are:
• Four different wait-state settings (including no wait-state).
• Independent wait-state setting for different external memory sectors (configurable
sector size).
• The number of bits dedicated to address high byte is selectable.
• Bus keepers on data lines to minimize current consumption (optional).
SRAM becomes available using the dedicated external memory pins (see
page 2
memory configuration is shown in
, Table 27 on page 68, Table 33 on page 72, and Table 45 on page 80). The
Figure 11.
Figure 1 on
24
ATmega128(L)
2467B–09/01
Figure 11. External Memory with Sector Select
ATmega128(L)
External Memory
(0-60K x 8)
Memory Configuration A
Internal memory
Lower sector
SRW01
SRW00
Upper sector
SRW11
SRW10
0x0000
0x10FF
0x1100
SRL[2..0]
0xFFFF
Memory Configuration B
0x0000
Internal memory
0x0FFF
0x1000
SRW10
External Memory
(0-60K x 8)
0xFFFF
Note: ATmega128 in non ATmega103 compatibility mode: Memory Configuration A is available
(Memory Configuration B N/A)
ATmega128 in ATmega103 compatibility mode: Memory Configuration B is available
(Memory Configuration A N/A)
ATmega103 Compatibility Both External Memory Control Registers (XMCRA and XMCRB) are placed in Extended
I/O space. In ATmega103 Compatibility mode, these registers are not available, and the
features selected by these registers are not available. The device is still ATmega103
compatible, as these features did not exist in ATmega103. The limitations in
ATmega103 compatibility mode are:
• Only two wait-states settings are available (SRW1n = 0b00 and SRW1n = 0b01).
• The number of bits that are assigned to address high byte are fixed.
• The external memory section can not be divided into sectors with different wait-state
settings.
• Bus-keeper is not available.
, WR and ALE pins are output only (Port G in ATmega128).
Using the External Memory Interface
• RD
The interface consists of:
• AD7:0: Multiplexed low-order address bus and data bus.
• A15:8: High-order address bus (configurable number of bits).
• ALE: Address latch enable.
• RD
: Read strobe.
• WR: Write strobe.
2467B–09/01
25
The control bits for the External Memory Interface are located in three registers, the
MCU Control Register – MCUCR, the External Memory Control Register A – XMCRA,
and the External Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the
data direction registers that corresponds to the ports dedicated to the XMEM interface.
For details about the port override, see the alternate functions in section
page 60
. The XMEM interface will auto-detect whether an access is internal or external.
“I/O-Ports” on
If the access is external, the XMEM interface will output address, data, and the control
signals on the ports according to
Figure 13 (this figure shows the wave forms without
wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is
low during a data transfer. When the XMEM interface is enabled, also an internal access
will cause activity on address, data and ALE ports, but the RD
and WR strobes will not
toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is
disabled, the address space above the internal SRAM boundary is not mapped into the
internal SRAM.
Figure 12 illustrates how to connect an external SRAM to the AVR using
an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.
Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style 74HC series
latch becomes inadequate. The external memory interface is designed in compliance to
the 74AHC series latch. However, most latches can be used as long they comply with
the main timing parameters. The main parameters for the address latch are:
• D to Q propagation delay (t
• Data setup time before G low (t
• Data (address) hold time after G low (
PD
).
).
SU
).
TH
The external memory interface is designed to guaranty minimum address hold time after
G is asserted low of t
Tables 138 through Tables 145 on pages 317 - 319. The D-to-Q propagation delay
ing”
) must be taken into consideration when calculating the access time requirement of
(t
PD
= 5 ns. Refer to t
h
LAXX_LD/tLLAXX_ST
the external component. The data setup time before G low (t
address valid to ALE low (t
) minus PCB wiring delay (dependent on the capacitive
AVLLC
in “External Data Memory Tim-
) must not exceed
SU
load).
Figure 12. External SRAM Connected to the AVR
D[7:0]
AD7:0
AVR
ALE
A15:8
RD
WR
DQ
G
A[7:0]
SRAM
A[15:8]
RD
WR
Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is
written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.
26
ATmega128(L)
2467B–09/01
ATmega128(L)
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper
can be disabled and enabled in software as described in
ister B – XMCRB” on page 31
. When enabled, the bus-keeper will keep the previous
value on the AD7:0 bus while these lines are tri-stated by the XMEM interface.
If neither bus-keeper nor pull-ups are enabled, the XMEM interface will leave the AD7:0
tri-stated during a read access until the next RAM access (internal or external) appears.
Timing External memory devices have different timing requirements. To meet these require-
ments, the ATmega128 XMEM interface provides four different wait-states as shown in
Table 4. It is important to consider the timing specification of the external memory
device before selecting the wait-state. The most important parameters are the access
time for the external memory compared to the set-up requirement of the ATmega128.
The access time for the external memory is defined to be the time from receiving the
chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data
is stable during a read sequence (See t
145
on pages 317 - 319). The different wait-states are set up in software. As an addi-
LLRL
+ t
RLRH
tional feature, it is possible to divide the external memory space in two sectors with
individual wait-state settings. This makes it possible to connect two different memory
devices with different timing requirements to the same XMEM interface. For XMEM
interface timing details, please refer to
159
in the “External Data Memory Timing” on page 317.
Table 138 to Table 145 and Figure 156 to Figure
“External Memory Control Reg-
- t
in Tables 138 through Tables
DVRH
Note that the XMEM interface is asynchronous and that the waveforms in the following
figures are related to the internal system clock. The skew between the internal and
external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without Wait-state
(SRWn1 = 0 and SRWn0 = 0)
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
CPU
ALE
A15:8
DA7:0
WR
RD
)
(1)
T1 T2 T3
AddressPrev. addr.
Address DataPrev. data XX
T4
Write
DataPrev. data Address
DataPrev. data Address
Read
2467B–09/01
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external).
27
Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1
(1)
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
CPU
ALE
A15:8
DA7:0
WR
RD
T1 T2 T3
)
AddressPrev. addr.
Address DataPrev. data XX
DataPrev. data Address
DataPrev. data Address
T4
T5
Write
Read
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM
(internal or external).
Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0
System Clock (CLK
CPU
T1 T2 T3
)
T4 T5
(1)
T6
ALE
A15:8
DA7:0
WR
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
RD
Address DataPrev. data XX
AddressPrev. addr.
DataPrev. data Address
DataPrev. data Address
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM
(internal or external).
Write
Read
28
ATmega128(L)
2467B–09/01
ATmega128(L)
XMEM Register Description
MCU Control Register – MCUCR
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
CPU
ALE
A15:8
DA7:0
WR
)
T1 T2 T3
AddressPrev. addr.
Address DataPrev. data XX
DataPrev. data Address
DataPrev. data Address
RD
T4 T5 T6
(1)
T7
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
Bit 76543210
SRE SRW10
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000
SE SM1 SM0 SM2 IVSEL IVCE MCUCR
Write
Read
External Memory Control Register A – XMCRA
• Bit 7 - SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR
, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to
zero, disables the External Memory Interface and the normal pin and data direction settings are used.
• Bit 6 - SRW10: Wait-state Select Bit
For a detailed description in non-ATmega103 Compatibility mode, see common description for the SRWn bits below (XMCRA description). In ATmega103 Compatibility mode,
writing SRW10 to one enables the wait-state and one extra cycle is added during
read/write strobe as shown in
Bit 76543210
- SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 - XMCRA
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial value00000000
Figure 14.
• Bit 7 - Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location,
write this bit to zero for compatibility with future devices.
2467B–09/01
29
• Bit 6..4 - SRL2, SRL1, SRL0: Wait-state Sector Limit
It is possible to configure different wait-states for different external memory addresses.
The external memory address space can be divided in two sectors that have separate
wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
3
and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the
Table
entire external memory address space is treated as one sector. When the entire SRAM
address space is configured as one sector, the wait-states are configured by the
SRW11 and SRW10 bits.
Table 3. Sector limits with different settings of SRL2..0
SRL2 SRL1 SRL0 Sector Limits
0 0 0 Lower sector = N/A
Upper sector = 0x1100-0xFFFF
0 0 1 Lower sector = 0x1100-0x1FFF
Upper sector = 0x2000-0xFFFF
0 1 0 Lower sector = 0x1100-0x3FFF
Upper sector = 0x4000-0xFFFF
0 1 1 Lower sector = 0x1100-0x5FFF
Upper sector = 0x6000-0xFFFF
1 0 0 Lower sector = 0x1100-0x7FFF
Upper sector = 0x8000-0xFFFF
1 0 1 Lower sector = 0x1100-0x9FFF
Upper sector = 0xA000-0xFFFF
1 1 0 Lower sector = 0x1100-0xBFFF
Upper sector = 0xC000-0xFFFF
1 1 1 Lower sector = 0x1100-0xDFFF
Upper sector = 0xE000-0xFFFF
• Bit 1 and Bit 6 MCUCR - SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of
the external memory address space, see
Table 4.
• Bit 3..2 - SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of
the external memory address space, see
Table 4. Wait States
SRWn1 SRWn0 Wait States
0 0 No wait-states
0 1 Wait one cycle during read/write strobe
1 0 Wait two cycles during read/write strobe
1 1 Wait two cycles during read/write and wait one cycle before driving out
Note: 1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see
Figures 13 through Figures 16 for how the setting of the SRW bits affects the timing.
(1)
new address
Table 4.
30
ATmega128(L)
2467B–09/01
Loading...