Rainbow Electronics ATF750LVC User Manual

Features

• 3.0V to 3.6V Operating Range

• Advanced, High-speed, Electrically-erasable Programmable Logic Device

– Superset of 22V10
– Enhanced Logic Flexibility
– Architecturally Compatible with ATV750B and ATV750 Software and Hardware

• D- or T-type Flip-flop

• Product Term or Direct Input Pin Clocking

• 15 ns Maximum Pin-to-pin Delay with 3V Operation

• Highest Density Programmable Logic Available in 24-pin Package

– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested

• Increased Logic Flexibility

– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops

• Enhanced Output Logic Flexibility

– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs

• Programmable Pin-keeper Circuits

• Dual-in-line and Surface Mount Package in Standard Pinouts

• Commercial and Industrial Temperature Ranges

• 20-year Data Retention

• 2000V ESD Protection

• 1000 Erase/Write Cycles

Block Diagram

High-speed
Complex
Programmable
Logic Device

ATF750LVC

(OE PRODUCT TERMS)

12

INPUT

PINS

PROGRAMMABLE

INTERCONNECT

AND

COMBINATORIAL

LOGIC ARRAY

4TO8

PRODUCT

TERMS

(CLOCK PIN)

LOGIC

OPTION

(UP T0 20

FLIP-FLOPS)

OUTPUT

OPTION

10

I/O

PINS

Description

The Atmel “750” architecture is twice as powerful as most other 24-pin programmable
logic devices. Increased product terms, sum terms, flip-flops and output logic configu­rations translate into more usable gates. High-speed logic and uniform, predictable
delays guarantee fast in-system performance. The ATF750LVC is a high-performance

(continued)

Pin Configurations

Pin Name Function

CLK Clock

IN Logic Inputs

I/O Bi-directional Buffers

GND Ground

VCC 3V Supply

Note: For PLCC, pins 1, 8, 15, and 22

can be left unconnected. For
superior performance, connect
VCC to pin 1 and GND to pins
8, 15, and 22.

DIP/SOIC/TSSOP

CLK/IN

GND

1
2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

IN

9

IN

10

IN

11

IN

12

24
23
22
21
20
19
18
17
16
15
14
13

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN

GND *

IN
IN
IN

IN
IN
IN

PLCC

ININCLK/IN

VCC *

432

5
6
7
8
9
10
11

1

12131415161718

IN

IN

GND

GND *

VCC

I/O

282726

IN

I/O

I/O

I/O

25

I/O

24

I/O

23

GND *

22

I/O

21

I/O

20

I/O

19

I/O

Rev. 1447D–03/01

1

CMOS (electrically-erasable) complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-eras­able technology.

Each of the ATF750LVC’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi­directional I/O pins. Each flip-flop is individually config­urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.

There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
format is used to assign between four to eight product

Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +4.6V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

(1)

(1)

terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.

Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu­ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip­flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to 4.6V for pulses of less
than 20 ns.

+ 0.75V DC,

CC

DC and AC Operating Conditions

3.3V Operation Commercial Industrial

Operating Temperature (Ambient) 0°C - 70°C -40°C - +85°C

V

Power Supply 3.0 - 3.6V 3.0 -=3.6V

CC

2

ATF750LVC

Clock Mux

Output Options

CLOCK

PRODUCT

TERM

CKi

CLK

PIN

ATF750LVC

CKMUX

TO

LOGIC

CELL

SELECT

Bus-friendly Pin-keeper Input and I/Os

All input and I/O pins on the ATF750LVC(L) have program­mable “pin-keeper” circuits. If activated, when any pin is
driven high or low and then subsequently left floating, it will
stay at that previous high or low level.

This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec­essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.

Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.

Table 1. Software Compiler Mode Selection

Synario Wincupl Pin-keeper Circuit

ATF750LVC V750C Disabled

ATF750LVC (PPK) V750CPPK Enabled

Input Diagram

INPUT

I/O Diagram

OE

DATA

ESD

PROTECTION

CIRCUIT

V

CC

V

CC

100K

PROGRAMMABLE

OPTION

V

CC

I/O

100K

PROGRAMMABLE

OPTION

3

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

LI

I

LO

I

CC

Input Load Current VIN = -0.1V to VCC + 1V 10 µA

Output Leakage
Current

Power Supply
Current, Standby

= -0.1V to VCC + 0.1V 10 µA

V

OUT

= Max,

V

CC

= Max,

V

IN

Outputs Open

C-15

Com. 65 90 mA

Ind. 70 100 mA

(1)(2)

I

OS

V

IL

V

IH

V

OL

V

OH

Output Short
Circuit Current

V

= 0.5V -120 mA

OUT

Input Low Voltage 3.0 ≤ VCC ≤ 3.6V -0.6 0.8 V

Input High Voltage 2.0 V

I

= 16 mA Com., Ind. 0.5 V
Output Low
Vol ta ge

Output High
Vol ta ge

VIN = VIH or VIL,

= Min

V

CC

VIN = VIH or VIL,

= Min

V

CC

OL

I

= 12 mA Mil. 0.5 V

OL

I

= 24 mA Com. 0.8 V

OL

= -2.0 mA 2.4 V

I

OH

+ 0.75 V

CC

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

2. This test is performed at initial characterisation only.

Input Test Waveforms and Measurement Levels

Output Test Load

VCC

316 Ω

348 Ω

tR, tF < 3 ns (10% to 90%)

4

ATF750LVC

ATF750LVC

AC Waveforms, Product Term Clock

(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics, Product Term Clock

(1)

-15

Symbol Parameter

UnitsMin Max

t

PD

t

EA

t

ER

t

CO

t

CF

t

S

t

SF

t

H

t

P

t

W

Input or Feedback to Non-registered Output 15 ns

Input to Output Enable 15 ns

Input to Output Disable 15 ns

Clock to Output 5 12 ns

Clock to Feedback 5 9 ns

Input Setup Time 8 ns

Feedback Setup Time 7 ns

Hold Time 5 ns

Clock Period 14 ns

Clock Width 7 ns

External Feedback 1/(tS + tCO)50MHz

f

MAX

t

AW

t

AR

t

AP

t

SP

Internal Feedback 1/(tSF + tCF)62MHz

No Feedback 1/(t

) 71 MHz

P

Asynchronous Reset Width 15 ns

Asynchronous Reset Recovery Time 15 ns

Asynchronous Reset to Registered Output Reset 15 ns

Setup Time, Synchronous Preset 8 ns

Note: 1. See ordering information for valid part numbers.

5