Rainbow Electronics ATF750CL User Manual

Features

• Advanced, High-speed, Electrically-erasable Programmable Logic Device

– Superset of 22V10
– Enhanced Logic Flexibility
– Backward Compatible with ATV750B/BL and ATV750/L

• Low-power Edge-sensing “L” Option with 1 mA Standby Current

• D- or T-type Flip-flop

• Product Term or Direct Input Pin Clocking

• 7.5 ns Maximum Pin-to-pin Delay with 5V Operation

• Highest Density Programmable Logic Available in 24-pin Package

– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested

• Increased Logic Flexibility

– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops

• Enhanced Output Logic Flexibility

– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs

• Programmable Pin-keeper Circuits

• Dual-in-line and Surface Mount Package in Standard Pinouts

• Commercial and Industrial Temperature Ranges

• 20-year Data Retention

• 2000V ESD Protection

• 1000 Erase/Write Cycles

Block Diagram

High-speed
Complex
Programmable
Logic Device

ATF750C
ATF750CL

(OE PRODUCT TERMS)

12

INPUT

PINS

PROGRAMMABLE

INTERCONNECT

AND

COMBINATORIAL

LOGIC ARRAY

4TO8

PRODUCT

TERMS

(CLOCK PIN)

LOGIC

OPTION

(UP T0 20

FLIP-FLOPS)

OUTPUT

OPTION

10

I/O

PINS

Description

The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform predictable delays

(continued)

Pin Configurations

Pin Name Function

CLK Clock

IN Logic Inputs

I/O Bi-directional Buffers

GND Ground

VCC +5V Supply

Note: For PLCC, pins 1, 8, 15, and 22

can be left unconnected. For
superior performance, connect
VCC to pin 1 and GND to pins
8, 15, and 22.

DIP/SOIC/TSSOP

CLK/IN

GND

1
2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

IN

9

IN

10

IN

11

IN

12

24
23
22
21
20
19
18
17
16
15
14
13

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN

GND *

IN
IN
IN

IN
IN
IN

PLCC

ININCLK/IN

VCC *

432

5
6
7
8
9
10
11

1

12131415161718

IN

IN

GND

GND *

VCC

I/O

282726

IN

I/O

I/O

I/O

25

I/O

24

I/O

23

GND *

22

I/O

21

I/O

20

I/O

19

I/O

Rev. 0776H–03/01

1

guarantee fast in-system performance. The ATF750C(L) is
a high-performance CMOS (electrically-erasable) complex
programmable logic device (CPLD) that utilizes Atmel’s
proven electrically-erasable technology.

Each of the ATF750C(L)’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi­directional I/O pins. Each flip-flop is individually config­urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.

There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
format is used to assign between four to eight product
terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

(1)

(1)

terms and flip-flops, complex state machines are easily
implemented with logic to spare.

Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu­ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip­flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.

The ATF750C(L) is a low-power device with speeds
as fast as 15 ns. The ATF750C(L) provides the optimum
low-power CPLD solution. This device significantly
reduces total system power, thereby allowing battery­powered operations.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max­imum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.

+ 0.75V DC,

CC

DC and AC Operating Conditions

All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to
be either 2.7V to 3.6V, 5V ± 5% or 5V ± 10%.

Commercial

5V Operation

Operating Temperature (Ambient) 0°C - 70°C -40°C - +85°C

V

Power Supply 5V ±=5% 5V ±=10%

CC

2

ATF750C(L)

-7.5, -10, -15

Industrial

-10, -15

Logic Options

Combinatorial Output Registered Output

Combined Terms Separate Terms

Combined Terms Separate Terms

ATF750C(L)

Clock Mux

Output Options

CLOCK

PRODUCT

TERM

CKi

CLK

PIN

CKMUX

TO

LOGIC

CELL

SELECT

3

Bus-friendly Pin-keeper Input and I/Os

All input and I/O pins on the ATF750C(L) have programma­ble “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.

This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The

Table 1. Software Compiler Mode Selection

Synario WINCUPL Pin-keeper Circuit

ATF750C V750C Disabled

ATF750C (PPK) V750CPPK Enabled

Input Diagram

INPUT

keeper circuits eliminate the need for external pull-up resis­tors and eliminate their DC power consumption.

Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.

V

CC

100K

I/O Diagram

OE

DATA

ESD

PROTECTION

CIRCUIT

V

CC

V

CC

PROGRAMMABLE

OPTION

100K

PROGRAMMABLE

OPTION

I/O

4

ATF750C(L)

ATF750C(L)

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

LI

I

LO

I

CC

(1)

I

OS

Input Load Current VIN = -0.1V to VCC + 1V 10 µA

Output Leakage
Current

= -0.1V to VCC + 0.1V 10 µA

V

OUT

Com. 125 180 mA

C-7, -10

Ind., Mil. 135 190 mA

Power Supply
Current, Standby

CC

V

= Max,

IN

Outputs Open

C-15

Com. 125 180 mA

Ind., Mil. 135 190 mA

V

= Max,

Com. 0.12 1 mA

CL-15

Ind., Mil. 0.15 2 mA

Output Short
Circuit Current

= 0.5V -120 mA

V

OUT

V

IL

V

IH

V

OL

V

OH

Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V

Input High Voltage 2.0 V

= 16 mA Com., Ind. 0.5 V

I
Output Low
Vol ta ge

Output High
Vol ta ge

VIN = VIH or VIL,
V

= Min

CC

VIN = VIH or VIL,

= Min

V

CC

OL

I

= 12 mA Mil. 0.5 V

OL

I

= 24 mA Com. 0.8 V

OL

= -4.0 mA 2.4 V

I

OH

+ 0.75 V

CC

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

Input Test Waveforms and Measurement Levels

tR, tF < 3 ns (10% to 90%)

Output Test Load

VCC

300
(390 MIL.)

390
(750 MIL.)

5

AC Waveforms, Product Term Clock

(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics, Product Term Clock

(1)

-7 -10 C/CL-15

Symbol Parameter

UnitsMin Max Min Max Min Max

t

PD

t

EA

t

ER

t

CO

t

CF

t

S

t

SF

t

H

t

P

t

W

Input or Feedback to Non-registered Output 7.5 10 15 ns

Input to Output Enable 7.5 10 15 ns

Input to Output Disable 7.5 10 15 ns

Clock to Output 3 7.5 4 10 5 12 ns

Clock to Feedback 1 5 4 7.5 5 9 ns

Input Setup Time 3 4 8/12 ns

Feedback Setup Time 3 4 7 ns

Hold Time 125ns

Clock Period 7 11 14 ns

Clock Width 3.5 5.5 7 ns

External Feedback 1/(tS + tCO)957150/41MHz

f

MAX

t

AW

t

AR

t

AP

t

SP

Internal Feedback 1/(tSF + tCF) 125 86 62 MHz

No Feedback 1/(t

) 142 90 71 MHz

P

Asynchronous Reset Width 5 10 15 ns

Asynchronous Reset Recovery Time 3 10 15 ns

Asynchronous Reset to Registered Output Reset 8 12 15 ns

Setup Time, Synchronous Preset 4 7 8 ns

Note: 1. See ordering information for valid part numbers.

6

ATF750C(L)

ATF750C(L)

AC Waveforms, Input Pin Clock

(1)

Notes: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics, Input Pin Clock

-7 -10 C/CL-15

Symbol Parameter

UnitsMin Max Min Max Min Max

t

PD

t

EA

t

ER

t

COS

t

CFS

t

SS

t

SFS

t

HS

t

PS

t

WS

f

MAXS

t

AW

t

ARS

t

AP

t

SPS

Input or Feedback to Non-registered Output 7.5 10 15 ns

Input to Output Enable 7.5 10 15 ns

Input to Output Disable 7.5 10 15 ns

Clock to Output 0 6.5 0 7 0 10 ns

Clock to Feedback 0 3.5 0 5 0 5.5 ns

Input Setup Time 4 5 8/12.5 ns

Feedback Setup Time 4 5 7 ns

Hold Time 000ns

Clock Period 7 10 12 ns

Clock Width 3.5 5 6 ns

External Feedback 1/(tSS + t

Internal Feedback 1/(t

No Feedback 1/(t

SFS

) 142 100 83 MHz

PS

)958355/44MHz

COS

+ t

) 133 100 80 MHz

CFS

Asynchronous Reset Width 5 10 15 ns

Asynchronous Reset Recovery Time 5 10 15 ns

Asynchronous Reset to Registered Output Reset 8 10 15 ns

Setup Time, Synchronous Preset 5 5/9 11 ns

7

Functional Logic Diagram ATF750C, Upper Half

8

ATF750C(L)

Functional Logic Diagram ATF750C, Lower Half

ATF750C(L)

9

Preload of Registered Outputs

The ATF750C(L)’s registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A V

Level Forced on Registered

Output Pin during Preload Cycle Select Pin State Register #0 State after Cycle Register #1 State after Cycle

level on the I/O pin will force the register

IH

V

IH

V

IL

V

IH

V

IL

Low High X

Low Low X

High X High

High X Low

high; a V

will force it low, independent of the output polar-

IL

ity. The PRELOAD state is entered by placing a 10.25V to

10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.
When the clock term is pulsed high, the data on the I/O
pins is placed into the register chosen by the select pin.

Power-up Reset

The registers in the ATF750C(L)s are designed to reset
during power-up. At a point delayed slightly from V
ing V

, all registers will be reset to the low state. The out-

RST

CC

cross-

put state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the
uncertainty of how V

actually rises in the system, the fol-

CC

lowing conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup
times must be met before driving the clock terms or
pin high, and

3. The clock pin, or signals from which clock terms are
derived, must remain stable during t

PR

.

Parameter Description Typ Max Units

t

PR

V

RST

Power-up Reset Time 600 1000 ns

Power-up Reset Voltage 3.8 4.5 V

Pin Capacitance

f = 1 MHz, T = 25°C

C

IN

C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

(1)

Typ Max Units Conditions

58 pFV

68 pFV

= 0V

IN

OUT

= 0V

10

ATF750C(L)

ATF750C(L)

Using the ATF750C’s Many Advanced Features

The ATF750C(L)’s advanced flexibility packs more usable
gates into 24 pins than any other logic device. The
ATF750C(L)s start with the popular 22V10 architecture,
and add several enhanced features:

• Selectable D- and T-type Registers

Each ATF750C(L) flip-flop can be individually configured
as either D- or T-type. Using the T-type configuration, JK
and SR flip-flops are also easily created. These options
allow more efficient product term usage.

• Selectable Asynchronous Clocks

Each of the ATF750C(L)’s flip-flops may be clocked by
its own clock product term or directly from Pin 1 (SMD
Lead 2). This removes the constraint that all registers
must use the same clock. Buried state machines,
counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock
source selection further allows mixing higher
performance pin clocking and flexible product term
clocking within one design.

• A Full Bank of Ten More Registers

The ATF750C(L) provides two flip-flops per output logic
cell for a total of 20. Each register has its own sum term,
its own reset term and its own clock term.

• Independent I/O Pin and Feedback Paths

Each I/O pin on the ATF750C(L) has a dedicated input
path. Each of the 20 registers has its own feedback
terms into the array as well. This feature, combined with
individual product terms for each I/O’s output enable,
facilitates true bi-directional I/O design.

Synchronous Preset and Asynchronous Reset

One synchronous preset line is provided for all 20 registers
in the ATF750C(L). The appropriate input signals to cause
the internal clocks to go to a high state must be received
during a synchronous preset. Appropriate setup and hold
times must be met, as shown in the switching waveform
diagram.

An individual asynchronous reset line is provided for each
of the 20 flip-flops. Both master and slave halves of the flip­flops are reset when the input signals received force the
internal resets high.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying
of the ATF750C(L) fuse patterns. Once the security fuse
is programmed, all fuses will appear programmed during
verify.

The security fuse should be programmed last, as its effect
is immediate.

11

ATF750C SUPPLY CURRENT VS.

SUPPLY VOLTAGE (T

140

120

100

80

(mA)

60

CC

I

40

20

0

4.50 4.75 5.00 5.25 5.50

SUPPLY VOLTAGE (V)

= 25°C)

A

ATF750CL SUPPLY CURRENT

VS. SUPPLY VOLTAGE ( T

160

140

120

100

80

(µA)

CC

I

60

40

20

0

4.50 4.75 5.00 5.25 5.50

SUPPLY VOLTAGE (V)

= 25°C)

A

SUPPLY CURRENT VS. FREQUENCY

160

120

80

(mA)

CC

I

40

0

0 5 10 25 50 75 100

STANDARD POWER (T

FREQUENCY (MHz)

= 25°C)

A

ATF750C/CL OUTPUT SOURCE CURRENT

VS. SUPPLY VOLTAGE (V

0

-5

-10

-15

-20

-25

(mA)

OH

I

-30

-35

-40

-45

-50

44.555.56

SUPPLY VOLTAGE (V)

= 2.4V)

OH

SUPPLY CURRENT VS. FREQUENCY

140

LOW-POWER ("L") VERSION (T

120

100

80

(mA)

60

CC

I

40

20

0

0 5 10 25 50 75 100

FREQUENCY (MHz)

= 25°C)

A

ATF750C/CL OUTPUT SOURCE CURRENT

VS. OUTPUT VOLTAGE (V

0.00

-10.00

-20.00

-30.00

-40.00

(mA)

-50.00

OH

I

-60.00

-70.00

-80.00

-90.00

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

= 5V, TA = 25°C)

CC

V

(V)

OH

12

ATF750C(L)

ATF750C(L)

A

ATF750C/CL OUTPUT SINK CURRENT

VS. SUP PL Y VOLT AG E ( V

44

43

42

41

40

39

(mA)

OL

I

38

37

36

35

34

44.555.56

SUPPLY VOLTAGE (V)

= 0.5V)

OL

ATF750C/CL OUTPUT SINK CURRENT

VS. OUTPUT VOLTAGE (V

90

80

70

60

50

(mA)

40

OL

I

30

20

10

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

= 5V, TA = 25°C)

CC

V

(V)

OL

ATF750C/CL OUTPUT SINK CURRENT

VS. OUTPUT VOLTAGE (V

140

120

100

80

(mA)

OL

60

I

40

20

0

0 0.5 1 1.5 2 2 .5 3 3.5 4 4.5 5

= 5V, TA = 25°C)

CC

(V)

V

OL

TF750C/CL INPUT CURRENT VS. INPUT VOLTAGE

= 5V,TA = 25°C)

(V

30

25

20

15

10

5

0

-5

-10

INPUT CURRENT (uA)

-15

-20

-25

00.511.522.5 33.544.555.5 6

CC

INPUT VOLTAGE (V)

ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE

= 5V,TA = 25°C)

(V

CC

WITHOUT PIN-KEEPER

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

INPUT CURRENT (uA)

0.2

0

-0.2
0 0.5 1 1 .5 2 2.5 3 3.5 4 4 .5 5 5.5 6

INPUT VOLTAGE (V)

ATF750C/CL INPUT CLAMP CURRENT

VS. INPUT VOLTAGE (V

0

-10

-20

-30

-40

-50

-60

-70

-80

INPUT CURRENT (mA)

-90

-100
0 -0.2 -0.4 -0.6 -0.8 -1

INPUT VOLTAGE (V)

= 5V,TA = 35°C)

CC

13

ATF750C(L) Ordering Information

Ext.

t

PD

(ns)

t

COS

(ns)

7.5 6.5 95 ATF750C-7JC 28J Commercial

10 7 83 ATF750C-10JC

15 10 55 ATF750C-15JC

15 10 44 ATF750CL-15JC

Note: 1. Special order only: TSSOP package requires special thermal management.

f

MAXS

(MHz) Ordering Code Package Operation Range

(0°C to 70°C)

AT F7 50 C - 1 0P C
AT F7 50 C - 1 0S C
AT F7 50 C - 1 0X C

AT F7 50 C - 1 0J I
AT F7 50 C - 1 0P I
AT F7 50 C - 1 0S I

AT F7 50 C - 1 5P C
AT F7 50 C - 1 5S C
AT F7 50 C - 1 5X C

AT F7 50 C - 1 5J I
AT F7 50 C - 1 5P I
AT F7 50 C - 1 5S I

AT F7 50 C L - 15 P C
AT F7 50 C L - 15 S C
AT F7 50 C L - 15 X C

AT F7 50 C L - 15 J I
AT F7 50 C L - 15 P I
AT F7 50 C L - 15 S I

28J
24P3
24S

(1)

24X

(1)

28J
24P3
24S

28J
24P3
24S

(1)

24X

(1)

28J
24P3
24S

28J
24P3
24S

(1)

24X

(1)

28J
24P3
24S

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Using “C” Product for Industrial

To use commercial product for industrial ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” =
10 ns “I”) and de-rate power by 30%.

Package Type

28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)

24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

24S 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

(1)

24X

14

24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP)

ATF750C(L)

Packaging Information

(

28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AB

.045

.045(1.14) X 45°

.032(.813)
.026(.660)

.050(1.27) TYP

PIN NO. 1
IDENTIFY

.300(7.62) REF SQ

1.14) X 30° - 45°

.456(11.6)

SQ

.450(11.4)

.495(12.6)

SQ

.485(12.3)

.022(.559) X 45° MAX (3X)

.012(.305)
.008(.203)

.430(10.9)

.390(9.91)
.021(.533)
.013(.330)

.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)

.180(4.57)
.165(4.19)

SQ

24P3, 24-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AF

1.27(32.3)

.200(5.06)

SEATING

PLANE

1.25(31.7)

1.100(27.94) REF

MAX

.151(3.84)
.125(3.18)

.110(2.79)
.090(2.29)

.012(.305)

.008(.203)

PIN

1

.065(1.65)
.040(1.02)

.325(8.26)
.300(7.62)

0

REF

15

.400(10.2) MAX

.090(2.29)

.005(.127)

.070(1.78)
.020(.508)

.023(.584)
.014(.356)

.266(6.76)
.250(6.35)

MAX

MIN

24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)

.020(.508)

.013(.330)

PIN 1 ID

0
8

.616(15.6)
.598(15.2)

REF

.299(7.60)
.291(7.39)

.050(1.27) BSC

.012(.305)

.003(.076)

.050(1.27)
.015(.381)

.420(10.7)
.393(9.98)

.105(2.67)
.092(2.34)

.013(.330)
.009(.229)

24X, 24-lead, 0.173" Wide, Thin Shrink Small Outline
(TSSOP)
Dimensions in Millimeters and (Inches)*

*Controlling dimension: millimeters

15

ATF750C(L)

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TEL [phone]
FAX [phone]

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Room 1219
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FAX [phone]

Japan

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Atmel Colorado Springs

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Atmel Smart Card ICs

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Fax-on-Demand

North America:
1-[phone]

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e-mail

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Web Site

http://www.atmel.com

BBS

1-[phone]

© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war­ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop­erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

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