Rainbow Electronics ATF750CL User Manual

Features

• Advanced, High-speed, Electrically-erasable Programmable Logic Device

– Superset of 22V10
– Enhanced Logic Flexibility
– Backward Compatible with ATV750B/BL and ATV750/L

• Low-power Edge-sensing “L” Option with 1 mA Standby Current

• D- or T-type Flip-flop

• Product Term or Direct Input Pin Clocking

• 7.5 ns Maximum Pin-to-pin Delay with 5V Operation

• Highest Density Programmable Logic Available in 24-pin Package

– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested

• Increased Logic Flexibility

– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops

• Enhanced Output Logic Flexibility

– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs

• Programmable Pin-keeper Circuits

• Dual-in-line and Surface Mount Package in Standard Pinouts

• Commercial and Industrial Temperature Ranges

• 20-year Data Retention

• 2000V ESD Protection

• 1000 Erase/Write Cycles

Block Diagram

High-speed
Complex
Programmable
Logic Device

ATF750C
ATF750CL

(OE PRODUCT TERMS)

12

INPUT

PINS

PROGRAMMABLE

INTERCONNECT

AND

COMBINATORIAL

LOGIC ARRAY

4TO8

PRODUCT

TERMS

(CLOCK PIN)

LOGIC

OPTION

(UP T0 20

FLIP-FLOPS)

OUTPUT

OPTION

10

I/O

PINS

Description

The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform predictable delays

(continued)

Pin Configurations

Pin Name Function

CLK Clock

IN Logic Inputs

I/O Bi-directional Buffers

GND Ground

VCC +5V Supply

Note: For PLCC, pins 1, 8, 15, and 22

can be left unconnected. For
superior performance, connect
VCC to pin 1 and GND to pins
8, 15, and 22.

DIP/SOIC/TSSOP

CLK/IN

GND

1
2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

IN

9

IN

10

IN

11

IN

12

24
23
22
21
20
19
18
17
16
15
14
13

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN

GND *

IN
IN
IN

IN
IN
IN

PLCC

ININCLK/IN

VCC *

432

5
6
7
8
9
10
11

1

12131415161718

IN

IN

GND

GND *

VCC

I/O

282726

IN

I/O

I/O

I/O

25

I/O

24

I/O

23

GND *

22

I/O

21

I/O

20

I/O

19

I/O

Rev. 0776H–03/01

1

guarantee fast in-system performance. The ATF750C(L) is
a high-performance CMOS (electrically-erasable) complex
programmable logic device (CPLD) that utilizes Atmel’s
proven electrically-erasable technology.

Each of the ATF750C(L)’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi­directional I/O pins. Each flip-flop is individually config­urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.

There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
format is used to assign between four to eight product
terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

(1)

(1)

terms and flip-flops, complex state machines are easily
implemented with logic to spare.

Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu­ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip­flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.

The ATF750C(L) is a low-power device with speeds
as fast as 15 ns. The ATF750C(L) provides the optimum
low-power CPLD solution. This device significantly
reduces total system power, thereby allowing battery­powered operations.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max­imum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.

+ 0.75V DC,

CC

DC and AC Operating Conditions

All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to
be either 2.7V to 3.6V, 5V ± 5% or 5V ± 10%.

Commercial

5V Operation

Operating Temperature (Ambient) 0°C - 70°C -40°C - +85°C

V

Power Supply 5V ±=5% 5V ±=10%

CC

2

ATF750C(L)

-7.5, -10, -15

Industrial

-10, -15

Logic Options

Combinatorial Output Registered Output

Combined Terms Separate Terms

Combined Terms Separate Terms

ATF750C(L)

Clock Mux

Output Options

CLOCK

PRODUCT

TERM

CKi

CLK

PIN

CKMUX

TO

LOGIC

CELL

SELECT

3

Bus-friendly Pin-keeper Input and I/Os

All input and I/O pins on the ATF750C(L) have programma­ble “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.

This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The

Table 1. Software Compiler Mode Selection

Synario WINCUPL Pin-keeper Circuit

ATF750C V750C Disabled

ATF750C (PPK) V750CPPK Enabled

Input Diagram

INPUT

keeper circuits eliminate the need for external pull-up resis­tors and eliminate their DC power consumption.

Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.

V

CC

100K

I/O Diagram

OE

DATA

ESD

PROTECTION

CIRCUIT

V

CC

V

CC

PROGRAMMABLE

OPTION

100K

PROGRAMMABLE

OPTION

I/O

4

ATF750C(L)

ATF750C(L)

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

LI

I

LO

I

CC

(1)

I

OS

Input Load Current VIN = -0.1V to VCC + 1V 10 µA

Output Leakage
Current

= -0.1V to VCC + 0.1V 10 µA

V

OUT

Com. 125 180 mA

C-7, -10

Ind., Mil. 135 190 mA

Power Supply
Current, Standby

CC

V

= Max,

IN

Outputs Open

C-15

Com. 125 180 mA

Ind., Mil. 135 190 mA

V

= Max,

Com. 0.12 1 mA

CL-15

Ind., Mil. 0.15 2 mA

Output Short
Circuit Current

= 0.5V -120 mA

V

OUT

V

IL

V

IH

V

OL

V

OH

Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V

Input High Voltage 2.0 V

= 16 mA Com., Ind. 0.5 V

I
Output Low
Vol ta ge

Output High
Vol ta ge

VIN = VIH or VIL,
V

= Min

CC

VIN = VIH or VIL,

= Min

V

CC

OL

I

= 12 mA Mil. 0.5 V

OL

I

= 24 mA Com. 0.8 V

OL

= -4.0 mA 2.4 V

I

OH

+ 0.75 V

CC

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

Input Test Waveforms and Measurement Levels

tR, tF < 3 ns (10% to 90%)

Output Test Load

VCC

300
(390 MIL.)

390
(750 MIL.)

5