Rainbow Electronics ATF2500CQL User Manual

Features

• High-performance, High-density, Electrically-erasable Programmable Logic Device

• Fully Connected Logic Array with 416 Product Terms

• 10 ns Maximum Pin-to-pin Delay for 5V Operation

• Low-power Edge-sensing “L” Option with <1 mA Standby Current

• 24 Flexible Output Macrocells

– 48 Flip-flops – Two per Macrocell
–72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently

• D- or T-type Flip-flops

• Product Term or Direct Input Pin Clocking

• Registered or Combinatorial Internal Feedback

• Backward Compatible with ATV2500B/BQL and ATV2500H/L Software

• Advanced Electrically-erasable Technology

– Reprogrammable
– 100% Tested

• 44-lead Surface Mount Package

ATF2500C
CPLD Family
Datasheet

Block Diagram

Description

The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully
connected logic array and flexible macrocell structure, high gate utilization is easily
obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) pro­grammable logic device (PLD) that utilizes Atmel’s proven electrically-erasable
technology.

Pin Configurations

Pin Name Function

IN Logic Inputs

CLK/IN Pin Clock and Input

I/O Bi-directional Buffers

I/O 0,2,4... “Even” I/O Buffers

I/O 1,3,5... “Odd” I/O Buffers

GND Ground

VCC +5V Supply

VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12

DIP

1

IN
IN

IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5

IN

IN

IN

IN

40
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

IN

39

IN

38

IN

37

IN

36

I/O6

35

I/O7

34

I/O8

33

I/O9

32

I/O10

31

I/O11

30

GND

29

I/O23

28

I/O22

27

I/O21

26

I/O20

25

I/O19

24

I/O18

23

IN

22

IN

21

IN

PLCC/LCC/JLCC

I/O1

I/O0

65432

7

I/O2

8

I/O3

9

I/O4

10

I/O5

11

VCC

12

VCC

13

I/O17

14

I/O16

15

I/O15

16

I/O14

17

I/O13

1819202122232425262728

INININININININ

I/O12

GNDININ

CLK/INININININ

1

4443424140

IN

I/O18

I/O6

39
38
37
36
35
34
33
32
31
30
29

I/O19

I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20

ATF2500C
ATF2500CL
ATF2500CQ
ATF2500CQL

Preliminary

Note: For ATF2500CQ and ATF2500CQL

(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required.

Rev. 0777G–12/01

1

The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out­puts of each flip-flop.

In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro­cell’s three sum terms can be combined to provide up to 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro­viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal
combinatorial feedback to the logic array.

Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip­flops may also be individually configured to have direct input pin clocking. Each output has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.

The Atmel-unique “L” low-power feature is an edge-sensing option that is now field program­mable for the ATF2500C family. The “L” feature utilizes Atmel-patented Input Transition
Detection (ITD) circuitry and is activated by selecting the “L” option from the program menu.

Using the ATF2500C Family’s Many Advanced Features

The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:

• Fully Connected Logic Array – Each array input is always available to every product
term. This makes logic placement a breeze.

• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.

• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin resources.

• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.

• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of

48. Each register has its own clock and reset terms, as well as its own sum term.

• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O’s output enable,
facilitate true bi-directional I/O design.

• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with no

speed penalty.

2

ATF2500C Family

0777G–12/01

ATF2500C Family

Power-up Reset The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed

slightly from V

crossing V

CC

depend on the polarity of the output buffer.

, all registers will be reset to the low state. The output state will

RST

This feature is critical for state as nature of reset and the uncertainty of how V

actually rises

CC

in the system, the following conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and

3. The clock pin, and any signals from which clock terms are derived, must remain stable
during t

Parameter Description Typ Max Units

t

PR

V

RST

Power-up Reset Time 600 1000 ns

Power-up Reset Voltage 3.8 4.5 V

PR

.

Level Forced on

Odd I/O Pin during

PRELOAD Cycle

V

IH/VIL

V

IH/VIL

V

IH/VIL

VIH/V

IL

0777G–12/01

Q Select Pin

State

Even/Odd

Select

Even Q1 State

after Cycle

Even Q2 State

after Cycle

Odd Q1 State

after Cycle

Odd Q2 State

after Cycle

Low Low High/Low X X X

High Low X High/Low X X

Low High X X High/Low X

High High X X X High/Low

3

Preload and Observability of Registered Outputs

The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn­chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
appropriate register high; a V
tion bit settings.

The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.

Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.
In this mode, the contents of the buried register bank will appear on the associated outputs
when the OE control signals are active.

will force it low, independent of the polarity or other configura-

IL

level on the odd I/O pins will force the

IH

Programming Software Support

Security Fuse Usage

Input and I/O Pull-ups

All family members of the ATF2500C can be designed with Atmel-Synario™ and Atmel-Win-

™

CUPL

Additionally, the ATF2500C may be programmed to perform the ATV2500H/Ls functional sub­set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In
this case, the ATF2500C becomes a direct replacement or speed upgrade for the
ATV2500H/L. The ATF2500CQ/CQL are direct replacements for the ATV2500BQ/BQL and
the AT2500H/L, including the lack of extra grounds on P4 and P26.

A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once
programmed, the outputs will read programmed during verify.

The security fuse should be programmed last, as its effect is immediate.

The security fuse also inhibits Preload and Q2 observability.

All ATF2500C family members have programmable internal input and I/O pinkeeper circuits.

The default condition, including when using the AT2500CQ/CQL family to replace the
AT2500BQ/BQL or AT2500H/L, is that the pinkeepers are not activated.

When pinkeepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states.
Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).

. ProChip™ designer support will be available Q102.

4

ATF2500C Family

0777G–12/01

Input Diagram

I/O Diagram

ATF2500C Family

Functional Logic Diagram Description

INPUT

The ATF2500C functional logic diagram describes the interconnections between the input,
feedback pins and logic cells. All interconnections are routed through the single global bus.

The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0
through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five
lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into
three sum terms, which are used as shown in the macrocell diagrams.

Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share
Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing
Preset 7.

The 14 dedicated inputs and their complements use the numbered positions in the global bus
as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2
true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by
these signals in the global bus are the six numbers in the bus diagram next to each macrocell.

Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs.

(1)

0777G–12/01

5

Functional Logic Diagram ATV2500C

Notes: 1. Pin 4 and Pin 26 are “ground” connections and are not required for PLCC, LCC and JLCC versions of ATF2500CQ or

ATF2500CQL, making them compatible with ATV2500H and ATV2500L as well as ATV2500BQ and ATV2500BQL pinouts.

2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND1 = P33 and
P34, and GND2 = P4, P26 (See Note 1, above).

6

ATF2500C Family

0777G–12/01

ATF2500C Family

Output Logic, Registered

(1)

S2 = 0 Terms in

Output ConfigurationS1 S0 D/T1 D/T2

0084Registered (Q1); Q2 FB

(1)

10124

1184Registered (Q1); D/T2 FB

Output

S3

Configuration S6 Q1 CLOCK

0 Active Low 0 CK1

1 Active High 1 CK1 • PIN1

S4 Register 1 Type S7

0D 0CK2

1T 1CK2 • PIN1

S5 Register 2 Type

0D

1T

Registered (Q1); Q2 FB

Q2 CLOCK

Output Logic, Combinatiorial

(1)

S2 = 1 Terms in

Output ConfigurationS5 S1 S0 D/T1 D/T2

X004

X0144

X104

1114

01144

(1)

(1)

(1)

Combinatorial (8 Terms);

4

Q2 FB

Combinatorial (4 Terms);
Q2 FB

Combinatorial (12 Terms);

(1)

4

Q2 FB

Combinatorial (8 Terms);

4

D/T2 FB

Combinatorial (4 Terms);
D/T2 FB

Note: 1. These four terms are shared with D/T1.

Clock Option

Note: 1. These diagrams show equivalent logic functions, not

necessarily the actual circuit implementation.

0777G–12/01

7

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Junction Temperature .............................................150°C Max

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

DC and AC Operating Conditions

Commercial Industrial Military

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not

(1)

Note: 1. Minimum voltage is -0.6V DC which may under-

(1)

(1)

implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to +7.0V for pulses of less
than 20 ns.

+ 0.75V DC

CC

Operating Temperature

V

Power Supply 5V ± 5% 5V ± 10% 5V ± 10%

CC

0°C - 70°C

(Ambient)

-40°C - 85°C
(Ambient)

Pin Capacitance

f = 1 MHz, T = 25°C

C

IN

C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

(1)

Typ Max Units Conditions

46pFV

812pFV

= 0V

IN

OUT

= 0V

Test Waveforms and Measurement Levels Output Test Load

-55°C - 125°C
(Case)

8

ATF2500C Family

0777G–12/01

ATF2500C Family

AC Waveforms

AC Waveforms

(1)

Input Pin Clock

(1)

Product Term Clock

(1)

AC Waveforms

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

0777G–12/01

Combinatorial Outputs and Feedback

9

ATF2500C DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

IL

I

LO

I

CC

Input Load Current VIN = -0.1V to VCC + 1V 10 µA

Output Leakage
Current

Power Supply
Current Standby

= -0.1V to VCC + 0.1V

V

OUT

= MAX,

V

CC

V

= GND or

IN

f = 0 MHz,

V

CC

ATF2500C

Outputs Open

I

OS

V

IL

V

IH

V

OL

V

OH

Output Short
Circuit Current

Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V

Input High Voltage 2.0 VCC + 0.75 V

Output Low
Volt age

Output High
Volt age

= 0.5V

V

OUT

VIN = VIH or VIL,
V

= 4.5V

CC

= MIN

V

CC

I

= 8 mA Com., Ind. 0.5 V

OL

IOL = 6 mA Mil. 0.5 V

I

= -100 µA VCC - 0.3 V

OH

I

= -4.0 mA 2.4

OH

Note: 1. See ICC versus frequency characterization curves.

ATF2500C AC Characteristics

Symbol Parameter

Com.

Ind., Mil.

10 µA

110 190 mA

110 210 mA

-120 mA

-10 -15

UnitsMinMaxMinMax

t

t

t

t

t

t

t

t

t

t

t

PD1

PD2

PD3

PD4

EA1

ER1

EA2

ER2

AW

AP

APF

Input to Non-registered Output 10 15 ns

Feedback to Non-registered Output 10 15 ns

Input to Non-registered Feedback 6 11 ns

Feedback to Non-registered Feedback 6 11 ns

Input to Output Enable 10 15 ns

Input to Output Disable 10 15 ns

Feedback to Output Enable 10 15 ns

Feedback to Output Disable 10 15 ns

Asynchronous Reset Width 4 8 ns

Asynchronous Reset to Registered Output 13 18 ns

Asynchronous Reset to Registered Feedback 10 15 ns

10

ATF2500C

0777G–12/01

ATF2500C Register AC Characteristics, Input Pin Clock

-10 -15

Symbol Parameter

t

COS

t

CFS

t

SIS

t

SFS

t

HS

t

WS

t

PS

Clock to Output 5.5 10 ns

Clock to Feedback 0 2 0 5 ns

Input Setup Time 2 9 ns

Feedback Setup Time 2 9 ns

Hold Time 0 0 ns

Clock Width 3 6 ns

Clock Period 8 12 ns

External Feedback 1/(t

F

MAXS

Internal Feedback 1/(t

No Feedback 1/(tPS)11083MHz

SIS

SFS

+ t

)7552MHz

COS

+ t

)10071MHz

CFS

Min Max Min Max

ATF2500C

Units

t

ARS

Asynchronous Reset/Preset Recovery Time 5 12 ns

ATF2500C Register AC Characteristics, Product Term Clock

-10 -15

Symbol Parameter

t

COA

t

CFA

t

SIA

t

SFA

t

HA

t

WA

t

PA

F

t

ARA

MAXA

Clock to Output 10 15 ns

Clock to Feedback 2 5 5 12 ns

Input Setup Time 2 5 ns

Feedback Setup Time 2 5 ns

Hold Time 1 5 ns

Clock Width 3 7.5 ns

Clock Period 9 15 ns

External Feedback 1/(t

Internal Feedback 1/(t

No Feedback 1/(t

PS

+ t

SIA

SFA

)75.550MHz

COA

+ t

)10058MHz

CFA

)10066MHz

Asynchronous Reset/Preset Recovery Time 2 8 ns

UnitsMin Max Min Max

0777G–12/01

11

STAND-BY ICC VS.

4.5

SUPPLY VOLTAGE (T

4.0

3.5

3.0

2.5

(µA)

2.0

CC

I

1.5

1.0

0.5

0.0

4.5 4.8 5.0 5.3 5.5

TBD

SUPPLY VOLTAGE (V)

= 25°C)

A

NORMALIZED ICC VS. TE MP

1.4

1.2

1.0

0.8

0.6

NORMALIZED Icc

0.4

-40.0 0.0 25.0 75.0

TBD

TEMPERATURE (C)

SUPPLY CURRENT VS.

140.000

120.000

100.000

80.000

(mA)

CC

60.000

I

40.000

20.000

INPUT FREQUENCY (V

0.000

0.0 0.5 2. 5 5.0 7. 5 10. 0 25.0 37.5 50. 0

FREQUENCY (MHz)

= 5.0V, TA = 25°C)

CC

TBD

OUTPUT SOURCE CURRENT VS.

0

SUPPLY VOLTAGE (V

-10

-20

(mA)

-30

OH

I

-40

TBD

-50

4.0 4.5 5.0 5.5 6.0

SUPPLY VOLTAGE (V)

= 2.4V)

OH

SUPPLY CURRENT VS.

1.000

INPUT FREQUENCY (V

0.800

0.600

(mA)

0.400

CC

I

0.200

0.000

0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0

FREQUENCY (MHz)

= 5.0V, TA = 25°C)

CC

TBD

OUTPUT SOURCE CURRENT VS.

OUTP UT VOL TAGE (V

0.0

-10.0

-20.0

-30.0

-40.0

(mA)

-50.0

OH

I

-60.0

-70.0

-80.0

-90.0

0.00 0.50 1. 00 1.50 2. 00 2.50 3.00 3. 50 4.00 4. 50 5 .00

= 5.0V, TA = 25°C)

CC

TBD

V

(V)

OH

OUTPUT SINK CURRENT VS.

1

1

1

0

Iol (mA)

0

0

4.0 4.5 5.0 5. 5 6.0

12

SUPPLY VOLTAGE (V

TBD

SUPPLY VOLTAGE (V)

ATF2500C

= 0.5V)

OL

OUTPUT SINK CURRENT VS.

140.0

120.0

100.0

80.0

(mA)

60.0

OL

I

40.0

20.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT VOLTAGE (V

SUPPLY VOLTAGE (V)

= 5.0V, TA = 25°C)

CC

TBD

0777G–12/01