• Zero Power – 25 µA Maximum Standby Power (Input Transition Detection)
• CMOS and TTL Compatible Inputs and Outputs
• Advanced Electrically-erasableTechnology
– Reprogrammable
– 100% Tested
• Latch Feature Holds Inputs to Previous Logic State
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Standard Pinouts
• PCI Compliant
Highperformance
EE PLD
Block Diagram
Description
The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel’s proven electrically-erasable
(continued)
Pin Configurations
All Pinouts Top View
Pin NameFunction
CLKClock
INLogic Inputs
I/OBi-directional Buffers
VCC+5V Supply
PLCC
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP
24
VCC
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
IN
ATF22V10CZ
ATF22V10CQZ
Note:For PLCC, P1, P8, P15 and P22 can be left
unconnected. For superior performance, connect VCC to pin 1 and GND to 8, 15, and 22.
CLK/IN
GND
DIP/SOIC
1
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
24
VCC
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
IN
Rev. 0778H–03/01
1
Flash memory technology. Speeds down to 12 ns with zero
standby power dissipation are offered. All speed ranges
are specified over the full 5V ±10% range for industrial temperature ranges; 5V ±5% for commercial range 5-volt
devices. The ATF22V10CZ/CQZ provides a low voltage
and edge-sensing “zero” power CMOS PLD solution with
“zero” standby power (5 µA typical). The
ATF22V10CZ/CQZ provides a “zero” power CMOS PLD
solution with 5V operating voltages, powering down automatically to the zero power-mode through Atmel’s patented
Input Transition Detection (ITD) circuitry when the device is
idle, offering “zero” (25 µA worst case) standby power. This
feature allows the user to manage total system power to
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
(1)
(1)
meet specific application requirements and enhance reliability. Pin “keeper” circuits on input and output pins eliminate static power consumed by pull-up resistors. The
“CQZ” combines the low high-frequency I
of the “Q”
CC
design with the “Z” feature.
The ATF22V10CZ/CQZ incorporates a superset of the
generic architectures, which allows direct replacement of
the 22V10 family and most 24-pin combinatorial PLDs. Ten
outputs are each allocated 8 to 16 product terms. Three
different modes of operation, configured automatically
with software, allow highly complex logic functions to be
realized.
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:1.Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.
+ 0.75V DC,
CC
DC and AC Operating Conditions
CommercialIndustrial
Operating Temperature (Ambient)0°C - 70°C-40°C - 85°C
V
Power Supply5V ± 5%5V ± 10%
CC
Compiler Mode Selection
PAL Mode
(5828 Fuses)
SynarioATF22V10C (DIP)
ATF22V10C (PLCC)
WINCUPLP22V10
P22V10LCC
GAL Mode
(5892 Fuses)
ATF22V10C DIP (UES)
ATF22V10C PLCC (UES)
G22V10
G22V10LCC
2
ATF22V10C(Q)Z
ATF22V10C(Q)Z
Functional Logic Diagram Description
The Functional Logic Diagram describes the
ATF22V10CZ/CQZ architecture.
The ATF22V10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four
output configurations: active high/low, registered/combinatorial output.The universal architecture of the
ATF22V10CZ/CQZ can be programmed to emulate most
24-pin PAL devices.
DC Characteristics
SymbolParameterConditionMinTypMaxUnits
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the
ATF22V10CZ/CQZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of the state of the security
fuse.
I
IL
I
IH
Input or I/O Low
Leakage Current
Input or I/O High
Leakage Current
0 ≤ V
3.5 ≤ V
IN
≤ V
≤ V
IN
(Max)
IL
CC
-10µA
10
CZ-12, 15Com90150mA
= Max
V
I
CC
Clocked Power
Supply Current
CC
Outputs Open,
f = 15 MHz
CZ-15Ind90180mA
CQZ-20Com4060mA
CQZ-20Ind4080mA
CZ-12, 15Com525
V
= Max
I
SB
Power Supply Current,
Standby
CC
= MAX
V
IN
Outputs Open
CZ-15Ind550
CQZ-20Com525µA
CQZ-20Ind550
(1)
I
OS
V
IL
V
IH
V
OL
V
OH
Output Short Circuit
Current
= 0.5V-130mA
V
OUT
Input Low Voltage-0.50.8V
Input High Voltage2.0VCC + 0.75V
= VIH or V
V
Output Low Voltage
Output High Voltage
IN
VCC = Min,
= 16 mA
I
OL
= VIH or V
V
IN
V
= Min,
CCIO
= -4.0 mA
I
OH
IL
0.5V
IL
2.4V
Notes:1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
µA
µA
µA
µA
3
AC Waveforms
REG. FEEDBACK
SYNCH. PRESET
ASYNCH. RESET
INPUTS, I/O
CP
tS
tH
tWtW
tP
tAW
tAR
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
AC Characteristics
SymbolParameter
t
PD
t
CF
t
CO
t
S
t
H
t
W
f
MAX
t
EA
t
ER
t
PZX
t
PXZ
t
AP
Input or Feedback to Non-registered Output312315320 ns
Note:1. See ordering information for valid part numbers.
4
ATF22V10C(Q)Z
101014ns
ATF22V10C(Q)Z
Input Test Waveforms and
Output Test Loads
Measurement Levels
Note:Similar competitors devices are specified with slightly
different loads. These load differences may affect output
signals’ delay and slew rate. Atmel devices are tested
with sufficient margins to meet compatible device specification conditions.
Pin Capacitance
f = 1 MHz, T = 25C
C
IN
C
I/O
Note:1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF22V10CZ/CQZ are designed to
reset during power-up. At a point delayed slightly from V
crossing V
RST
The output state will depend on the polarity of the buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
following conditions are required:
1.The V
CC
below 0.7V.
2.The clock must remain stable during T
3.After T
PR
must be met before driving the clock pin high.
Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can
be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
(1)
TypMaxUnitsConditions
810 pFV
810 pFV
, all registers will be reset to the low state.
actually rises in the system, the
CC
rise must be monotonic and start
.
PR
occurs, all input and feedback setup times
= 0V; f = 1.0 MHz
IN
= 0V; f = 1.0 MHz
OUT
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22V10CZ/CQZ fuse patterns. Once pro-
CC
grammed, fuse verify and preload are inhibited. However,
the 64-bit User Signature remains accessible. The security
fuse should be programmed last, as its effect is immediate.
Programming/Erasing
Programming/erasing is performed using standard
PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming.
V
R
ST
POWER
t
PR
REGISTERED
OUTPUTS
CLOCK
t
S
t
W
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
ParameterDescriptionTypMaxUnits
T
PR
V
RST
Power-up
Reset Time
Power-up
Reset Voltage
6001000ns
3.84.5V
5
Input and I/O Pull-ups
All ATF22V10CZ/CQZ family members have internal input
and I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their
last driven state. This ensures that all logic array inputs and
Input Diagram
device outputs are at known states. These are relatively
weak active circuits that can be easily overridden by TTLcompatible drivers (see input and I/O diagrams below).
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0778H–03/01/xM
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