– Pin-keeper Feature Holds Inputs and I/Os to Previous Logic States
– PCI Compliant
• High-reliability EE Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
• Commercial and Industrial Temperature Ranges
AT20V8C Family
Highperformance
EE PLD
ATF20V8C
Pin Configurations
All Pinouts Top View
Pin NameFunction
CLKClock
INLogic Inputs
I/OBi-directional Buffers
OE
NCNo Internal Connection
VCC+5V Supply
PDPower-down
(1)
PD/IN
NC
5
6
IN
7
IN
8
9
IN
10
IN
11
IN
Output Enable
PLCC
ININCLK/INNCVCCINI/O
432
1
282726
12131415161718
IN
IN
GND
NC
IN
OE/IN
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
CLK/IN
(1)
PD/
GND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
CLK/IN
(1)
PD/IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
DIP/SOIC
1
2
IN
3
IN
4
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
TSSOP
ATF20V8CQ
VCC
24
IN
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
IN
14
OE/IN
13
24
VCC
23
IN
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
IN
13
OE/IN
ATF20V8CQZ
Note:1. PD on C and CQ only.
Rev. 0408H–04/01
1
Block Diagram
Description
The ATF20V8C is a high-performance CMOS (electrically
erasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically erasable technology. Speeds
down to 5 ns and power dissipation as low as 10 µA are
offered. All speed ranges are specified over the full 5V ±
10% range for industrial temperature ranges, and 5V ± 5%
for commercial ranges.
The ATF20V8C(Q) provides a high-speed CMOS PLD
solution with maximum pin-to-pin delay of 5 ns. The
ATF20V8C(Q) also has a user-controlled power-down feature, offering “zero” standby power (10 µA typical). The
user-controlled power-down feature allows the user to
manage total system power to meet specific application
requirements and enhance reliability without sacrificing
speed.
The ATF20V8CQZ provides the zero power CMOS PLD
solution, with “zero” standby power (10 µA typical). The
device powers down automatically through Atmel’s patented Input Transition Detection (ITD) circuitry to the “zero”
standby power mode when all inputs are idle.
Pin “keeper” circuits on input and output pins reduce static
power consumed by pull-ups.
The ATF20V8C(Q)(Z) is the industry-standard 20V8 architecture. Eight outputs are each allocated eight product
terms. Three different modes of operation, configured automatically with software, allow highly complex logic
functions to be realized.
Power-up Reset
uncertainty of how V
lowing conditions are required:
1. The V
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during t
rise must be monotonic,
CC
actually rises in the system, the fol-
CC
.
PR
Preload of Registered Outputs
The ATF20V8C registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
The registers in the ATF20V8Cs are designed to reset during power-up. At a point delayed slightly from V
, all registers will be reset to the low state. As a result,
V
RST
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
2
ATF20V8C Family
crossing
CC
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
0408H–04/01
ATF20V8C Family
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8C’s fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Input Diagram
INPUT
Logic data book section titled, “CMOS PLD Programming
Hardware and Software Support.”
Input and I/O Pull-ups
All ATF20V8C family members have internal input and I/O
“pin-keeper” circuits. Therefore, whenever inputs or I/Os
are not being driven externally, they will maintain their last
driven state. This ensures that all logic array inputs and
device outputs are at known states. These are relatively
weak active circuits that can be easily overridden by TTLcompatible drivers (see input and I/O diagrams below).
V
CC
100K
I/O Diagram
OE
DATA
INPUT
ESD
PROTECTION
CIRCUIT
V
CC
V
CC
I/O
100K
0408H–04/01
3
Functional Logic Diagram Description
The logic option and functional diagrams describe the
ATF20V8C architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output or dedicated input.
The ATF20V8C’s macrocell can be configured in one of
three different modes. Each mode makes the ATF20V8Cs
look like a different device. The ATF20V8Cs can be a registered output, combinatorial I/O, combinatorial output or
dedicated input. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The determining factors would be the usage of register versus
combinatorial outputs and dedicated outputs versus output
with output enable control.
The ATF20V8Cs have a user-controlled power-down pin,
which, when active, allows the user to place the device into
operate at high speed. Maximum pin-to-pin delays of 5 ns
are offered. Static power loss due to pull-up resistors is
eliminated by using input and output pin “keeper” circuits
that hold pins to their previous logic levels when idle.
The universal architecture of the ATF20V8Cs can be programmed to emulate many 24-pin PAL devices. The user
can download the subset device JEDEC programming file
to the PLD programmer and the ATF20V8Cs can be configured to act like the chosen device.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the contents the ATF20V8Cs.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision or date. The User Signature is accessible
regardless of the state of the security fuse.
a “zero” standby power-down mode. The device can also
Compiler Mode Selection
RegisteredComplexSimpleAuto Select
ABEL, Atmel-ABELP20V8RP20V8CP20V8P20V8
CUPLG20V8MSG20V8MAG20V8G20V8A
LOG/iCGAL20V8_R
(1)
GAL20V8_C7
(1)
GAL20V8_C8
(1)
GAL20V8
OrCAD-PLD“Registered”“Complex”“Simple”GAL20V8
PLDesignerP20V8P20V8P20V8P20V8
Tango-PLDG20V8G20V8G20V8G20V8
Note:1. Only applicable for version 3.4 or lower.
4
ATF20V8C Family
0408H–04/01
Registered Mode
PAL Device Emulation/PAL Replacement
The registered mode is used if one or more registers are
required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a
registered output or I/O, the output is enabled by the OE
pin, and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a
product term, and seven product terms are allocated to the
Registered Mode Operation
ATF20V8C Family
sum term. When the macrocell is configured as an input,
the output enable is permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
20R8 20RP8
20R6 20RP6
20R4 20RP4
0408H–04/01
5
Registered Mode Logic Diagram
6
ATF20V8C Family
0408H–04/01
Complex Mode
PAL Device Emulation/PAL Replacement
In the Complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the
array. Pins 13 through 18 have pin feedback paths back to
the AND-array, which makes full I/O capability possible.
Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each
macrocell has seven product terms going to the sum term
and one product term enabling the output.
Complex Mode Operation
ATF20V8C Family
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
20L8
20H8
20P8
Simple Mode
PAL Device Emulation/PAL Replacement
In the Simple Mode, eight product terms are allocated to
the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with
pin feedback to the AND-array. Pins 1 and 11 are regular
inputs.
Simple Mode Option
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can
be emulated using this mode:
14L8 14H8 14P8
16L6 18H6 16P6
18L4 18H4 18P4
20L2 20H2 20P2
0408H–04/01
7
Complex Mode Logic Diagram
8
ATF20V8C Family
0408H–04/01
Simple Mode Logic Diagram
ATF20V8C Family
0408H–04/01
9
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
during Programming .....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
(1)
(1)
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V
+ 0.75V DC, which
CC
may overshoot to 7.0V for pulses of less than
20 ns.
DC and AC Operating Conditions
CommercialIndustrial
Operating Temperature (Ambient)0°C - 70°C-40°C - 85°C
V
Power Supply5V=± 5%5V=± 10%
CC
ParameterDescriptionTypMaxUnits
t
PR
V
RST
Power-up Reset Time6001,000ns
Power-up Reset Voltage3.84.5V
10
ATF20V8C Family
0408H–04/01
ATF20V8C Family
Input Test Waveforms and
Output Test Loads
Measurement Levels
Commercial
tR, tF < 1.5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C
C
IN
C
OUT
Note:1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
TypMaxUnitsConditions
58 pFV
68 pFV
IN
OUT
= 0V
= 0V
0408H–04/01
11
ATF20V8C DC Characteristics
VCC = 5.0V and TA = 25°C
SymbolParameterConditionMinTypMaxUnits
I
I
I
I
IL
IH
CC
CC2
Input or I/O Low
Leakage Current
Input or I/O High
Leakage Current
Power Su ppl y
Current, Standby
Clocked Power
Supply Current
0 ≤=VIN ≤=VIL (Max)-35-100µA
3.5 ≤=VIN ≤=V
CC
10µA
C-5Com.6090mA
C-5Ind.60100mA
C-7Com.6090mA
V
= Max,
CC
V
= Max,
IN
Outputs Open
C-7Ind.60100mA
C-10Com.6080mA
C-10Ind.6090mA
C-15Com.6080mA
C-15Ind.6090mA
C-5Com.70110mA
C-5Ind.70125mA
C-7Com.70110mA
= Max,
V
CC
C-7Ind.70125mA
Outputs Open,
f = 15 MHz
C-10Com.6090mA
C-10Ind.60105mA
C-15Com.6090mA
C-15Ind.60105mA
(1)
IOS
Output Short
V
= 0.5V-130mA
OUT
Circuit Current
V
IL
V
IH
V
OL
V
OH
Input Low Voltage-0.50.8V
Input High Voltage2.0VCC + 0.75V
= VIH or VIL,
V
Output Low Voltage
V
IN
CC
= Min
Output High VoltageVIN = VIH or VIL,
= Min
V
CC
IOL = 24 mA
= 16 mA 0.5V
I
OL
I
= -4.0 mA2.4V
OH
Com.,
Ind.
0.5V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. All values are at V
and TA=25°C.
CC
3. Shaded area indicates preliminary data.
12
ATF20V8C
0408H–04/01
ATF20V8C
AC Waveforms
(1)
Note:1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
ATF20V8C Family AC Characteristics
(1)
C-5C-7C-10C-15
SymbolParameter
t
PD
Input or Feedback to
Non-registered Output
8 outputs switching
1 output switching710ns
MinMaxMinMaxMinMaxMinMax
3537.5310315 ns
Units
t
CF
t
CO
t
S
t
H
t
P
t
W
Clock to Feedback3368ns
Clock to Output242527210ns
Input or Feedback Setup Time357.512ns
Hold Time0000ns
Clock Period681216ns
Clock Width3468ns
External Feedback 1/(tS + tCO)1431006845MHz
f
t
t
t
t
MAX
EA
ER
PZX
PXZ
Internal Feedback 1/(t
No Feedback 1/(t
Input to Output Enable – Product Term3639310315ns
Input to Output Disable – Product Term2629210215ns
OE pin to Output Enable2526210215ns
OE pin to Output Disable1.551.561.5101.515ns
+ tCF)1671257450MHz
S
)71671258362MHz
P
Notes: 1. See ordering information for valid part numbers and speed grades.
To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0408H–04/01/xM
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