Rainbow Electronics ATF20V8BQL User Manual

Features

• Industry-standard Architecture

– Emulates Many 24-pin PALs
– Low-cost Easy-to-use Software Tools

• High-speed Electrically-erasable Programmable Logic Devices

– 7.5 ns Maximum Pin-to-pin Delay

• Several Power Saving Options

Device ICC, Standby ICC, Active

ATF20V8B 50 mA 55 mA

ATF20V8BQ 35 mA 40 mA

®

High-

ATF20V8BQL 5 mA 20 mA

• CMOS and TTL Compatible Inputs and Outputs

• Input and I/O Pull-up Resistors

• Advanced Flash Technology

– Reprogrammable
– 100% Tested

• High-reliability CMOS Process

– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity

• Commercial and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Packages in Standard Pinouts

• PCI-Compliant

Block Diagram

TSSOP

Pin Configurations

All Pinouts Top View

Pin Name Function

CLK Clock

I Logic Inputs

I/O Bi-directional Buffers

OE Output Enable

* No Internal Connection

VCC +5V Supply

CLK/IN

GND

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

DIP/SOIC

1
2
3
4
5
6
7
8
9
10
11
12

CLK/IN

GND

1
2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

IN

9

IN

10

IN

11

IN

12

24

VCC

23

IN

22

I/O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

IN

13

OE/IN

24
23
22
21
20
19
18
17
16
15
14
13

5

IN

6

IN

7

IN

8

*

9

IN

10

IN

11

IN

VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN

PLCC

ININCLK/IN*VCCINI/O

432

1

282726

12131415161718

*

IN

IN

IN

GND

OE/IN

performance
EE PLD

ATF20V8B
ATF20V8BQ
ATF20V8BQL

I/O

25

I/O

24

I/O

23

*

22

I/O

21

I/O

20

I/O

19

I/O

Rev. 0407H–04/01

1

Description

The ATF20V8B is a high-performance CMOS (electrically­erasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technol­ogy. Speeds down to 7.5 ns and power dissipation as low
as 10 mA are offered. All speed ranges are specified over
the full 5V
and 5V

± 10% range for industrial temperature ranges,

± 5% for commercial temperature ranges.

Several low-power options allow selection of the best solu­tion for various types of power-limited applications. Each of

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

(1)

(1)

these options significantly reduces total system power and
enhances system reliability.

The ATF20V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 20R8
family and most 24-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft­ware, allow highly complex logic functions to be realized.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Note: 1. Minimum voltage is -0.6V DC which may under-

shoot to -2.0V for pulses of less than 20 ns.Maxi­mum output pin voltage is V
may overshoot to 7.0V for pulses of less than 20
ns.

+ 0.75V DC which

CC

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C

V

Power Supply 5V=± 5% 5V=± 10%

CC

2

ATF20V8B(Q)(L)

ATF20V8B(Q)(L)

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

IL

Input or I/O Low
Leakage Current

≤=VIL(Max) -35 -100 µA

0 ≤=V

IN

I

I

I

IH

CC

CC2

Input or I/O High
Leakage Current

Power Supp ly
Current, Standby

Clocked Power
Supply Current

= Max,

CC

= Max,

IN

IN

≤=V

CC

3.5 ≤=V

V
V
Outputs Open

= Max,

V

CC

Outputs Open,
f = 15 MHz

10 µA

Com. 60 90 mA

B-7, -10

Ind. 60 100 mA

B-15 Com. 60 80 mA

B-15 Ind. 60 90 mA

B-25 Com. 60 80 mA

B-25 Ind. 60 90 mA

BQ-10 Com. 35 55 mA

BQL-15 Com. 5 10 mA

BQL-15 Ind. 5 15 mA

BQL-25 Com. 5 10 mA

BQL-25 Ind. 5 15 mA

Com. 80 110 mA

B-7, -10

Ind. 80 125 mA

B-15 Com. 60 90 mA

B-15 Ind. 60 105 mA

B-25 Com. 60 90 mA

B-25 Ind. 60 105 mA

BQ-10 Com. 40 55 mA

BQL-15 Com. 20 35 mA

BQL-15 Ind. 20 40 mA

BQL-25 Com. 20 35 mA

BQL-25 Ind. 20 40 mA

IOS

V

IL

V

IH

V

OL

V

OH

(1)

Output Short
Circuit Current

Input Low Voltage -0.5 0.8 V

Input High Voltage 2.0 VCC + 0.75 V

Output Low Voltage

Output High Voltage

V

= 0.5V -130 mA

OUT

= VIH or VIL,

V

IN

= Min

V

CC

= VIH or VIL,

V

IN

= Min

V

CC

= 24 mA

I

OL

= 16 mA 0.5 V

I

OL

= -4.0 mA 2.4 V

I

OH

Com.,
Ind.

0.5 V

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

2. Shaded parts are obsolete with a last time buy date of 19 August 1999.

3

AC Waveforms

(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics

(1)

-7 -10 -15

Symbol Parameter

t

PD

t

CF

t

CO

t

S

t

H

t

P

t

W

Input or Feedback to
Non-Registered Output

Clock to Feedback 3 6 8 10 ns

Clock to Output 25272102 12 ns

Input or Feedback
Setup Time

Hold Time 0000 ns

Clock Period 8 12 16 24 ns

Clock Width 46812 ns

8 outputs switching 3 7.5 3 10 3 15

1 output switching 7 ns

57.512

External Feedback 1/(tS + tCO) 100 68 45 37 MHz

f

MAX

Internal Feedback 1/(t

+ tCF) 125 74 50 40 MHz

S

No Feedback 1/(tP) 125 83 62 41 MHz

t

t

t

t

EA

ER

PZX

PXZ

Input to Output Enable — Product Term 3 9 3 10 3 15 3 20 ns

Input to Output Disable —Product Term 2 9 2 10 2 15 2 20 ns

OE pin to Output Enable 2 6 2 10 2 15 2 20 ns

OE pin to Output Disable 1.5 6 1.5 10 1.5 15 1.5 20 ns

Note: 1. See ordering information for valid part numbers and speed grades.

2. Shaded parts are obsolete with a last time buy data of of 19 August 1999.

-25

Min Max

UnitsMin Max Min Max Min Max

3 25 ns

15 ns

4

ATF20V8B(Q)(L)

ATF20V8B(Q)(L)

Input Test Waveforms and Measurement Levels

Output Test Loads

Commercial

tR, tF < 5 ns (10% to 90%)

Pin Capacitance

f = 1 MHz, T = 25°C

C

IN

C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

(1)

Typ Max Units Conditions

58 pF V

68 pF V

Power-up Reset

The registers in the ATF20V8Bs are designed to reset dur-

.

crossing

CC

Parameter Description Typ Max Units

t

PR

V

RST

Power-up Reset Time 600 1,000 ns

Power-up Reset Voltage 3.8 4.5 V

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.

The security fuse should be programmed last, as its effect
is immediate.

ing power-up. At a point delayed slightly from V

, all registers will be reset to the low state. As a result,

V

RST

the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the
uncertainty of how V

actually rises in the system, the fol-

CC

lowing conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and

3. The clock must remain stable during t

PR

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.

IN

OUT

= 0V

= 0V

Electronic Signature Word

There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.

Programming/Erasing

Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”

5

Input and I/O Pull-ups

All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V
ensures that all logic array inputs are at known states.

. This

CC

These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).

Input Diagram I/O Diagram

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.

The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a dif­ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter­mining factors would be the usage of register versus com­binatorial outputs and dedicated outputs versus outputs
with output enable control.

The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural

subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.

Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF20V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessi­ble regardless of the state of the security fuse.

6

ATF20V8B(Q)(L)