– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• PCI-Compliant
Block Diagram
TSSOP
Pin Configurations
All Pinouts Top View
Pin NameFunction
CLKClock
ILogic Inputs
I/OBi-directional Buffers
OEOutput Enable
*No Internal Connection
VCC+5V Supply
CLK/IN
GND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
CLK/IN
GND
1
2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
24
VCC
23
IN
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
IN
13
OE/IN
24
23
22
21
20
19
18
17
16
15
14
13
5
IN
6
IN
7
IN
8
*
9
IN
10
IN
11
IN
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
PLCC
ININCLK/IN*VCCINI/O
432
1
282726
12131415161718
*
IN
IN
IN
GND
OE/IN
performance
EE PLD
ATF20V8B
ATF20V8BQ
ATF20V8BQL
I/O
25
I/O
24
I/O
23
*
22
I/O
21
I/O
20
I/O
19
I/O
Rev. 0407H–04/01
1
Description
The ATF20V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technology. Speeds down to 7.5 ns and power dissipation as low
as 10 mA are offered. All speed ranges are specified over
the full 5V
and 5V
± 10% range for industrial temperature ranges,
± 5% for commercial temperature ranges.
Several low-power options allow selection of the best solution for various types of power-limited applications. Each of
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
(1)
(1)
these options significantly reduces total system power and
enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 20R8
family and most 24-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:1.Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is V
may overshoot to 7.0V for pulses of less than 20
ns.
+ 0.75V DC which
CC
DC and AC Operating Conditions
CommercialIndustrial
Operating Temperature (Ambient)0°C - 70°C-40°C - 85°C
V
Power Supply5V=± 5%5V=± 10%
CC
2
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
DC Characteristics
SymbolParameterConditionMinTypMaxUnits
I
IL
Input or I/O Low
Leakage Current
≤=VIL(Max)-35-100µA
0 ≤=V
IN
I
I
I
IH
CC
CC2
Input or I/O High
Leakage Current
Power Supp ly
Current, Standby
Clocked Power
Supply Current
= Max,
CC
= Max,
IN
IN
≤=V
CC
3.5 ≤=V
V
V
Outputs Open
= Max,
V
CC
Outputs Open,
f = 15 MHz
10µA
Com.6090mA
B-7, -10
Ind.60100mA
B-15Com.6080mA
B-15Ind.6090mA
B-25Com.6080mA
B-25Ind.6090mA
BQ-10Com.3555mA
BQL-15Com.510mA
BQL-15Ind.515mA
BQL-25Com.510mA
BQL-25Ind.515mA
Com.80110mA
B-7, -10
Ind.80125mA
B-15Com.6090mA
B-15Ind.60105mA
B-25Com.6090mA
B-25Ind.60105mA
BQ-10Com.4055mA
BQL-15Com.2035mA
BQL-15Ind.2040mA
BQL-25Com.2035mA
BQL-25Ind.2040mA
IOS
V
IL
V
IH
V
OL
V
OH
(1)
Output Short
Circuit Current
Input Low Voltage-0.50.8V
Input High Voltage2.0VCC + 0.75V
Output Low Voltage
Output High Voltage
V
= 0.5V-130mA
OUT
= VIH or VIL,
V
IN
= Min
V
CC
= VIH or VIL,
V
IN
= Min
V
CC
= 24 mA
I
OL
= 16 mA 0.5V
I
OL
= -4.0 mA2.4V
I
OH
Com.,
Ind.
0.5V
Notes:1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
3
AC Waveforms
(1)
Note:1.Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics
(1)
-7-10-15
SymbolParameter
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Input or Feedback to
Non-Registered Output
Clock to Feedback36810ns
Clock to Output2527210212ns
Input or Feedback
Setup Time
Hold Time0000ns
Clock Period8121624ns
Clock Width46812ns
8 outputs switching37.5310315
1 output switching7ns
57.512
External Feedback 1/(tS + tCO)100684537MHz
f
MAX
Internal Feedback 1/(t
+ tCF)125745040MHz
S
No Feedback 1/(tP)125836241MHz
t
t
t
t
EA
ER
PZX
PXZ
Input to Output Enable — Product Term39310315320ns
Input to Output Disable —Product Term29210215220ns
OE pin to Output Enable26210215220ns
OE pin to Output Disable1.561.5101.5151.520ns
Note:1.See ordering information for valid part numbers and speed grades.
2.Shaded parts are obsolete with a last time buy data of of 19 August 1999.
-25
MinMax
UnitsMinMaxMinMaxMinMax
325 ns
15ns
4
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Input Test Waveforms and
Measurement Levels
Output Test Loads
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C
C
IN
C
OUT
Note:1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
TypMaxUnitsConditions
58 pFV
68 pFV
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
.
crossing
CC
ParameterDescriptionTypMaxUnits
t
PR
V
RST
Power-up Reset Time6001,000ns
Power-up Reset Voltage3.84.5V
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
ing power-up. At a point delayed slightly from V
, all registers will be reset to the low state. As a result,
V
RST
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
actually rises in the system, the fol-
CC
lowing conditions are required:
1.The V
rise must be monotonic,
CC
2.After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3.The clock must remain stable during t
PR
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
IN
OUT
= 0V
= 0V
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
5
Input and I/O Pull-ups
All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V
ensures that all logic array inputs are at known states.
. This
CC
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
Input DiagramI/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a different device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs
with output enable control.
The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF20V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessible regardless of the state of the security fuse.
6
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
Compiler Mode Selection
RegisteredComplexSimpleAuto Select
ABEL, Atmel-ABELP20V8RP20V8CP20V8P20V8
CUPLG20V8MSG20V8MAG20V8G20V8A
LOG/iCGAL20V8_R
OrCAD-PLD“Registered”“Complex”“Simple”GAL20V8
PLDesignerP20V8P20V8P20V8P20V8
Tango-PLDG20V8G20V8G20V8G20V8
Note:1. Only applicable for version 3.4 or lower.
(1)
GAL20V8_C7
ATF20V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered
mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE
register is clocked by the CLK pin. Eight product terms are
allocated to the sum term. For a combinatorial output or
I/O, the output enable is controlled by a product term, and
seven product terms are allocated to the sum term. When
pin, and the
(1)
GAL20V8_C8
(1)
GAL20V8
the macrocell is configured as an input, the output enable is
permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
20R8 20RP8
20R6 20RP6
20R4 20RP4
Registered Mode Operation
7
Registered Mode Logic Diagram
8
ATF20V8B(Q)(L)
ATF20V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex
Mode, combinatorial output and I/O functions are possible.
Pins 1 and 11 are regular inputs to the array. Pins 13
through 18 have pin feedback paths back to the AND-array,
which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have
input capability. In this mode, each macrocell has seven
product terms going to the sum term and one product term
enabling the output.
Complex Mode Operation
ATF20V8B(Q)(L)
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
20L8
20H8
20P8
ATF20V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple
Mode, 8 product terms are allocated to the sum term. Pins
15 and 16 (center macrocells) are permanently configured
as combinatorial outputs. Other macrocells can be either
inputs or combinatorial outputs with pin feedback to the
AND-array. Pins 1 and 11 are regular inputs.
Simple Mode Option
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs can
be emulated using this mode:
Note:1. Shaded parts are obsolete with a last time buy date of 19 August 1999.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Note:1.Shaded parts are obsolete with a last time buy date of 19 August 1999.
28J
24P3
24S
24X
28J
24P3
24S
24X
28J
24P3
24S
24X
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C))
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0407H–04/01/xM
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