Rainbow Electronics ATF20V8BQL User Manual

Features

Industry-standard Architecture
– Emulates Many 24-pin PALs – Low-cost Easy-to-use Software Tools
High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
Device ICC, Standby ICC, Active
ATF20V8B 50 mA 55 mA
ATF20V8BQ 35 mA 40 mA
®
High-
ATF20V8BQL 5 mA 20 mA
CMOS and TTL Compatible Inputs and Outputs
Input and I/O Pull-up Resistors
Advanced Flash Technology
– Reprogrammable – 100% Tested
High-reliability CMOS Process
– 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-Compliant

Block Diagram

TSSOP

Pin Configurations

All Pinouts Top View
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional Buffers
OE Output Enable
* No Internal Connection
VCC +5V Supply
CLK/IN
GND
IN IN IN IN IN IN IN IN IN IN
DIP/SOIC
1 2 3 4 5 6 7 8 9 10 11 12
CLK/IN
GND
1 2
IN
3
IN
4
IN
5
IN
6
IN
7
IN
8
IN
9
IN
10
IN
11
IN
12
24
VCC
23
IN
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
IN
13
OE/IN
24 23 22 21 20 19 18 17 16 15 14 13
5
IN
6
IN
7
IN
8
*
9
IN
10
IN
11
IN
VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN
PLCC
ININCLK/IN*VCCINI/O
432
1
282726
12131415161718
*
IN
IN
IN
GND
OE/IN
performance EE PLD
ATF20V8B ATF20V8BQ ATF20V8BQL
I/O
25
I/O
24
I/O
23
*
22
I/O
21
I/O
20
I/O
19
I/O
Rev. 0407H–04/01
1

Description

The ATF20V8B is a high-performance CMOS (electrically­erasable) programmable logic device (PLD) that utilizes Atmel’s proven electrically-erasable Flash memory technol­ogy. Speeds down to 7.5 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the full 5V and 5V
± 10% range for industrial temperature ranges,
± 5% for commercial temperature ranges.
Several low-power options allow selection of the best solu­tion for various types of power-limited applications. Each of

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
(1)
(1)
these options significantly reduces total system power and enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 20R8 family and most 24-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with soft­ware, allow highly complex logic functions to be realized.
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi­mum output pin voltage is V may overshoot to 7.0V for pulses of less than 20 ns.
+ 0.75V DC which
CC

DC and AC Operating Conditions

Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C
V
Power Supply 5V=± 5% 5V=± 10%
CC
2
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)

DC Characteristics

Symbol Parameter Condition Min Typ Max Units
I
IL
Input or I/O Low Leakage Current
=VIL(Max) -35 -100 µA
0 =V
IN
I
I
I
IH
CC
CC2
Input or I/O High Leakage Current
Power Supp ly Current, Standby
Clocked Power Supply Current
= Max,
CC
= Max,
IN
IN
=V
CC
3.5 =V
V V Outputs Open
= Max,
V
CC
Outputs Open, f = 15 MHz
10 µA
Com. 60 90 mA
B-7, -10
Ind. 60 100 mA
B-15 Com. 60 80 mA
B-15 Ind. 60 90 mA
B-25 Com. 60 80 mA
B-25 Ind. 60 90 mA
BQ-10 Com. 35 55 mA
BQL-15 Com. 5 10 mA
BQL-15 Ind. 5 15 mA
BQL-25 Com. 5 10 mA
BQL-25 Ind. 5 15 mA
Com. 80 110 mA
B-7, -10
Ind. 80 125 mA
B-15 Com. 60 90 mA
B-15 Ind. 60 105 mA
B-25 Com. 60 90 mA
B-25 Ind. 60 105 mA
BQ-10 Com. 40 55 mA
BQL-15 Com. 20 35 mA
BQL-15 Ind. 20 40 mA
BQL-25 Com. 20 35 mA
BQL-25 Ind. 20 40 mA
IOS
V
IL
V
IH
V
OL
V
OH
(1)
Output Short Circuit Current
Input Low Voltage -0.5 0.8 V
Input High Voltage 2.0 VCC + 0.75 V
Output Low Voltage
Output High Voltage
V
= 0.5V -130 mA
OUT
= VIH or VIL,
V
IN
= Min
V
CC
= VIH or VIL,
V
IN
= Min
V
CC
= 24 mA
I
OL
= 16 mA 0.5 V
I
OL
= -4.0 mA 2.4 V
I
OH
Com., Ind.
0.5 V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
3
AC Waveforms
(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics
(1)
-7 -10 -15
Symbol Parameter
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
Input or Feedback to Non-Registered Output
Clock to Feedback 3 6 8 10 ns
Clock to Output 25272102 12 ns
Input or Feedback Setup Time
Hold Time 0000 ns
Clock Period 8 12 16 24 ns
Clock Width 46812 ns
8 outputs switching 3 7.5 3 10 3 15
1 output switching 7 ns
57.512
External Feedback 1/(tS + tCO) 100 68 45 37 MHz
f
MAX
Internal Feedback 1/(t
+ tCF) 125 74 50 40 MHz
S
No Feedback 1/(tP) 125 83 62 41 MHz
t
t
t
t
EA
ER
PZX
PXZ
Input to Output Enable — Product Term 3 9 3 10 3 15 3 20 ns
Input to Output Disable —Product Term 2 9 2 10 2 15 2 20 ns
OE pin to Output Enable 2 6 2 10 2 15 2 20 ns
OE pin to Output Disable 1.5 6 1.5 10 1.5 15 1.5 20 ns
Note: 1. See ordering information for valid part numbers and speed grades.
2. Shaded parts are obsolete with a last time buy data of of 19 August 1999.
-25
Min Max
UnitsMin Max Min Max Min Max
3 25 ns
15 ns
4
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)

Input Test Waveforms and Measurement Levels

Output Test Loads

Commercial

tR, tF < 5 ns (10% to 90%)

Pin Capacitance

f = 1 MHz, T = 25°C
C
IN
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
Typ Max Units Conditions
58 pF V
68 pF V

Power-up Reset

The registers in the ATF20V8Bs are designed to reset dur-
.
crossing
CC
Parameter Description Typ Max Units
t
PR
V
RST
Power-up Reset Time 600 1,000 ns
Power-up Reset Voltage 3.8 4.5 V

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
ing power-up. At a point delayed slightly from V
, all registers will be reset to the low state. As a result,
V
RST
the registered output state will always be high on power-up. This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the uncertainty of how V
actually rises in the system, the fol-
CC
lowing conditions are required:
1. The V
rise must be monotonic,
CC
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and
3. The clock must remain stable during t
PR

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.
IN
OUT
= 0V
= 0V

Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.

Programming/Erasing

Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, “CMOS PLD Programming Hardware and Software Support.”
5

Input and I/O Pull-ups

All ATF20V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V ensures that all logic array inputs are at known states.
. This
CC
These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below).

Input Diagram I/O Diagram

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.
The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a dif­ferent device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The deter­mining factors would be the usage of register versus com­binatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF20V8B universal architecture can be programmed to emulate many 24-pin PAL devices. These architectural
subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF20V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the content of the ATF20V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessi­ble regardless of the state of the security fuse.
6
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)

Compiler Mode Selection

Registered Complex Simple Auto Select
ABEL, Atmel-ABEL P20V8R P20V8C P20V8 P20V8
CUPL G20V8MS G20V8MA G20V8 G20V8A
LOG/iC GAL20V8_R
OrCAD-PLD Registered”“Complex”“Simple GAL20V8
PLDesigner P20V8 P20V8 P20V8 P20V8
Tango-PLD G20V8 G20V8 G20V8 G20V8
Note: 1. Only applicable for version 3.4 or lower.
(1)
GAL20V8_C7

ATF20V8B Registered Mode

PAL Device Emulation/PAL Replacement. The registered
mode is used if one or more registers are required. Each macrocell can be configured as either a registered or com­binatorial output or I/O, or as an input. For a registered out­put or I/O, the output is enabled by the OE register is clocked by the CLK pin. Eight product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When
pin, and the
(1)
GAL20V8_C8
(1)
GAL20V8
the macrocell is configured as an input, the output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode:
20R8 20RP8 20R6 20RP6 20R4 20RP4

Registered Mode Operation

7

Registered Mode Logic Diagram

8
ATF20V8B(Q)(L)

ATF20V8B Complex Mode

PAL Device Emulation/PAL Replacement. In the complex
Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output.

Complex Mode Operation

ATF20V8B(Q)(L)
Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode:
20L8
20H8 20P8

ATF20V8B Simple Mode

PAL Device Emulation/PAL Replacement. In the Simple
Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs.

Simple Mode Option

The compiler selects this mode when all outputs are combi­natorial without OE control. The following simple PALs can be emulated using this mode:
14L8 14H8 14P8 16L6 18H6 16P6 18L4 18H4 18P4 20L2 20H2 20P2
9

Complex Mode Logic Diagram

10
ATF20V8B(Q)(L)

Simple Mode Logic Diagram

ATF20V8B(Q)(L)
11
12
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)
13
14
ATF20V8B(Q)(L)
ATF20V8B(Q)(L)

ATF20V8B Ordering Information

tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range
7.5 5 5 ATF20V8B-7JC ATF20V8B-7PC ATF20V8B-7SC ATF20V8B-7XC
28J 24P3 24S 24X
Commercial
(0°C to 70°C)
10 7.5 7 ATF20V8B-10JC
ATF20V8B-10PC ATF20V8B-10SC ATF20V8B-10XC
ATF20V8B-10JI ATF20V8B-10PI ATF20V8B-10SI ATF20V8B-10XI
15 12 10 ATF20V8B-15JC
ATF20V8B-15PC ATF20V8B-15SC ATF20V8B-15XC
ATF20V8B-15JI ATF20V8B-15PI ATF20V8B-15SI ATF20V8B-15XI
25 15 12 ATF20V8B-25JC
ATF20V8B-25PC ATF20V8B-25SC ATF20V8B-25XC
ATF20V8B-25JI ATF20V8B-25PI ATF20V8B-25SI ATF20V8B-25XI
28J 24P3 24S 24X
28J 24P3 24S 24X
28J 24P3 24S 24X
28J 24P3 24S 24X
28J 24P3 24S 24X
28J 24P3 24S 24X
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Note: 1. Shaded parts are obsolete with a last time buy date of 19 August 1999.

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
15

ATF20V8BQ and ATF20V8BQL Ordering Information

tPD (ns) tS (ns) tCO (ns) Ordering Code Package Operation Range
10 7.5 7 ATF20V8BQ-10JC
ATF20V8BQ-10PC ATF20V8BQ-10XC
28J 24P3 24X
Commercial
(0°C to 70°C)
15 12 10 ATF20V8BQL-15JC
ATF20V8BQL-15PC ATF20V8BQL-15SC ATF20V8BQL-15XC
15 12 10 ATF20V8BQL-15JI
ATF20V8BQL-15PI ATF20V8BQL-15SI ATF20V8BQL-15XI
25 15 12 ATF20V8BQL-25JC
ATF20V8BQL-25PC ATF20V8BQL-25SC ATF20V8BQL-25XC
ATF20V8BQL-25JI ATF20V8BQL-25PI ATF20V8BQL-25SI ATF20V8BQL-25XI
Note: 1. Shaded parts are obsolete with a last time buy date of 19 August 1999.
28J 24P3 24S 24X
28J 24P3 24S 24X
28J 24P3 24S 24X
28J 24P3 24S 24X
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C))
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J 28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S 24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
16
ATF20V8B(Q)(L)
Packaging Information
ATF20V8B(Q)(L)
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
.045(1.14) X 45°
.032(.813) .026(.660)
.050(1.27) TYP
PIN NO. 1 IDENTIFY
.045(1.14) X 30° - 45°
.456(11.6) .450(11.4)
.300(7.62) REF SQ
SQ
.495(12.6) .485(12.3)
.022(.559) X 45° MAX (3X)
SQ
.012(.305) .008(.203)
.430(10.9)
.390(9.91) .021(.533) .013(.330)
.043(1.09) .020(.508) .120(3.05) .090(2.29)
.180(4.57) .165(4.19)
SQ
24P3, 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
1.27(32.3)
.200(5.06)
SEATING
PLANE
MAX
.151(3.84) .125(3.18)
.110(2.79) .090(2.29)
.012(.305) .008(.203)
1.25(31.7)
1.100(27.94) REF
PIN
1
.065(1.65) .040(1.02)
.325(8.26) .300(7.62)
0
REF
15
.400(10.2) MAX
.090(2.29)
.005(.127)
.070(1.78) .020(.508)
.023(.584) .014(.356)
.266(6.76) .250(6.35)
MAX
MIN
24S, 24-lead, 0.300" Wide, Plastic Gulll-wing Small Outline (SOIC) Dimensions in Inches and (Millimeters)
.020(.508) .013(.330)
PIN 1 ID
.616(15.6) .598(15.2)
0
REF
8
.299(7.60) .291(7.39)
.050(1.27) BSC
.012(.305) .003(.076)
.050(1.27) .015(.381)
.420(10.7) .393(9.98)
.105(2.67) .092(2.34)
.013(.330) .009(.229)
24X, 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) Dimensions in Millimeters and (Inches)
17
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Companys standard warranty which is detailed in Atmels Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as critical components in life support devices or systems.
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Printed on recycled paper.
0407H–04/01/xM
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