The ATF16V8CZ is a high-perform ance EECMOS
Programmable Logic Device which utilizes Atmel’s proven
electrically-erasable Flash memory technology. Speeds
down to 12 ns and a 25 µA edge-sensing power-down
mode are offered. All speed ranges are specified over the
full 5V ± 10% range for industrial temperature ranges; 5V ±
5% for commercial range 5-volt devices.
The ATF16V8CZ incorporates a superset of the generic
architectures, wh ich allows di rect replac ement of th e 16R8
family and most 20-pin combinatorial PLDs. Ei ght outputs
are each allocated eight produc t terms. Three different
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
(1)
(1)
modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
The ATF16V8CZ can significantly reduce total system
power, thereby enhancing system reliability and reducing
power supply costs. Wh en al l the inpu ts an d inte rn al nodes
are not switchi ng, su pply cur rent dr ops to les s than 25 µA.
This automatic power-down feature allows for power
savings in slow clock systems and asynchronous applications. Also, the pin keeper circuits eliminate the need for
internal pull-up resistors along with their attendant power
consumption.
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device . This is a s tress rating only and
functional operatio n of the dev ice at th ese or an y
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for exten ded periods may af fect device
reliability.
Note:1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.
+ 0.75V DC,
CC
DC and AC Operating Conditions
CommercialIndustrial
Operating Temperature (Ambient)0°C - 70°C-40°C - 85°C
V
Power Supply5V ± 5%5V ± 10%
CC
2
ATF16V8CZ
ATF16V8CZ
DC Characteristics
SymbolParameterConditionMinTypMaxUnits
I
IL
I
IH
I
CC1
Input or I/O Low Leakage Current0 ≤ VIN ≤ VIL(Max)-10µA
Input or I/O High Leakage Current3.5 ≤ VIN ≤ V
Power Supply Current
15 MHz, V
V
IN
CC
= 0, VCC, Outputs Open
CC
= Max,
Com95mA
Ind.105mA
10µA
(1)
I
CC
I
OS
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Power Supply Current,
Standby Mode
Output Short Circuit Current
Input Low VoltageMin < VCC < Max-0.50.8V
Input High Voltage2.0VCC+1V
Output Low Current
Output Hi gh Current
Output Low CurrentVCC = Min
Output Hi gh CurrentVCC = MinCom., Ind.4mA
MHz, V
= 0, VCC, Outputs Open
V
IN
V
OUT
= 5V; TA = 25°C
V
CC
= Min, All Outputs
V
CC
= -16 mA
I
OL
= Min
V
CC
= -3.2 mA
I
OL
Note:1. All ICC parameters measured with outputs open.
AC Waveforms
(1)
= Max,
CC
= 0.5V;
Com.525
Ind550
µA
µA
-150mA
Com, Ind.0.5V
2.4V
Com.24mA
Ind.12
Note:1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
3
AC Characteristics
SymbolParameter
-12-15
UnitsMinMaxMinMax
t
t
t
t
t
t
t
F
t
t
t
t
PD
CF
CO
S
H
P
W
MAX
EA
ER
PZX
PXZ
Input or Feedback to Non-registered Output312315ns
Clock to Feedback68ns
Clock to Output28210ns
Input or Feedback Setup Time1012ns
Input Hold Time00ns
Clock Period1216ns
Clock Width68ns
External Feedback 1/(tS + tCO)5545MHz
Internal Feedback 1/(tS + tCF)6250MHz
No Feedback 1/(t
)8362MHz
P
Input to Output Enable – Product Term312315ns
Input to Output Disable – Product Term215215ns
OE pin to Output Enable212215ns
OE pin to Output Disable1.5121.515ns
4
ATF16V8CZ
ATF16V8CZ
Input Test Waveforms and
Output Test Loads
Measurement Levels
tR, tF < 1.5 ns (10% to 90%)
Note:Similar devices are tested with slightly different loads.
These load differences may affect output signals’ delay
and slew rate. Atmel devices are tested with sufficient
margins to mee t compatible devices.
Pin Capacitance
f = 1 MHz, T = 25°C
C
IN
C
OUT
Note:1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(1)
TypMaxUnitsConditions
58 pFV
68 pFV
= 0V
IN
OUT
= 0V
Power-up Reset
The ATF16V8CZ’s registers are designed to reset during
power-up. At a point delayed slightly from V
, all registers will be reset to th e low s tate. As a resul t,
V
RST
the registered output state will always be high on power-up.
This feature is critical for state machine initialization.
However, due to the asynchronous nature of reset and the
uncertainty of how V
actually rises in the system, the
CC
following conditions are required:
1. The V
rise must be monotonic, from below 0.7V,
CC
2. After reset occurs, all input and feedback setup
times must be met before driving the clock term
high, and
3. The signals from which the clock is derived must
remain stable during t
The ATF16V8CZ’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since an y state can be
forced into the registers to control test sequenc ing. A
JEDEC file with preload is generated whe n a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automaticall y by approved
programmers.
Security Fuse Usage
A single fuse is provided to pre vent unauthorized copying
of the ATF16V8CZ fuse patterns. Once programmed, fuse
verify and preload are in hibited. Howev er, the 64-bit Us er
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Input and I/O Pin Keeper Circuits
The ATF16V8CZ contains inte rnal i nput and I/O pin kee per
circuits. These circuits allow each ATF16V8CZ pin to hold
its previous value even when it is not being driven by an
external source or by the devi ce's output buffe r. This helps
insure that all logic array inputs are at known, valid logic
levels. This redu ces s ystem power b y preven ting pi ns fro m
floating to indeterminate levels. By using pin keeper circuits
rather than pull-up resistors, there is no DC current
required to hold the pins in either logic state (high or low).
These pin keeper circui ts are implemen ted as weak feedback inverters, as s hown in the Input Di agram below.
These keeper circuits c an ea si ly be over dr iven by standard
TTL- or CMOS-compatible driver s. The typical ove rdrive
current required is 40 µA.
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
Marks bearing ® and/or ™ are regi stered trad emar ks and trad emark s of A tmel C orp oratio n.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
0453F–08/99/xM
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