Rainbow Electronics ATF16V8C User Manual

Features

• Industry-standard Architecture

– Emulates Many 20-pin PALs – Low-cost Easy-to-use Software Tools

• High-speed Electrically-erasable Programmable Logic Devices

– 5 ns Maximum Pin-to-pin Delay

• Low-power - 100 µA Pin-controlled Power-down Mode Option

• CMOS and TTL Compatible Inputs and Outputs

– I/O Pin Keeper Circuits

• Advanced Flash Technology

– Reprogrammable – 100% Tested

• High-reliability CMOS Process

– 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunity

• Commercial and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Packages in Standard Pinouts

• PCI Compliant

Block Diagram

Highperformance EE PLD

ATF16V8C

Note: 1. Includes optional PD control pin.

Pin Configurations

All Pinouts Top View

Pin Name Function

CLK Clock I Logic Inputs I/O Bidirectional Buffers OE VCC +5V Supply PD Power-down

Output Enable

I/CLK

I1 I2

PD/I3

I4 I5 I6 I7 I8

GND

I/CLK

PD/I3

GND

DIP/SOIC

1 2 3 4 5 6 7 8 9 10

TSSOP

1 2

4 5

VCC

I/O

I9/OE

PLCC

VCC

I/O

I9/OE

PD/I3

I4 I5 I6 I7

I2I1I/CLK 321

4 5 6 7 8

910111213 I8

GND

I9/OE

VCC

I/O

19 18

17 16 15 14

I/O

I/O I/O I/O I/O I/O

Rev. 0425G–08/99

Description

The ATF16V8C is a high -perfor manc e EEC MOS Pr ogra mmable Logic Device that utilizes Atmel’s proven electricallyerasable Flash memory technology. Speeds down to 5 ns and a 100 µA pin-controlled power-down mode option are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges; 5V ± 5% for commercial range 5-volt devices.

The ATF16V8C incorporates a s uperset of the ge neric architectures, wh ich allows di rect replac ement of th e 16R8 family and most 20-pin combinatorial PLDs. Ei ght outputs are each allocated eight produc t terms. Three different

Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin with Respect to Ground...-2.0V to +7.0V Voltage on Input Pins

with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

modes of operation, configured automatically with software, allow highly complex logic functions to be realized.

The ATF16V8C can significantly reduce total system power, thereby enhancing system reliability and reducing power supply costs. When pin 4 is configured as the power-down control pin, supply current drops to less than 100 µA whenever the pin is high. If the power-down feature isn't required for a particular application, pin 4 may be used as a logic input. Also, the pin keeper circuits eliminate the need for internal pu ll -up r es isto rs a lon g wi th t hei r atte nda nt power consumption.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device . This is a s tress rating only and functional operatio n of the dev ice at th ese or an y other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for exten ded periods may af fect device reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V which may overshoot to 7.0V for pulses of less than 20 ns.

+ 0.75V DC,

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0°C - 70°C-40°C - 85°C V

Power Supply 5V ± 5% 5V ± 10%

ATF16V8C

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I I

CC1

Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL (Max) -10.0 µA Input or I/O High Leakage Current 3.5 ≤ VIN ≤ V

(1)

Power Supply Current, Standby

15 MHz, V V

= 0, VCC, Outputs Open

= Max,

Com. 115 mA Ind. 130 mA

10.0 µA

Power Supply Current, Power-down Mode

Output Short Circuit Current V

= Max, VIN = 0, V

= 0.5V;

OUT

= 5V; TA = 25°C

Input Low Voltage Min < VCC < Max -0.5 0.8 V Input High Voltage 2.0 VCC + 1 V

= Min; All Outputs

Output Low Voltage

Output High Voltage

= 24 mA

= Min

= -4.0 mA

Output Low Current VCC = Min

Output High Current VCC = Min Com., Ind. -4.0 mA

Note: 1. All ICC parameters measured with outputs open.

AC Waveforms

Com. 10 100 µA Ind. 10 105

µA

-150 mA

Com., Ind. 0.5 V

2.4 V

Com. 24.0 mA Ind. 12.0 mA

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics

Symbol Parameter

-5 -7 UnitsMin Max Min Max

Input or Feedback to Non-Registered Output 1 5 3 7.5 ns Clock to Feedback 3 3 ns Clock to Output 1425ns Input or Feedback Setup Time 3 5 ns Input Hold Time 0 0 ns Clock Period 6 8 ns Clock Width 3 4 ns External Feedback 1/(tS + tCO) 142 100 MHz

t t t t

MAX

PZX

PXZ

Internal Feedback 1/(tS + tCF) 166 125 MHz No Feedback 1/(t

) 166 125 MHz

Input to Output Enable – Product Term2639ns Input to Output Disable – Product Term2529ns OE pin to Output Enable 2526ns OE pin to Output Disable 1.5 5 1.5 6 ns

Power-down AC Characteristics

(1)(2)(3)

-5 -7

Symbol Parameter

IVDH

GVDH

CVDH

DHIX

DHGX

DHCX

DLIV

DLGV

DLCV

DLOV

Valid Input Before PD High 5.0 7.5 ns Valid OE Before PD High 0 0 ns Valid Clock Before PD High 0 0 ns Input Don’t Care After PD High 5.0 7.5 ns OE Don’t Care After PD High 5.0 7.5 ns Clock Don’t Care After PD High 5.0 7.5 ns PD Low to Valid Input 5.0 7.5 ns PD Low to Valid OE 15.0 20.0 ns PD Low to Valid Clock 15.0 20.0 ns PD Low to Valid Output 20.0 25.0 ns

Notes: 1. Output data is latched and held.

2. HI-Z outputs remain HI-Z.

3. Clock and input transitions are ignored.

UnitsMin Max Min Max

ATF16V8C

Input Test Waveforms and Measurement Levels:

Output Test Loads:

5.0V

R1 = 200

R2 = 200

OUTPUT PIN

CL = 50 pF

tR, tF < 1.5 ns (10% to 90%)

Pin Capacitance

(1)

f = 1 MHz, T = 25°C

Typ Max Units Conditions

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

58pFV 68pFV

Power-up Reset

The ATF16V8C ’s registers are designed to reset during power-up. At a point delayed slightly from V

, all registers will be reset to th e low s tate. As a resul t,

RST

the registered output state will always be high on power-up. This feature is critical for state machine initialization.

However, due to the asynchronous nature of reset and the uncertainty of how V

actually rises in the system, the

following conditions are required:

1. The V

rise must be monotonic, from below 0.7V,

2. After reset occurs, all input and feedback setup times must be met before driving the clock term high, and

3. The signals from which the clock is derived must remain stable during t

crossing

Parameter Description Typ Max Units

RST

Power-up Reset Time

Power-up Reset Voltage

600 1,000 ns

3.8 4.5 V

= 0V

OUT

= 0V

Power-down Mode

The ATF16V8C includes an optional pin controlled powerdown feature. Dev ice pin 4 may be configur ed as the power-down pin. When this feature is enabled and the power-down pin is high, total curren t consumption dr ops to less than 100 µ A. I n the p ower-do wn mode , all output data and internal logic states are latched and held. All registered and combinator ial output da ta remains v alid. Any ou tputs which were in a HI-Z state at the onset of power-down will remain at HI-Z. During power-down, all input signals except the power-down pin are blocked. T he input and I/O pin keeper circuits remain ac tiv e to in su re that pin s do not floa t to indeterminate levels. This helps to further reduce system power.

Selection of the power-down option is specified in the ATF16V8C logi c de sign f ile. The log ic com pile r wi ll in clud e this option selection in the otherwise standard 16V8 JEDEC fuse file. When the power-down feature is not specified in the design file, pin 4 is available as a logic input, and there is no power-down pin. This allows the ATF16V8C to be programmed using any existing standard 16V8 fuse file.

Note: Some programmers list the JEDEC-compatible 16V8C

(No PD used) separately from the non-JEDEC compatible 16V8CEXT. (EXT for extended features.)

external source or by the device’s output buffer. This helps insure that all logic array inputs are at known, valid logic levels. This redu ces s ystem power b y preven ting pi ns fro m floating to indeterminate levels. By using pin keeper circuits rather than pull-up resistors, there is no DC current required to hold the pins in either logic state (high or low).

These pin keeper circuits are implemented a s weak feedback inverters, as shown in the Inp ut Diagram below. These keeper circuits c an ea si ly be ov er driv en by s tand ard TTL- or CMOS-compatible driver s. The typical ove rdrive current required is 40 µA.

Input Diagram

Registered Output Preload

The ATF16V8C’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since an y state can be forced into the registers to control test sequenc ing. A JEDEC file with preload is generated whe n a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automaticall y by approved programmers.

Security Fuse Usage

A single fuse is provided to pre vent unauthorized copying of the ATF16V8C fuse patterns. Once programmed, fuse verify and preload are in hibited. Howev er, the 64-bit Us er Signature remains accessible.

The security fuse will be programmed last, as its effect is immediate.

Input and I/O Pin Keeper Circuits

The ATF16V8C contains internal input and I/O pin keeper circuits. These circuits allow each ATF16V8C pin to hold its previous value even when it is not being driven by an

I/O Diagram

ATF16V8C

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