Rainbow Electronics ATF16V8BQL User Manual

Features

• Industry-standard Architecture

– Emulates Many 20-pin PALs
– Low-cost Easy-to-use Software Tools

• High-speed Electrically-erasable Programmable Logic Devices

– 7.5 ns Maximum Pin-to-pin Delay

• Several Power Saving Options

Device ICC, Standby ICC, Active

ATF16V8B 50 mA 55 mA

ATF16V8BQ 35 mA 40 mA

ATF16V8BQL 5 mA 20 mA

• CMOS and TTL Compatible Inputs and Outputs

– Input and I/O Pull-up Resistors

• Advanced Flash Technology

– Reprogrammable
– 100% Tested

• High-reliability CMOS Process

– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity

• Commercial, and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Packages in Standard Pinouts

• PCI-compliant

®

High­performance
EE PLD

ATF16V8B
ATF16V8BQ
ATF16V8BQL

Block Diagram

Pin Configurations

All Pinouts Top View

Pin Name Function

CLK Clock

I Logic Inputs

I/O Bi-directional Buffers

OE

VCC +5V Supply

Output Enable

I/CLK

GND

DIP/SOIC

1
2

I1

3

I2

4

I3

5

I4

6

I5

7

I6

8

I7

9

I8

10

I/CLK

GND

20
19
18
17
16
15
14
13
12
11

TSSOP

1
2

I1

3

I2

4

I3

5

I4

6

I5

7

I6

8

I7

9

I8

10

VCC

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

I9/OE

11

PLCC

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE

I3
I4
I5
I6
I7

I2I1I/CLK

321

4
5
6
7
8

910111213

I8

GND

I9/OE

VCC

20

I/O

I/O

19
18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

I/O

Rev. 0364I–04/01

1

Description

The ATF16V8B is a high-performance CMOS (electrically­erasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technol­ogy. Speeds down to 7.5 ns are offered. All speed ranges
are specified over the full 5V
temperature ranges, and 5V

± 10% range for industrial

± 5% for commercial tempera-

ture ranges.

Several low-power options allow selection of the best solu­tion for various types of power-limited applications. Each of

Absolute Maximum Ratings*

Temperature Under Bias.................................-55oC to +125oC

Storage Temperature......................................-65

Voltage on Any Pin with

Respect to Ground .......................................-2.0 V to +7.0 V

Voltage on Input Pins
with Respect to Ground

During Programming...................................-2.0 V to +14.0 V

Programming Voltage with

Respect to Ground .....................................-2.0 V to +14.0 V

o

C to +150oC

(1)

(1)

(1)

these options significantly reduces total system power and
enhances system reliability.

The ATF16V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft­ware, allow highly complex logic functions to be realized.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.

+ 0.75V DC,

CC

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0

VCC Power Supply 5V=± 5% 5V=± 10%

o

C - 70oC-40

o

C - 85oC

2

ATF16V8B(QL)

ATF16V8B(QL)

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

IL

I

IH

Input or I/O Low
Leakage Current

Input or I/O High
Leakage Current

0 ≤=VIN ≤=VIL(Max) -35 -100 µA

3.5 ≤=V

IN

≤=V

CC

10 µA

Com. 55 85 mA

B-7, -10

Ind. 55 95 mA

B-15 Com. 50 75 mA

B-15 Ind. 50 80 mA

V

= Max,

I

CC

Power Supp ly
Current, Standby

CC

= Max,

V

IN

Outputs Open

B-25 Com. 50 75 mA

B-25 Ind. 50 80 mA

BQ-10 Com. 35 55 mA

BQL-15 Com. 5 10 mA

BQL-15 Ind. 5 15 mA

BQL-25 Com. 5 10 mA

BQL-25 Ind. 5 15 mA

Com. 60 90 mA

B-7, -10

Ind. 60 100 mA

B-15 Com. 55 85 mA

B-15 Ind. 55 95 mA

B-25 Com. 55 85 mA

B-25 Ind. 55 95 mA

BQ-10 Com. 40 55 mA

I

CC2

Clocked Power
Supply Current

= Max,

V

CC

Outputs Open,
f=15 MHz

BQL-15 Com. 20 35 mA

BQL-15 Ind. 20 40 mA

BQL-25 Com. 20 35 mA

BQL-25 Ind. 20 40 mA

(1)

I

OS

V

IL

V

IH

V

OL

V

OH

Output Short
Circuit Current

= 0.5 V -130 mA

V

OUT

Input Low Voltage -0.5 0.8 V

Input High Voltage 2.0 VCC+0.75 V

Output High Voltage

Output High Voltage

V

IN=VIH

V

CC

V

IN=VIH

V

CC

or VIL,

=Min

or VIL,

=Min

= -24 mA

I

OL

Com., Ind.

= -4.0 mA 2.4 V

I

OH

0.5 V

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

2. Shaded parts are obsolete with a last time buy date of 19 August 1999.

3

AC Waveforms

(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.

AC Characteristics

(1)

-10 -15

Symbol Parameter

t

PD

t

CF

t

CO

t

S

t

H

t

P

t

W

Input or Feedback to
Non-Registered Output

Clock to Feedback 6 8 10 ns

Clock to Output 2 7 2 10 2 12 ns

Input or Feedback
Setup Time

Hold Time 0 0 0 ns

Clock Period 12 16 24 ns

Clock Width 6 8 12 ns

8 outputs switching 3 10 3 15

1 output switching ns

7.5 12

External Feedback 1/(tS+tCO)684537 MHz

f

MAX

t

EA

t

ER

t

PZX

t

PXZ

Internal Feedback 1/(tS + tCF)745040 MHz

No Feedback 1/(t

Input to Output Enable —
Product Term

Input to Output Disable —
Product Term

)836241 MHz

P

310315

210215

OE pin to Output Enable 2 10 2 15 2 20 ns

OE pin to Output Disable 1.5 10 1.5 15 1.5 20 ns

Note: 1. See ordering information for valid part numbers and speed grades.

2. Shaded parts are obsolete with a last time buy date of 19 August 1999.

-25

Min Max

UnitsMin Max Min Max

3 25 ns

15 ns

3 20 ns

2 20 ns

4

ATF16V8B(QL)

ATF16V8B(QL)

Input Test Waveforms and Measurement Levels:

Output Test Loads:

Commercial

tR, tF < 5 ns (10% to 90%)

Pin Capacitance

f = 1 MHz, T = 25°C

C

IN

C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

(1)

Typ Max Units Conditions

58 pF V

68 pF V

Power-up Reset

The registers in the ATF16V8Bs are designed to reset dur-

.

crossing

CC

Parameter Description Typ Max Units

t

PR

V

RST

Power-up
Reset Time

Power-up
Reset Voltage

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying
of the ATF16V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.

The security fuse should be programmed last, as its effect
is immediate.

ing power-up. At a point delayed slightly from V

, all registers will be reset to the low state. As a result,

V

RST

the registered output state will always be high on power-up.

This feature is critical for state machine initialization. How­ever, due to the asynchronous nature of reset and the
uncertainty of how V

actually rises in the system, the fol-

CC

lowing conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and

3. The clock must remain stable during t

PR

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.

= 0 V

IN

= 0 V

OUT

600 1,000 ns

3.8 4.5 V

5

Electronic Signature Word

There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.

Programming/Erasing

Programming/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware
and Software Support for information on
software/programming.

Input and I/O Pull-ups

All ATF16V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V
ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).

CC

. This

Input Diagram

Compiler Mode Selection

I/O Diagram

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the
ATF16V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.

The ATF16V8B can be configured in one of three different
modes. Each mode makes the ATF16V8B look like a differ­ent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter­mining factors would be the usage of register versus
combinatorial outputs and dedicated outputs versus
outputs with output enable control.

The ATF16V8B universal architecture can be programmed
to emulate many 20-pin PAL devices. These architectural
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF16V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.

Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF16V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessible
regardless of the state of the security fuse.

Registered Complex Simple Auto Select

ABEL, Atmel-ABEL P16V8R P16V8C P16V8AS P16V8

CUPL G16V8MS G16V8MA G16V8AS G16V8

LOG/iC GAL16V8_R

OrCAD-PLD “Registered”“Complex”“Simple” GAL16V8A

PLDesigner P16V8R P16V8C P16V8C P16V8A

Tango-PLD G16V8R G16V8C G16V8AS G16V8

Note: 1. Only applicable for version 3.4 or lower.

6

ATF16V8B(QL)

(1)

GAL16V8_C7

(1)

GAL16V8_C8

(1)

GAL16V8

ATF16V8B(QL)

Macrocell Configuration

Software compilers support the three different OMC
modes as different device types. Most compilers have the
ability to automatically select the device type, generally
based on the register usage and output enable (OE) usage.
Register usage on the device forces the software to choose
the registered mode. All combinatorial outputs with OE
controlled by the product term will force the software to
choose the complex mode. The software will choose the
simple mode only when all outputs are dedicated combina­torial without OE control. The different device types can be
used to override the automatic device selection by the soft­ware. For further details, refer to the compiler software
manuals.

When using compiler software to configure the device, the
user must pay special attention to the following restrictions
in each mode.

In registered mode pin 1 and pin 11 are permanently
configured as clock and output enable, respectively. These
pins cannot be configured as dedicated inputs in the
registered mode.

In complex mode pin 1 and pin 11 become dedicated
inputs and use the feedback paths of pin 19 and pin 12
respectively. Because of this feedback path usage, pin 19
and pin 12 do not have the feedback option in this mode.

In simple mode all feedback paths of the output pins are
routed via the adjacent pins. In doing so, the two inner most
pins (pins 15 and 16) will not have the feedback option as
these pins are always configured as dedicated combinato­rial output.

ATF16V8B Registered Mode

PAL Device Emulation/PAL Replacement. The registered

mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or com­binatorial output or I/O, or as an input. For a registered
output or I/O, the output is enabled by the OE
register is clocked by the CLK pin. Eight product terms are
allocated to the sum term. For a combinatorial output or
I/O, the output enable is controlled by a product term, and
seven product terms are allocated to the sum term. When
the macrocell is configured as an input, the output enable is
permanently disabled.

Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:

16R8 16RP8

16R6 16RP6

16R4 16RP4

pin, and the

Registered Configuration for
Registered Mode

Notes: 1. Pin 1 controls common CLK for the registered out-

puts. Pin 11 controls common OE
outputs. Pin 1 and Pin 11 are permanently
configured as CLK and OE

2. The development software configures all the archi­tecture control bits and checks for proper pin usage
automatically.

(1)(2)

for the registered

.

Combinatorial Configuration for
Registered Mode

Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK

and OE

2. The development software configures all the archi­tecture control bits and checks for proper pin usage
automatically.

.

(1)(2)

7

Registered Mode Logic Diagram

8

ATF16V8B(QL)

ATF16V8B Complex Mode

ATF16V8B(QL)

PAL Device Emulation/PAL Replacement. In the complex

mode, combinatorial output and I/O functions are possible.
Pins 1 and 11 are regular inputs to the array. Pins 13
through 18 have pin feedback paths back to the AND-array,
which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have
input capability. In this mode, each macrocell has seven
product terms going to the sum term and one product term
enabling the output.

Complex Mode Option

ATF16V8B Simple Mode

PAL Device Emulation/PAL Replacement. In the Simple

Mode, 8 product terms are allocated to the sum term. Pins
15 and 16 (center macrocells) are permanently configured
as combinatorial outputs. Other macrocells can be either
inputs or combinatorial outputs with pin feedback to the
AND-array. Pins 1 and 11 are regular inputs.

Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:

16L8

16H8

16P8

The compiler selects this mode when all outputs are combi­natorial without OE control. The following simple PALs can
be emulated using this mode:

10L8 10H8 10P8

12L6 12H6 12P6

14L4 14H4 14P4

16L2 16H2 16P2

Simple Mode Option

* - Pins 15 and 16 are always enabled.

9

Complex Mode Logic Diagram

10

ATF16V8B(QL)

Simple Mode Logic Diagram

ATF16V8B(QL)

11

SUPPLY CURRENT vs. INPUT FREQUENCY

ATF16V8B/BQ (VCC = 5V, TA = 25C)

75

I

50

C
C

m

25

A

ATF16V8B

ATF16V8BQ

SUPPLY CURRENT vs. INPUT FREQUENCY

ATF16V8BL/BQL (VCC = 5V, TA = 25C)

75

I

50

C
C

m

25

A

ATF16V8B

ATF16V8BQL

0

0 25 50 75 100

FREQUENCY (MHz)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

65

55

I
C
C

45

m
A

35

25

4.50 4.75 5.00 5.25 5.50

ATF16V8B/BQ (TA = 25C)

ATF16V8B

ATF16V8BQ

SUPPLY VOLTAGE (V)

0

0 20406080100

FREQUENCY (MHz)

12

OUTPUT SOURCE CURRENT

vs. SUPPLY VOLTAGE (TA = 25C)

-10

-12

I

-14

O

-16

H

-18

m

-20

A

-22

-24

4.5 4.7 4.9 5.1 5.3 5.5

SUPPLY VOLTAGE (V)

ATF16V8B(QL)

ATF16V8B(QL)

NORMALIZED TCO

vs. SUPPLY VOLTAGE(TA=25°C)

1.3

N

1.15

O

R

M

1

T

0.85

C

O

0.7

4.50 4.75 5.00 5.25 5.50

SUPPLY VOLTAGE (V)

ATF16V8B/BQ

ATF16V8BQL

NORMALIZED TPD

vs. SUPPLY VOLTAGE (TA=25°C)

1.3

N

1.15

O
R
M

1

T

0.85

P
D

0.7

4.50 4.75 5.00 5.25 5.50

SUPPLY VOLTAGE (V)

ATF16V8B/BQ

ATF16V8BQL

13

14

ATF16V8B(QL)

ATF16V8B(QL)

15

ATF16V8B Ordering Information

t

PD

(ns)

10 7.5 7 ATF16V8B-10JC

15 12 10 ATF16V8B-15JC

25 15 12 ATF16V8B-25JC

Note: 1. Shaded parts are obsolete with a last time buy date of 19 August 1999.

t

S

(ns)

t

CO

(ns) Ordering Code Package Operation Range

20J
ATF16V8B-10PC
ATF16V8B-10SC
ATF16V8B-10XC

ATF16V8B-10JI
ATF16V8B-10PI
ATF16V8B-10SI
ATF16V8B-10XI

ATF16V8B-15PC
ATF16V8B-15SC
ATF16V8B-15XC

ATF16V8B-15JI
ATF16V8B-15PI
ATF16V8B-15SI
ATF16V8B-15XI

ATF16V8B-25PC
ATF16V8B-25SC
ATF16V8B-25XC

ATF16V8B-25JI
ATF16V8B-25PI
ATF16V8B-25SI
ATF16V8B-25XI

20P3

20S

20X

20J

20P3

20S

20X

20J

20P3

20S

20X

20J

20P3

20S

20X

20J

20P3

20S

20X

20J

20P3

20S

20X

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.

Package Type

20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)

20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S 20-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)

20X 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)

16

ATF16V8B(QL)

ATF16V8BQ and ATF16V8BQL Ordering Information

ATF16V8B(QL)

t

PD

(ns)

10 7.5 7 ATF16V8BQ-10JC

15 12 10 ATF16V8BQL-15JC

25 15 12 ATF16V8BQL-25JC

Note: 1. Shaded parts are obsolete with a last time buy date of 11 August 1999.

t

S

(ns)

t

CO

(ns) Ordering Code Package Operation Range

ATF16V8BQ-10PC
ATF16V8BQ-10SC
ATF16V8BQ-10XC

ATF16V8BQL-15PC
ATF16V8BQL-15SC
ATF16V8BQL-15XC

ATF16V8BQL-15JI
ATF16V8BQL-15PI
ATF16V8BQL-15SI
ATF16V8BQL-15XI

ATF16V8BQL-25PC
ATF16V8BQL-25SC
ATF16V8BQL-25XC

ATF16V8BQL-25JI
ATF16V8BQL-25PI
ATF16V8BQL-25SI
ATF16V8BQL-25XI

20J
20P3
20S
20X

20J
20P3
20S
20X

20J
20P3
20S
20X

20J
20P3
20S
20X

20J
20P3
20S
20X

Commercial

(0°C to 70°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.

Package Type

20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)

20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S 20-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)

20X 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)

17

Packaging Information

20J, 20-lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AA

20P3, 20-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 AD

1.060(26.9)

.210(5.33)

SEATING

PLANE

.150(3.81)
.115(2.92)

MAX

.110(2.79)
.090(2.29)

.014(.356)
.008(.203)

.980(24.9)

.900(22.86) REF

PIN

1

.070(1.78)
.045(1.13)

.325(8.26)
.300(7.62)

0

REF

15

.430(10.92) MAX

.090(2.29)

.005(.127)

.015(.381) MIN

.022(.559)
.014(.356)

.280(7.11)
.240(6.10)

MAX

MIN

20S, 20-lead, 0.300" Wide, Plastic Gull-Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)

0.020 (0.508)

0.013 (0.330)

0.420 (10.7)

0.393 (9.98)

0.105 (2.67)

0.092 (2.34)

PIN 1

0
8

REF

0.035 (0.889)

0.015 (0.381)

.050 (1.27) BSC

0.513 (13.0)

0.497 (12.6)

0.012 (0.305)

0.003 (0.076)

0.299 (7.60)

0.291 (7.39)

0.013 (0.330)

0.009 (0.229)

20X, 20-lead, 4.4 mm Wide, Plastic Thin Shrink
Small Outline (TSSOP)
Dimensions in Millimeters and (Inches)

0.30(0.012)

0.18(0.007)

PIN 1 ID

0

REF

8

6.60(.260)

6.40(.252)

0.70(.028)

0.50(.020)

4.48(.176)

4.30(.169)

0.65(.0256) BSC

0.15(.006)

0.05(.002)

6.50(.256)

6.25(.246)

1.10(0.043) MAX

0.18(.007)

0.09(.003)

18

ATF16V8B(QL)

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

Europe

Atmel SarL
Route des Arsenaux 41
Casa Postale 80
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Switzerland
TEL [phone]
FAX [phone]

Asia

Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL [phone]
FAX [phone]

Japan

Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL [phone]
FAX [phone]

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL [phone]
FAX [phone]

Atmel Rousset

Zone Industrielle
13106 Rousset Cedex
France
TEL [phone]
FAX [phone]

Atmel Smart Card ICs

Scottish Enterprise Technology Park
East Kilbride, Scotland G75 0QR
TEL [phone]
FAX [phone]

Atmel Grenoble

Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex
France
TEL [phone]
FAX [phone]

Fax-on-Demand

North America:

e-mail

[e-mail]

1-[phone]

International:
1-[phone]

Web Site

http://www.atmel.com

BBS

1-[phone]

© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.

Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

0364I–04/01/xM