Rainbow Electronics ATF16V8BQL User Manual

Features

• Industry-standard Architecture

– Emulates Many 20-pin PALs – Low-cost Easy-to-use Software Tools

• High-speed Electrically-erasable Programmable Logic Devices

– 7.5 ns Maximum Pin-to-pin Delay

• Several Power Saving Options

Device ICC, Standby ICC, Active

ATF16V8B 50 mA 55 mA

ATF16V8BQ 35 mA 40 mA

ATF16V8BQL 5 mA 20 mA

• CMOS and TTL Compatible Inputs and Outputs

– Input and I/O Pull-up Resistors

• Advanced Flash Technology

– Reprogrammable – 100% Tested

• High-reliability CMOS Process

– 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunity

• Commercial, and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Packages in Standard Pinouts

• PCI-compliant

Highperformance EE PLD

ATF16V8B ATF16V8BQ ATF16V8BQL

Block Diagram

Pin Configurations

All Pinouts Top View

Pin Name Function

CLK Clock

I Logic Inputs

I/O Bi-directional Buffers

VCC +5V Supply

Output Enable

I/CLK

GND

DIP/SOIC

1 2

I/CLK

GND

20 19 18 17 16 15 14 13 12 11

TSSOP

1 2

VCC

I/O

I9/OE

PLCC

VCC I/O I/O I/O I/O I/O I/O I/O I/O I9/OE

I3 I4 I5 I6 I7

I2I1I/CLK

321

4 5 6 7 8

910111213

GND

I9/OE

VCC

I/O

19 18

I/O

Rev. 0364I–04/01

Description

The ATF16V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to 7.5 ns are offered. All speed ranges are specified over the full 5V temperature ranges, and 5V

± 10% range for industrial

± 5% for commercial tempera-

ture ranges.

Several low-power options allow selection of the best solution for various types of power-limited applications. Each of

Absolute Maximum Ratings*

Temperature Under Bias.................................-55oC to +125oC

Storage Temperature......................................-65

Voltage on Any Pin with

Respect to Ground .......................................-2.0 V to +7.0 V

Voltage on Input Pins with Respect to Ground

During Programming...................................-2.0 V to +14.0 V

Programming Voltage with

Respect to Ground .....................................-2.0 V to +14.0 V

C to +150oC

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these options significantly reduces total system power and enhances system reliability.

The ATF16V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V which may overshoot to 7.0V for pulses of less than 20 ns.

+ 0.75V DC,

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0

VCC Power Supply 5V=± 5% 5V=± 10%

C - 70oC-40

C - 85oC

ATF16V8B(QL)

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

0 ≤=VIN ≤=VIL(Max) -35 -100 µA

3.5 ≤=V

≤=V

10 µA

Com. 55 85 mA

B-7, -10

Ind. 55 95 mA

B-15 Com. 50 75 mA

B-15 Ind. 50 80 mA

= Max,

Power Supp ly Current, Standby

= Max,

Outputs Open

B-25 Com. 50 75 mA

B-25 Ind. 50 80 mA

BQ-10 Com. 35 55 mA

BQL-15 Com. 5 10 mA

BQL-15 Ind. 5 15 mA

BQL-25 Com. 5 10 mA

BQL-25 Ind. 5 15 mA

Com. 60 90 mA

B-7, -10

Ind. 60 100 mA

B-15 Com. 55 85 mA

B-15 Ind. 55 95 mA

B-25 Com. 55 85 mA

B-25 Ind. 55 95 mA

BQ-10 Com. 40 55 mA

CC2

Clocked Power Supply Current

= Max,

Outputs Open, f=15 MHz

BQL-15 Com. 20 35 mA

BQL-15 Ind. 20 40 mA

BQL-25 Com. 20 35 mA

BQL-25 Ind. 20 40 mA

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Output Short Circuit Current

= 0.5 V -130 mA

OUT

Input Low Voltage -0.5 0.8 V

Input High Voltage 2.0 VCC+0.75 V

Output High Voltage

IN=VIH

or VIL,

=Min

or VIL,

=Min

= -24 mA

Com., Ind.

= -4.0 mA 2.4 V

0.5 V

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

2. Shaded parts are obsolete with a last time buy date of 19 August 1999.

AC Waveforms

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Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.

AC Characteristics

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-10 -15

Symbol Parameter

Input or Feedback to Non-Registered Output

Clock to Feedback 6 8 10 ns

Clock to Output 2 7 2 10 2 12 ns

Input or Feedback Setup Time

Hold Time 0 0 0 ns

Clock Period 12 16 24 ns

Clock Width 6 8 12 ns

8 outputs switching 3 10 3 15

1 output switching ns

7.5 12

External Feedback 1/(tS+tCO)684537 MHz

MAX

PZX

PXZ

Internal Feedback 1/(tS + tCF)745040 MHz

No Feedback 1/(t

Input to Output Enable — Product Term

Input to Output Disable — Product Term

)836241 MHz

310315

210215

OE pin to Output Enable 2 10 2 15 2 20 ns

OE pin to Output Disable 1.5 10 1.5 15 1.5 20 ns

Note: 1. See ordering information for valid part numbers and speed grades.

2. Shaded parts are obsolete with a last time buy date of 19 August 1999.

-25

Min Max

UnitsMin Max Min Max

3 25 ns

15 ns

3 20 ns

2 20 ns

ATF16V8B(QL)

Input Test Waveforms and Measurement Levels:

Output Test Loads:

Commercial

tR, tF < 5 ns (10% to 90%)

Pin Capacitance

f = 1 MHz, T = 25°C

OUT

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

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Typ Max Units Conditions

58 pF V

68 pF V

Power-up Reset

The registers in the ATF16V8Bs are designed to reset dur-

crossing

Parameter Description Typ Max Units

RST

Power-up Reset Time

Power-up Reset Voltage

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.

The security fuse should be programmed last, as its effect is immediate.

ing power-up. At a point delayed slightly from V

, all registers will be reset to the low state. As a result,

RST

the registered output state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V

actually rises in the system, the fol-

lowing conditions are required:

1. The V

rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and

3. The clock must remain stable during t

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.

= 0 V

OUT

600 1,000 ns

3.8 4.5 V

Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.

Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware and Software Support for information on software/programming.

Input and I/O Pull-ups

All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below).

. This

Input Diagram

Compiler Mode Selection

I/O Diagram

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.

The ATF16V8B can be configured in one of three different modes. Each mode makes the ATF16V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.

The ATF16V8B universal architecture can be programmed to emulate many 20-pin PAL devices. These architectural subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF16V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability.

Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse.

Registered Complex Simple Auto Select

ABEL, Atmel-ABEL P16V8R P16V8C P16V8AS P16V8

CUPL G16V8MS G16V8MA G16V8AS G16V8

LOG/iC GAL16V8_R

OrCAD-PLD “Registered”“Complex”“Simple” GAL16V8A

PLDesigner P16V8R P16V8C P16V8C P16V8A

Tango-PLD G16V8R G16V8C G16V8AS G16V8

Note: 1. Only applicable for version 3.4 or lower.

ATF16V8B(QL)

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GAL16V8_C7

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GAL16V8_C8

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GAL16V8

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