Rainbow Electronics AT45DB161D User Manual

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Features

• Single 2.5V - 3.6V or 2.7V - 3.6V Supply

• RapidS

• User Configurable Page Size

• Page Program Operation

• Flexible Erase Options

• Two SRAM Data Buffers (512-/528-Bytes)

• Continuous Read Capability through Entire Array

• Low-power Dissipation

• Hardware and Software Data Protection Features

• Sector Lockdown for Secure Code and Data Storage

• Security: 128-byte Security Register

• JEDEC Standard Manufacturer and Device ID Read

• 100,000 Program/Erase Cycles Per Page Minimum

• Data Retention – 20 Years

• Industrial Temperature Range

• Green (Pb/Halide-free/RoHS Compliant) Packaging Options

™

Serial Interface: 66MHz Maximum Clock Frequency

– SPI Compatible Modes 0 and 3

– 512-Bytes per Page – 528-Bytes per Page – Page Size Can Be Factory Pre-configured for 512-Bytes

– Intelligent Programming Operation – 4,096 Pages (512-/528-Bytes/Page) Main Memory

– Page Erase (512-Bytes) – Block Erase (4-Kbytes) – Sector Erase (128-Kbytes) – Chip Erase (16-Mbits)

– Allows Receiving of Data while Reprogramming the Flash Array

– Ideal for Code Shadowing Applications

– 7mA Active Read Current Typical – 25µA Standby Current Typical – 15µA Deep Power Down Typical

– Individual Sector

– 64-byte User Programmable Space – Unique 64-byte Device Identifier

16-megabit

2.5V or 2.7V DataFlash

AT45DB161D

1. Description

The AT45DB161D is a 2.5V or 2.7V, serial-interface sequential access Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB161D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies up to 66MHz. Its 17,301,504-bits of memory are organized as 4,096 pages of 512-bytes or 528-bytes each. In addition to the main memory, the AT45DB161D also contains two SRAM buffers of 512-/528-bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-write

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operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a

parallel interface, the Adesto DataFlash

uses a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, low-voltage and low-power are essential.

To allow for simple in-system reprogrammability, the AT45DB161D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB161D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

2. Pin Configurations and Pinouts

Figure 2-1. TSOP Top View: Type 1 Figure 2-2. BGA Package Ball-out

(Top View)

RDY/BUSY

RESET

NC NC

VCC

GND

NC NC NC CS

SCK

1 2 3 4 5 6 7 8 9 10 11 12 13

28 27 26 25 24 23 22 21 20 19 18 17 16 15

NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

CS RDY/BSY WP

NCNC

NC NC NC

SISO RESET

54321

NCVCCGNDSCK

Figure 2-3. MLF (VDFN) Top View Figure 2-4. SOIC Top View

SCK

RESET

Note: 1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND

AT45DB161D

SO GND VCC WP

SCK

RESET

1 2 3 4

GND

VCC

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Table 2-1. Pin Configurations

Symbol Name and Function

Chip Select: Asserting the

device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a high-impedance state. When the device is

SCK

deselected, data will not be accepted on the input pin (SI). A high-to-low transition on the

transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.

Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

CS pin selects the device. When the CS pin is deasserted, the

CS pin is required to start an operation, and a low-to-high

AT45DB161D

Asserte

d State Type

Low Input

– Input

RESET

RDY/

BUSY

Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.

Write Protect: When the Protection Register will be protected against program and erase operations regardless of whether the Enable Sector Protection command has been issued or not. The independently of the software controlled protection method. After the content of the Sector Protection Register cannot be modified.

If a program or erase command is issued to the device while the will simply ignore the command and perform no operation. The device will return to the idle state once the Lockdown command, however, will be recognized by the device when the

The not be used. However, it is recommended that the whenever possible.

Reset: A low state on the reset pin ( the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the is brought back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the

Ready/Busy: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, compare operations, and page-to-buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed.

CS pin has been deasserted. The Enable Sector Protection command and Sector

WP pin is internally pulled-high and may be left floating if hardware controlled protection will

RESET pin be driven high externally.

WP pin is asserted, all sectors specified for protection by the Sector

WP pin functions

WP pin goes low, the

WP pin is asserted, the device

WP pin is asserted.

WP pin also be externally connected to V

RESET) will terminate the operation in progress and reset

RESET pin. Normal operation can resume once the RESET pin

–

Low Input

–

Outpu

GND

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Device Power Supply: The VCCpin is used to supply the source voltage to the device. Operations at invalid V

Ground: The ground reference for the power supply. GND should be connected to the system ground.

voltages may produce spurious results and should not be attempted.

–Power

–

Groun

3. Block Diagram

SCK

RESET

VCC

GND

RDY/BUSY

4. Memory Array

To provide optimal flexibility, the memory array of the AT45DB161D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level.

FLASH MEMORY ARRAY

PAGE (512-/528-BYTES)

BUFFER 2 (512-/528-BYTES)BUFFER 1 (512-/528-BYTES)

I/O INTERFACE

SO SI

Figure 4-1. Memory Architecture Diagram

SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE

SECTOR 0a = 8 Pages

4,096-/4,224-bytes

SECTOR 0b = 248 Pages

126,976-/130,944-bytes

SECTOR 1 = 256 Pages

131,072-/135,168-bytes

SECTOR 2 = 256 Pages

131,072-/135,168-bytes

SECTOR 14 = 256 Pages

131,072-/135,168-bytes

SECTOR 15 = 256 Pages

131,072-/135,168-bytes

SECTOR 0

BLOCK 0

BLOCK 1

BLOCK 2

SECTOR 1

SECTOR 2

Block = 4,096-/4,224-bytes

BLOCK 30

BLOCK 31

BLOCK 32

BLOCK 33

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

BLOCK 510

BLOCK 511

8 Pages

BLOCK 0

BLOCK 1

PAGE 0

PAGE 1

PAGE 6

PAGE 7

PAGE 8

PAGE 9

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

PAGE 4,094

PAGE 4,095

Page = 512-/528-bytes

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5. Device Operation

The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 15-1 on page 27 through Table 15-7 on page 30. A valid instruction starts with the falling edge of address location. While the buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first.

Buffer addressing for standard DataFlash page size (528-bytes) is referenced in the datasheet using the terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0 denotes the 12 address bits required to designate a page address and BA9 - BA0 denotes the 10 address bits required to designate a byte address within the page.

For “Power of 2” binary page size (512-bytes) the Buffer addressing is referenced in the datasheet using the conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12 address bits required to designate a page address and A8 - A0 denotes the nine address bits required to designate a byte address within a page.

AT45DB161D

CS followed by the appropriate 8-bit opcode and the desired buffer or main memory

CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired

6. Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bitlevel Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode.

6.1 Continuous Array Read (Legacy Command: E8H): Up to 66MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read from the standard DataFlash page size (528-bytes), an opcode of E8H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four don’t care bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9 -

BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a continuous read from the binary page size (512-bytes), the opcode (E8H) must be clocked into the device followed by three address bytes and four don’t care bytes. The first 12 bits (A20 - A9) of the 21-bits sequence specify which page of the main memory array to read, and the last nine bits (A8 - A0) of the 21-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.

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A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66MHz

This command can be used with the serial interface to read the main memory array sequentially in high speed mode for any clock frequency up to the maximum specified by f page size set to 528-bytes, the

CS must first be asserted then an opcode 0BH must be clocked into the device followed by three address bytes and a dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a continuous read with the page size set to 512-bytes, the opcode, 0BH, must be clocked into the device followed by three address bytes (A20 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the f Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

. To perform a continuous read array with the

CAR1

specification. The

CAR1

specification. The

CAR1

6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz

This command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to maximum frequencies specified by f 528-bytes, the CS must first be asserted then an opcode, 03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence). The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a continuous read with the page size set to 512-bytes, the opcode, 03H, must be clocked into the device followed by three address bytes (A20 - A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

. To perform a continuous read array with the page size set to

CAR2

AT45DB161D

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6.4 Main Memory Page Read

A main memory page read allows the user to read data directly from any one of the 4,096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the standard DataFlash page size (528-bytes), an opcode of D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and four don’t care bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify the page in main memory to be read, and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within that page. To start a page read from the binary page size (512-bytes), the opcode D2H must be clocked into the device followed by three address bytes and four don’t care bytes. The first 12 bits (A20 - A9) of the 21-bits sequence specify which page of the main memory array to read, and the last nine bits (A8 - A0) of the 21-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are sent to initialize the read operation. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output) pin. The bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the f and leaves the contents of the buffers unchanged.

AT45DB161D

CS pin must remain low during the loading of the opcode, the address

specification. The Main Memory Page Read bypasses both data buffers

SCK

6.5 Buffer Read

The SRAM data buffers can be accessed independently from the main memory array, and utilizing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to the maximum specified by f frequency read operations up to the maximum specified by f

To perform a buffer read from the standard DataFlash buffer (528-bytes), the opcode must be clocked into the device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). To perform a buffer read from the binary buffer (512-bytes), the opcode must be clocked into the device followed by three address bytes comprised of 15 don’t care bits and nine buffer address bits (BFA8 - BFA0). Following the address bytes, one don’t care byte must be clocked in to initialize the read operation. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO).

. The D1H and D3H opcode can be used for lower

CAR1

CAR2

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7. Program and Erase Commands

7.1 Buffer Write

Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the standard DataFlash buffer (528-bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). The 10 buffer address bits specify the first byte in the buffer to be written. To load data into the binary buffers (512bytes each), a 1-byte opcode 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits and nine buffer address bits (BFA8 - BFA0). The nine buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-tohigh transition is detected on the

7.2 Buffer to Main Memory Page Program with Built-in Erase

Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the standard DataFlash page size (528-bytes), the opcode must be followed by three address bytes consist of two don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written and 10 don’t care bits. To perform a buffer to main memory page program with built-in erase for the binary page size (512-bytes), the opcode 83H for buffer 1 or 86H for buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits 12 page address bits (A20 - A9) that specify the page in the main memory to be written and nine don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

CS pin.

7.3 Buffer to Main Memory Page Program without Built-in Erase

A previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device. For the standard DataFlash page size (528-bytes), the opcode must be followed by three address bytes consist of two don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be written and 10 don’t care bits. To perform a buffer to main memory page program without built-in erase for the binary page size (512-bytes), the opcode 88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written and nine don’t care bits. When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of tP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

7.4 Page Erase

The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the standard DataFlash page size (528-bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of two don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory to be erased and 10 don’t care bits. To perform a page erase in the binary page size (512-bytes), the opcode 81H must be loaded into the device, followed by three address bytes consist of three don’t care bits, 12

AT45DB161D

3500O–DFLASH–11/2012

page address bits (A20 - A9) that specify the page in the main memory to be erased and nine don’t care bits. When a low-to-high transition occurs on the The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the status register and the RDY/

7.5 Block Erase

A block of eight pages can be erased at one time. This command is useful when large amounts of data has to be written into the device. This will avoid using multiple Page Erase Commands. To perform a block erase for the standard DataFlash page size (528-bytes), an opcode of 50H must be loaded into the device, followed by three address bytes comprised of two don’t care bits, nine page address bits (PA11 -PA3) and 13 don’t care bits. The nine page address bits are used to specify which block of eight pages is to be erased. To perform a block erase for the binary page size (512-bytes), the opcode 50H must be loaded into the device, followed by three address bytes consisting of three don’t care bits, nine page address bits (A20 - A12) and 12 don’t care bits. The nine page address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs on the should take place in a maximum time of t indicate that the part is busy.

Table 7-1. Block Erase Addressing

CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and

CS pin, the part will erase the selected page (the erased state is a logical 1).

BUSY pin will indicate that the part is busy.

. During this time, the status register and the RDY/BUSY pin will

AT45DB161D

PA11/

A20

PA10/

A19

000000000XXX 0

000000001XXX 1

000000010XXX 2

000000011XXX 3

•

111111100XXX 508

111111101XXX 509

111111110XXX 510

111111111XXX 511

•

7.6 Sector Erase

The Sector Erase command can be used to individually erase any sector in the main memory. There are 16 sectors and only one sector can be erased at one time. To perform sector 0a or sector 0b erase for the standard DataFlash page size (528-bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of two don’t care bits, nine page address bits (PA11 - PA3) and 13 don’t care bits. To perform a sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of two don’t care bits, four page address bits (PA11 - PA8) and 18 don’t care bits. To perform sector 0a or sector 0b erase for the binary page size (512-bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of three don’t care bit and nine page address bits (A20 - A12) and 12 don’t care bits. To perform a sector 1-15 erase, the opcode 7CH must be loaded into the device, followed by three address bytes comprised of 3 don’t care bit and four page address bits (A20 - A17) and 17 don’t care bits. The page address bits are used to specify any valid address location within the sector which is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected sector. The erase operation is internally self-timed and should

PA9/

A18

•

PA8/

A17

•

PA7/

A16

•

PA6/

A15

•

PA5/

A14

•

PA4/

A13

•

PA3/

A12

•

PA2/

A11

•

PA1/

A10

•

PA0/

A9 Block

•

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take place in a maximum time of tSE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

Table 7-2. Sector Erase Addressing

PA11/

A20

PA10/

A19

000000000XXX 0a

000000001XXX 0b

00 01XXXXXXXX 1

00 10XXXXXXXX 2

•

11 00XXXXXXXX 12

11 01XXXXXXXX 13

11 10XXXXXXXX 14

11 11XXXXXXXX 15

•

7.7 Chip Erase

The entire main memory can be erased at one time by using the Chip Erase command.

To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deasserted to start the erase process. The erase operation is internally self-timed and should take place in a time of tCE. During this time, the Status Register will indicate that the device is busy.

(1)

PA9/

A18

•

PA8/

A17

•

PA7/

A16

•

PA6/

A15

•

PA5/

A14

•

PA4/

A13

•

PA3/

A12

•

PA2/

A11

•

PA1/

A10

•

PA0/

A9 Sector

•

The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased.

Note: 1. Refer to the errata regarding Chip Erase on page 50.

The WP pin can be asserted while the device is erasing, but protection will not be activated until the internal erase cycle completes.

Table 7-3. Chip Erase Command

Command Byte 1 Byte 2 Byte 3 Byte 4

Chip Erase C7H 94H 80H 9AH

Figure 7-1. Chip Erase

Each transition represents eight bits

Note: 1. Refer to the errata regarding Chip Erase on page 50

Opcode

Byte 1

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

AT45DB161D

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7.8 Main Memory Page Program Through Buffer

This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a specified page in the main memory. To perform a main memory page program through buffer for the standard DataFlash page size (528-bytes), a 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of two don’t care bits, 12 page address bits, (PA11 - PA0) that select the page in the main memory where data is to be written, and 10 buffer address bits (BFA9 - BFA0) that select the first byte in the buffer to be written. To perform a main memory page program through buffer for the binary page size (512-bytes), the opcode 82H for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits (A20 - A9) that specify the page in the main memory to be written, and 9 buffer address bits (BFA8 - BFA0) that selects the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of t

. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

8. Sector Protection

Two protection methods, hardware and software controlled, are provided for protection against inadvertent or erroneous program and erase cycles. The software controlled method relies on the use of software commands to enable and disable sector protection while the hardware controlled method employs the use of the Write Protect (WP) pin. The selection of which sectors that are to be protected or unprotected against program and erase operations is specified in the nonvolatile Sector Protection Register. The status of whether or not sector protection has been enabled or disabled by either the software or the hardware controlled methods can be determined by checking the Status Register.

AT45DB161D

8.1 Software Sector Protection

8.1.1 Enable Sector Protection Command

Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector protection will be enabled.

Table 8-1. Enable Sector Protection Command

Command Byte 1 Byte 2 Byte 3 Byte 4

Enable Sector Protection 3DH 2AH 7FH A9H

Figure 8-1. Enable Sector Protection

Opcode

Byte 1

Each transition represents eight bits

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

3500O–DFLASH–11/2012

8.1.2 Disable Sector Protection Command

To disable the sector protection using the software controlled method, the be with any other command. Once the Sector Protection command must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the

CS pin must be deasserted after which the sector protection will be disabled. The WP pin

must be in the deasserted state; otherwise, the Disable Sector Protection command will be ignored.

Table 8-2. Disenable Sector Protection Command

Command Byte 1 Byte 2 Byte 3 Byte 4

Disable Sector Protection 3DH 2AH 7FH 9AH

Figure 8-2. Disable Sector Protection

CS pin must first be asserted as it would

CS pin has been asserted, the appropriate 4-byte sequence for the Disable

Opcode

Byte 1

Each transition represents eight bits

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

8.1.3 Various Aspects About Software Controlled Protection

Software controlled protection is useful in applications in which the processor. In such instances, the WP pin may be left floating (the WP pin is internally pulled high) and sector protection can be controlled using the Enable Sector Protection and Disable Sector Protection commands.

If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector protection is desired and if the WP pin is not used.

9. Hardware Controlled Protection

Sectors specified for protection in the Sector Protection Register and the Sector Protection Register itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted state. The Sector Protection Register and any sector specified for protection cannot be erased or reprogrammed as long as the WP pin is asserted. In order to modify the Sector Protection Register, the WP pin must be deasserted. If the WP pin is permanently connected to GND, then the content of the Sector Protection Register cannot be changed. If the WP pin is deasserted, or permanently connected to VCC, then the content of the Sector Protection Register can be modified.

WP pin is not or cannot be controlled by a host

The WP pin will override the software controlled protection method but only for protecting the sectors. For example, if the sectors were not previously protected by the Enable Sector Protection command, then simply asserting the WP pin would enable the sector protection within the maximum specified t deasserted; however, the sector protection would no longer be enabled (after the maximum specified t

time. When the WP pin is

WPE

WPD

time) as long as the Enable Sector Protection command was not issued while the WP pin was asserted. If the Enable Sector Protection command was issued before or while the WP pin was asserted, then simply deasserting the WP pin would not disable the sector protection. In this case, the Disable Sector Protection command would need to be issued while the WP pin is deasserted to disable the sector protection. The Disable Sector Protection command is also ignored whenever the WP pin is asserted.

A noise filter is incorporated to help protect against spurious noise that may inadvertently assert or deassert the WP pin.

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AT45DB161D

The table below details the sector protection status for various scenarios of the WP pin, the Enable Sector Protection command, and the Disable Sector Protection command.

Figure 9-1.

WP Pin and Protection Status

Table 9-1.

Time

Period

1 High

2 Low X X Enabled Read Only

3 High

WP Pin and Protection Status

WP Pin Enable Sector Protection Command

Command Not Issued Previously

Issue Command

Command Issued During Period 1 or 2

Issue Command

9.1 Sector Protection Register

The nonvolatile Sector Protection Register specifies which sectors are to be protected or unprotected with either the software or hardware controlled protection methods. The Sector Protection Register contains 16-bytes of data, of which byte locations 0 through 15 contain values that specify whether sectors 0 through 15 will be protected or unprotected. The Sector Protection Register is user modifiable and must first be erased before it can be reprogrammed. Table 9-3 illustrates the format of the Sector Protection Register.:

Sector

Disable Sector

Protection Command

–

Issue Command

–

Not Issued Yet

Issue Command

–

Protection

Status

Disabled Disabled

Enabled

Disabled

Enabled

Sector

Protection

Read/Write Read/Write Read/Write

Table 9-2. Sector Protection Register

Sector Number 0 (0a, 0b) 1 to 15

Protected

See Table 9-3

Unprotected 00H

FFH

Table 9-3. Sector 0 (0a, 0b)

0a 0b

(Page 0-7) (Page 8-255)

Bit7,6 Bit5,4 Bit1,0

Sectors 0a, 0b Unprotected 00 00 xx xx 0xH

Protect Sector 0a 11 00 xx xx CxH

Protect Sector 0b (Page 8-255) 00 11 xx xx 3xH

Protect Sectors 0a (Page 0-7), 0b (Page 8-255)

Note: 1. The default value for bytes 0 through 15 when shipped from Adesto is 00H

x = don’t care

(1)

11 11 xx xx FxH

Bit3,2

Value

Data

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9.1.1 Erase Sector Protection Register Command

In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command.

To erase the Sector Protection Register, the

CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and CFH. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed erase cycle. The erasing of the Sector Protection Register should take place in a time of t

, during which time the

Status Register will indicate that the device is busy. If the device is powered-down before the completion of the erase cycle, then the contents of the Sector Protection Register cannot be guaranteed.

The Sector Protection Register can be erased with the sector protection enabled or disabled. Since the erased state (FFH) of each byte in the Sector Protection Register is used to indicate that a sector is specified for protection, leaving the sector protection enabled during the erasing of the register allows the protection scheme to be more effective in the prevention of accidental programming or erasing of the device. If for some reason an erroneous program or erase command is sent to the device immediately after erasing the Sector Protection Register and before the register can be reprogrammed, then the erroneous program or erase command will not be processed because all sectors would be protected.

Table 9-4. Erase Sector Protection Register Command

Command Byte 1 Byte 2 Byte 3 Byte 4

Erase Sector Protection Register 3DH 2AH 7FH CFH

Figure 9-2. Erase Sector Protection Register

Opcode

Byte 1

Each transition represents eight bits

Opcode

Byte 2

Opcode

Byte 3

9.1.2 Program Sector Protection Register Command

Once the Sector Protection Register has been erased, it can be reprogrammed using the Program Sector Protection Register command.

To program the Sector Protection Register, the CS pin must first be asserted and the appropriate 4-byte opcode sequence must be clocked into the device via the SI pin. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and FCH. After the last bit of the opcode sequence has been clocked into the device, the data for the contents of the Sector Protection Register must be clocked in. As described in Section 9.1, the Sector Protection Register contains 16-bytes of data, so 16-bytes must be clocked into the device. The first byte of data corresponds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data corresponding to sector 15.

After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Sector Protection Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. If the device is powered-down during the program cycle, then the contents of the Sector Protection Register cannot be guaranteed.

If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed. For example, if only the first two bytes are clocked in instead of the complete 16-bytes, then the protection status of the last 14 sectors cannot be

Opcode

Byte 4

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AT45DB161D

guaranteed. Furthermore, if more than 16-bytes of data is clocked into the device, then the data will wrap back

around to the beginning of the register. For instance, if 17-bytes of data are clocked in, then the 17

byte will be

stored at byte location 0 of the Sector Protection Register.

If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register, then the protection status of the sector corresponding to that byte location cannot be guaranteed. For example, if a value of 17H is clocked into byte location 2 of the Sector Protection Register, then the protection status of sector 2 cannot be guaranteed.

The Sector Protection Register can be reprogrammed while the sector protection enabled or disabled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than disabling sector protection completely.

The Program Sector Protection Register command utilizes the internal SRAM buffer 1 for processing. Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued.

Table 9-5. Program Sector Protection Register Command

Command Byte 1 Byte 2 Byte 3 Byte 4

Program Sector Protection Register 3DH 2AH 7FH FCH

Figure 9-3. Program Sector Protection Register

Opcode

Byte 1

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

Data Byte

n + 1

Data Byte

n + 15

Each transition represents eight bits

9.1.3 Read Sector Protection Register Command

To read the Sector Protection Register, the

CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 32H and three dummy bytes must be clocked in via the SI pin. After the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the SCK pins will result in data for the content of the Sector Protection Register being output on the SO pin. The first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sector 1 and the last byte (byte 16) corresponds to sector 15. Once the last byte of the Sector Protection Register has been clocked out, any additional clock pulses will result in undefined data being output on the SO pin. The CS must be deasserted to terminate the Read Sector Protection Register operation and put the output into a high-impedance state.

Table 9-6. Read Sector Protection Register Command

Command Byte 1 Byte 2 Byte 3 Byte 4

Read Sector Protection Register 32H xxH xxH xxH

Note: xx = Dummy Byte

Figure 9-4. Read Sector Protection Register

Opcode X X X

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Each transition represents eight bits

Data Byte n Data Byte

n + 1

Data Byte

n + 15

9.1.4 Various Aspects About the Sector Protection Register

The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are encouraged to carefully evaluate the number of times the Sector Protection Register will be modified during the course of the applications’ life cycle. If the application requires that the Sector Protection Register be modified more than the specified limit of 10,000 cycles because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a combination of temporarily unprotecting individual sectors along with disabling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded.

10. Security Features

10.1 Sector Lockdown

The device incorporates a Sector Lockdown mechanism that allows each individual sector to be permanently locked so that it becomes read only. This is useful for applications that require the ability to permanently protect a number of sectors against malicious attempts at altering program code or security information. Onceasectoris

locked down, it can never be erased or programmed, and it can never be unlocked.

To issue the Sector Lockdown command, the CS pin must first be asserted as it would be for any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and 30H. After the last byte of the command sequence has been clocked in, then three address bytes specifying any address within the sector to be locked down must be clocked into the device. After the last address bit has been clocked in, the CS pin must then be deasserted to initiate the internally self-timed lockdown sequence.

The lockdown sequence should take place in a maximum time of tP, during which time the Status Register will indicate that the device is busy. If the device is powered-down before the completion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. In this case, it is recommended that the user read the Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown command if necessary.

Table 10-1. Sector Lockdown

Command Byte 1 Byte 2 Byte 3 Byte 4

Sector Lockdown 3DH 2AH 7FH 30H

Figure 10-1. Sector Lockdown

Each transition represents eight bits

Opcode

Byte 1

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

Address

Bytes

Address

Bytes

Address

Bytes

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10.1.1 Sector Lockdown Register

Sector Lockdown Register is a nonvolatile register that contains 16-bytes of data, as shown below:

Table 10-2. Sector Lockdown Register

Sector Number 0 (0a, 0b) 1 to 15

AT45DB161D

Locked

Unlocked 00H

Table 10-3. Sector 0 (0a, 0b)

Sectors 0a, 0b Unlocked 00 00 00 00 00H

Sector 0a Locked (Page 0-7) 11 00 00 00 C0H

Sector 0b Locked (Page 8-255) 00 11 00 00 30H

Sectors 0a, 0b Locked (Page 0-255) 11 11 00 00 F0H

10.1.2 Reading the Sector Lockdown Register

The Sector Lockdown Register can be read to determine which sectors in the memory array are permanently locked down. To read the Sector Lockdown Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 35H and three dummy bytes must be clocked into the device via the SI pin. After the last bit of the opcode and dummy bytes have been clocked in, the data for the contents of the Sector Lockdown Register will be clocked out on the SO pin. The first byte corresponds to sector 0 (0a, 0b) the second byte corresponds to sector 1 and the las byte (byte 16) corresponds to sector 15. After the last byte of the Sector Lockdown Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pin.

See Below

0a 0b

(Page 0-7) (Page 8-255)

Bit7,6 Bit5,4 Bit1,0

Bit3,2

FFH

Data

Value

Deasserting the CS pin will terminate the Read Sector Lockdown Register operation and put the SO pin into a high-impedance state.

Table 10-4 details the values read from the Sector Lockdown Register.

Table 10-4. Sector Lockdown Register

Command Byte 1 Byte 2 Byte 3 Byte 4

Read Sector Lockdown Register 35H xxH xxH xxH

Note: xx = Dummy Byte

Figure 10-2. Read Sector Lockdown Register

Opcode X X X

Each transition represents eight bits

Data Byte n Data Byte

n + 1

Data Byte

n + 15

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10.2 Security Register

The device contains a specialized Security Register that can be used for purposes such as unique device serialization or locked key storage. The register is comprised of a total of 128-bytes that is divided into two portions. The first 64-bytes (byte locations 0 through 63) of the Security Register are allocated as a one-time user programmable space. Once these 64-bytes have been programmed, they cannot be reprogrammed. The remaining 64-bytes of the register (byte locations 64 through 127) are factory programmed by Adesto and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed.

Table 10-5. Security Register

0 1 · · · 62 63 64 65 · · · 126 127

Data Type One-time User Programmable Factory Programmed By Adesto

10.2.1 Programming the Security Register

The user programmable portion of the Security Register does not need to be erased before it is programmed.

Security Register Byte Number

To program the Security Register, the

CS pin must first be asserted and the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-byte opcode sequence must start with 9BH and be followed by 00H, 00H, and 00H. After the last bit of the opcode sequence has been clocked into the device, the data for the contents of the 64-byte user programmable portion of the Security Register must be clocked in.

After the last data byte has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Security Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. If the device is powered-down during the program cycle, then the contents of the 64-byte user programmable portion of the Security Register cannot be guaranteed.

If the full 64-bytes of data is not clocked in before the CS pin is deasserted, then the values of the byte locations not clocked in cannot be guaranteed. For example, if only the first two bytes are clocked in instead of the complete 64-bytes, then the remaining 62-bytes of the user programmable portion of the Security Register cannot be guaranteed. Furthermore, if more than 64-bytes of data is clocked into the device, then the data will wrap back around to the beginning of the register. For instance, if 65-bytes of data are clocked in, then the 65thbyte will be stored at byte location 0 of the Security Register.

The user programmable portion of the Security Register can only be programmed one time. Therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62-bytes at a later time.

The Program Security Register command utilizes the internal SRAM buffer 1 for processing. Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued.

Figure 10-3. Program Security Register

Each transition represents eight bits

Opcode

Byte 1

AT45DB161D

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

Data Byte

n + 1

Data Byte

n + x

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10.2.2 Reading the Security Register

The Security Register can be read by first asserting the three dummy bytes. After the last don't care bit has been clocked in, the content of the Security Register can be clocked out on the SO pins. After the last byte of the Security Register has been read, additional pulses on the SCK pin will simply result in undefined data being output on the SO pins.

AT45DB161D

CS pin and then clocking in an opcode of 77H followed by

Deasserting the

CS pin will terminate the Read Security Register operation and put the SO pins into a high-

impedance state.

Figure 10-4. Read Security Register

Opcode X X X

Each transition represents eight bits

11. Additional Commands

11.1 Main Memory Page to Buffer Transfer

A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation for the standard DataFlash page size (528-bytes), a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes comprised of two don’t care bits, 12 page address bits (PA11 PA0), which specify the page in main memory that is to be transferred, and 10 don’t care bits. To perform a main memory page to buffer transfer for the binary page size (512-bytes), the opcode 53H for buffer 1 or 55H for buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits (A20 - A9) which specify the page in the main memory that is to be transferred, and nine don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (t RDY/BUSY can be monitored to determine whether the transfer has been completed.

Data Byte n Data Byte

n + 1

), the status register can be read or the

XFR

Data Byte

n + x

11.2 Main Memory Page to Buffer Compare

A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation for standard DataFlash page size, a 1-byte opcode, 60H for buffer 1 and 61H for buffer 2, must be clocked into the device, followed by three address bytes consisting of two don’t care bits, 12 page address bits (PA11 - PA0) that specify the page in the main memory that is to be compared to the buffer, and 10 don’t care bits. To start a main memory page to buffer compare for a binary page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits (A20 - A9) that specify the page in the main memory that is to be compared to the buffer, and nine don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. During this time (t indicate that the part is busy. On completion of the compare operation, bit six of the status register is updated with the result of the compare.

3500O–DFLASH–11/2012

), the status register and the RDY/BUSY pin will

COMP

11.3 Auto Page Rewrite

This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion within a sector. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the rewrite operation for standard DataFlash page size (528-bytes), a 1-byte opcode, 58H for buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes comprised of two don’t care bits, 12 page address bits (PA11-PA0) that specify the page in main memory to be rewritten and 10 don’t care bits. To initiate an auto page rewrite for a binary page size (512-bytes), the opcode 58H for buffer 1 or 59H for buffer 2, must be clocked into the device followed by three address bytes consisting of three don’t care bits, 12 page address bits (A20 - A9) that specify the page in the main memory that is to be written and nine don’t care bits. When a low-to-high transition occurs on the a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of t RDY/

BUSY pin will indicate that the part is busy.

If a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in

Figure 25-1 (page 42) is recommended. Otherwise, if multiple bytes in a page or several pages are programmed

randomly in a sector, then the programming algorithm shown in Figure 25-2 (page 43) is recommended. Each page within a sector must be updated/rewritten at least once within every 20,000 cumulative page erase/program operations in that sector. Please contact Adesto for availability of devices that are specified to exceed the 20K cycle cumulative limit.

CS pin, the part will first transfer data from the page in main memory to

. During this time, the status register and the

11.4 Status Register Read

The status register can be used to determine the device’s ready/busy status, page size, a Main Memory Page to Buffer Compare operation result, the Sector Protection status or the device density. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the status register, the CS pin must be asserted and the opcode of D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status register will be clocked out on the output pin (SO), starting with the next clock cycle. The data in the status register, starting with the MSB (bit seven), will be clocked out on the SO pin during the next eight clock cycles. After the one byte of the status register has been clocked out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled). The data in the status register is constantly updated, so each repeating sequence will output new data.

Ready/busy status is indicated using bit seven of the status register. If bit seven is a one, then the device is not busy and is ready to accept the next command. If bit seven is a zero, then the device is in a busy state. Since the data in the status register is constantly updated, the user must toggle SCK pin to check the ready/busy status. There are several operations that can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program, Main Memory Page Program through Buffer, Page Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite.

The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit six is a zero, then the data in the main memory page matches the data in the buffer. If bit six is a one, then at least one bit of the data in the main memory page does not match the data in the buffer.

Bit one in the Status Register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-controlled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled.

Bit zero in the Status Register indicates whether the page size of the main memory array is configured for “power of 2” binary page size (512-bytes) or standard DataFlash page size (528-bytes). If bit zero is a one, then the page size is set to 512-bytes. If bit zero is a zero, then the page size is set to 528-bytes.

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3500O–DFLASH–11/2012

The device density is indicated using bits five, four, three, and two of the status register. For the AT45DB161D, the four bits are 1011 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The device density is not the same as the density code indicated in the JEDEC device ID information. The device density is provided only for backward compatibility.

Table 11-1. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BUSY COMP 1 0 1 1 PROTECT PAGE SIZE

RDY/

12. Deep Power-down

After initial power-up, the device will default in standby mode. The Deep Power-down command allows the device to enter into the lowest power consumption mode. To enter the Deep Power-down mode, the asserted. Once the After the last bit of the command has been clocked in, the CS pin must be de-asserted to initiate the Deep Powerdown operation. After the CS pin is de-asserted, the will device enter the Deep Power-down mode within the maximum t

EDPD

for the Resume from Deep Power-down command.

CS pin has been asserted, an opcode of B9H command must be clocked in via input pin (SI).

time. Once the device has entered the Deep Power-down mode, all instructions are ignored except

AT45DB161D

CS pin must first be

Table 12-1. Deep Power-down

Command Opcode

Deep Power-down B9H

Figure 12-1. Deep Power-down

Each transition represents eight bits

Opcode

12.1 Resume from Deep Power-down

The Resume from Deep Power-down command takes the device out of the Deep Power-down mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the CS pin must first be asserted and an opcode of ABH command must be clocked in via input pin (SI). After the last bit of the command has been clocked in, the CS pin must be de-asserted to terminate the Deep Power-down mode. After the CS pin is de-asserted, the device will return to the normal standby mode within the maximum t the t will return to the normal standby mode.

Table 12-2. Resume from Deep Power-down

time before the device can receive any commands. After resuming form Deep Power-down, the device

RDPD

time. The CS pin must remain high during

RDPD

Command Opcode

Resume from Deep Power-down ABH

3500O–DFLASH–11/2012

Figure 12-2. Resume from Deep Power-Down

Each transition represents eight bits

Opcode

13. “Power of 2” Binary Page Size Option

“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile register that allows the page size of the main memory to be configured for binary page size (512-bytes) or standard DataFlash page size (528-bytes). The “power of 2” page size is a one-time programmable configuration register and once the device is configured for “power of 2” page size, it cannot be reconfigured again. The devices are initially shipped with the page size set to 528-bytes. The user has the option of ordering binary page size (512 bytes) devices from the factory. For details, please refer to Section 26. “Ordering Information” on page 44.

For the binary “power of 2” page size to become effective, the following steps must be followed:

1. Program the one-time programmable configuration resister using opcode sequence 3DH, 2AH, 80H and A6H (please see Section 13.1).

2. Power cycle the device (i.e. power down and power up again).

3. User can now program the page for the binary page size.

If the above steps are not followed in setting the the page size prior to page programming, user may expect incorrect data during a read operation.

13.1 Programming the Configuration Register

To program the Configuration Register for “power of 2” binary page size, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle. The programming of the Configuration Register should take place in a time of tP, during which time the Status Register will indicate that the device is busy. The device must be power cycled after the completion of the program cycle to set the “power of 2” page size. If the device is powered-down before the completion of the program cycle, then setting the Configuration Register cannot be guaranteed. However, the user should check bit zero of the status register to see whether the page size was configured for binary page size. If not, the command can be re-issued again.

Table 13-1. Programming the Configuration Register

Command Byte 1 Byte 2 Byte 3 Byte 4

Power of Two Page Size 3DH 2AH 80H A6H

Figure 13-1. Erase Sector Protection Register

Opcode

Byte 1

Each transition represents eight bits

Opcode

Byte 2

Opcode

Byte 3

Opcode

Byte 4

AT45DB161D

3500O–DFLASH–11/2012

14. Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information.

AT45DB161D

To read the identification information, the

CS pin must first be asserted and the opcode of 9FH must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00H indicating that no Extended Device Information follows. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional.

Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put the SO pin into a high-impedance state. The

CS pin can be deasserted at any time and does not require that a full byte of data be

read.

14.1 Manufacturer and Device ID Information

Hex

Value

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1FH 0 0 0 1 1 1 1 1 Manufacturer ID 1FH = Adesto

Hex

Value

Family Code Density Code

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

26H 0 0 1 0 0 1 1 0 Density Code 00110 = 16-Mbit

Hex

Value

MLC Code Product Version Code

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00H 0 0 0 0 0 0 0 0 Product Version 00000 = Initial Version

JEDEC Assigned Code

Family Code 001 = DataFlash

MLC Code 000 = 1-bit/Cell Technology

Hex

Value

00H 0 0 0 0 0 0 0 0 Byte Count 00H = 0 Bytes of Information

Each transition represents 8 bits

Note: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers

3500O–DFLASH–11/2012

Byte Count

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

9FH

Opcode

1FH

Manufacturer ID

Byte 1

26H 00H

Device ID

Byte 2

Device ID

Byte 3

00H Data Data

Extended

Device

Information

String Length

Extended

Device

Information

Byte x

This information would only be output

if the Extended Device Information String Length

value was something other than 00H.

Extended

Device

Information

Byte x + 1

may have Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Adesto (and some other manufacturers), the Manufacturer ID data is comprised of only one byte.

14.2 Operation Mode Summary

The commands described previously can be grouped into four different categories to better describe which commands can be executed at what times.

Group A commands consist of:

1. Main Memory Page Read

2. Continuous Array Read

3. Read Sector Protection Register

4. Read Sector Lockdown Register

5. Read Security Register

Group B commands consist of:

1. Page Erase

2. Block Erase

3. Sector Erase

4. Chip Erase

5. Main Memory Page to Buffer 1 (or 2) Transfer

6. Main Memory Page to Buffer 1 (or 2) Compare

7. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase

8. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase

9. Main Memory Page Program through Buffer 1 (or 2)

10. Auto Page Rewrite

Group C commands consist of:

1. Buffer 1 (or 2) Read

2. Buffer 1 (or 2) Write

3. Status Register Read

4. Manufacturer and Device ID Read

Group D commands consist of:

1. Erase Sector Protection Register

2. Program Sector Protection Register

3. Sector Lockdown

4. Program Security Register

If a Group A command is in progress (not fully completed), then another command in Group A, B, C, or D should not be started. However, during the internally self-timed portion of Group B commands, any command in Group C can be executed. The Group B commands using buffer 1 should use Group C commands using buffer 2 and vice versa. Finally, during the internally self-timed portion of a Group D command, only the Status Register Read command should be executed.

AT45DB161D

3500O–DFLASH–11/2012

15. Command Tables

Table 15-1. Read Commands

Command Opcode

Main Memory Page Read D2H

Continuous Array Read (Legacy Command) E8H

Continuous Array Read (Low Frequency) 03H

Continuous Array Read (High Frequency) 0BH

Buffer 1 Read (Low Frequency) D1H

Buffer 2 Read (Low Frequency) D3H

Buffer 1 Read D4H

Buffer 2 Read D6H

Table 15-2. Program and Erase Commands

Command Opcode

Buffer 1 Write 84H

AT45DB161D

Buffer 2 Write 87H

Buffer 1 to Main Memory Page Program with Built-in Erase 83H

Buffer 2 to Main Memory Page Program with Built-in Erase 86H

Buffer 1 to Main Memory Page Program without Built-in Erase 88H

Buffer 2 to Main Memory Page Program without Built-in Erase 89H

Page Erase 81H

Block Erase 50H

Sector Erase 7CH

Chip Erase C7H, 94H, 80H, 9AH

Main Memory Page Program Through Buffer 1 82H

Main Memory Page Program Through Buffer 2 85H

Table 15-3. Protection and Security Commands

Command Opcode

Enable Sector Protection 3DH + 2AH + 7FH + A9H

Disable Sector Protection 3DH + 2AH + 7FH + 9AH

Erase Sector Protection Register 3DH + 2AH + 7FH + CFH

Program Sector Protection Register 3DH + 2AH + 7FH + FCH

Read Sector Protection Register 32H

Sector Lockdown 3DH + 2AH + 7FH + 30H

Read Sector Lockdown Register 35H

Program Security Register 9BH + 00H + 00H + 00H

Read Security Register 77H

3500O–DFLASH–11/2012

Table 15-4. Additional Commands

Command Opcode

Main Memory Page to Buffer 1 Transfer 53H

Main Memory Page to Buffer 2 Transfer 55H

Main Memory Page to Buffer 1 Compare 60H

Main Memory Page to Buffer 2 Compare 61H

Auto Page Rewrite through Buffer 1 58H

Auto Page Rewrite through Buffer 2 59H

Deep Power-down B9H

Resume from Deep Power-down ABH

Status Register Read D7H

Manufacturer and Device ID Read 9FH

Table 15-5. Legacy Commands

Command Opcode

Buffer 1 Read 54H

Buffer 2 Read 56H

Main Memory Page Read 52H

Continuous Array Read 68H

Status Register Read

Notes: 1. These legacy commands are not recommended for new designs

2. Refer to the Revision History table on page 49

(2)

(1)

57H

AT45DB161D

3500O–DFLASH–11/2012

AT45DB161D

Table 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (512-Bytes)

Page Size = 512-bytes Address Byte Address Byte Address Byte

Opco

de Opcode

03h 0 0 0 0 0 0 1 1 x x x AAAAA AAAAAAAA AAAAAAAA

0Bh 0 0 0 0 1 0 1 1 x x x AAAAA AAAAAAAA AAAAAAAA

50h 01010000 xxxAAAAA AAAAxxxx xxxxxxx x

53h 0 1 0 1 0 0 1 1 x x x AAAAA AAAAAAAx xx x x x x x x

55h 0 1 0 1 0 1 0 1 x x x AAAAA AAAAAAAx xx x x x x x x

58h 0 1 0 1 1 0 0 0 x x x AAAAA AAAAAAAx xx x x x x x x

59h 0 1 0 1 1 0 0 1 x x x AAAAA AAAAAAAx xx x x x x x x

60h 0 1 1 0 0 0 0 0 x x x AAAAA AAAAAAAx xx x x x x x x

61h 0 1 1 0 0 0 0 1 x x x AAAAA AAAAAAAx xx x x x x x x

77h 01110111 xxxxxxxx xxxxxxxx xxxxxxx x

7Ch 01111100 xxxAAAAx xxxxxxxx xxxxxxx x

81h 1 0 0 0 0 0 0 1 x x x AAAAA AAAAAAAX x x x x x x x x

82h 1 0 0 0 0 0 1 0 x x x AAAAA AAAAAAAA AAAAAAAA

83h 1 0 0 0 0 0 1 1 x x x AAAAA AAAAAAAX x x x x x x x x

84h 10000100 xxxxxxxx xxxxxxxA AAAAAAAA

85h 1 0 0 0 0 1 0 1 x x x AAAAA AAAAAAAA AAAAAAAA

86h 1 0 0 0 0 1 1 0 x x x AAAAA AAAAAAAx xx x x x x x x

87h 10000111 xxxxxxxx xxxxxxxA AAAAAAAA

88h 1 0 0 0 1 0 0 0 x x x AAAAA AAAAAAAx xx x x x x x x

89h 1 0 0 0 1 0 0 1 x x x AAAAA AAAAAAAx xx x x x x x x

9Fh 1 0 0 1 1 1 1 1 N/A N/A N/A

B9h 1 0 1 1 1 0 0 1 N/A N/A N/A

ABh 1 0 1 0 1 0 1 1 N/A N/A N/A

D1h 11010001 xxxxxxxx xxxxxxxAAAAAAAAA

D2h 1 1 0 1 0 0 1 0 xx x AAAAA AAAAAAAA AAAAAAAA

D3h 11010011 xxxxxxxx xxxxxxxAAAAAAAAA

D4h 11010100 xxxxxxxx xxxxxxxAAAAAAAAA

D6h 11010110 xxxxxxxx xxxxxxxAAAAAAAAA

D7h 11010111 N/A N/A N/A

E8h 1 1 1 0 1 0 0 0 x x x AAAAA AAAAAAAA AAAAAAAA

Notes: x = Don’t Care

Reserved

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10A9A8A7A6A5A4A3A2A1A0

Additional

Don’t Care

Bytes

N/A

3500O–DFLASH–11/2012

Table 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528-Bytes)

Page Size = 528-bytes Address Byte Address Byte Address Byte

Reserved

PA11

PA10

PA9

PA8

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

BA9

BA8

BA7

BA6

BA5

BA4

BA3

03h 00 0 0 0 0 1 1 x x PPPPPP PPPPPPBB BBBBBBBB

0Bh 0 0 0 0 1 0 1 1 x x PPPPPP PPPPPPBB BBBBBBBB

50h 01010000 xxPPPPPP PPPxxxxx xxxxxxx x

53h 01 0 1 0 0 1 1 x x PPPPPP PPPPPPx x x x x x x x x x

55h 01 0 1 0 1 0 1 x x PPPPPP PPPPPPx x x x x x x x x x

58h 01 0 1 1 0 0 0 x x PPPPPP PPPPPPx x x x x x x x x x

59h 01 0 1 1 0 0 1 x x PPPPPP PPPPPPx x x x x x x x x x

60h 01 1 0 0 0 0 0 x x PPPPPP PPPPPPx x x x x x x x x x

61h 01 1 0 0 0 0 1 x x PPPPPP PPPPPPx x x x x x x x x x

77h 01110111 xxxxxxxx xxxxxxxx xxxxxxx x

7Ch 01111100 xxPPPPxx xxxxxxxx xxxxxxx x

81h 10 0 0 0 0 0 1 x x PPPPPP PPPPPPx x x x x x x x x x

82h 10 0 0 0 0 1 0 x x PPPPPP PPPPPPBB BBBBBBBB

83h 10 0 0 0 0 1 1 x x PPPPPP PPPPPPx x x x x x x x x x

84h 10000100 xxxxxxxx xxxxxxBB BBBBBBBB

85h 10 0 0 0 1 0 1 x x PPPPPP PPPPPPBB BBBBBBBB

86h 10 0 0 0 1 1 0 x x PPPPPP PPPPPPx x x x x x x x x x

87h 10000111 xxxxxxxx xxxxxxBB BBBBBBBB

88h 10 0 0 1 0 0 0 x x PPPPPP PPPPPPx x x x x x x x x x

89h 10 0 0 1 0 0 1 x x PPPPPP PPPPPPx x x x x x x x x x

9Fh 10011111 N/A N/A N/A

B9h 10111001 N/A N/A N/A

ABh 10101011 N/A N/A N/A

D1h 11010001 xxxxxxxx xxxxxxBB BBBBBBBB

D2h 1 1 0 1 0 0 1 0 x x PPPPPP PPPPPPBB BBBBBBBB

D3h 11010001 xxxxxxxx xxxxxxBB BBBBBBBB

D4h 11010100 xxxxxxxx xxxxxxBB BBBBBBBB

D6h 11010110 xxxxxxxx xxxxxxBB BBBBBBBB

D7h 11010111 N/A N/A N/A

E8h 1 1 1 0 1 0 0 0 x x PPPPPP PPPPPPBB BBBBBBBB

Notes: P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care

BA2

BA1

Additional Don’t Care

BA0

BytesOpcode Opcode

N/A

AT45DB161D

3500O–DFLASH–11/2012

16. Power-on/Reset State

When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode

3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state.

16.1 Initial Power-up/Reset Timing Restrictions

At power up, the device must not be selected until the supply voltage reaches the VCC(min.) and further delay of t

. During power-up, the internal Power-on Reset circuitry keeps the device in reset mode until the VCCrises

VCSL

above the Power-on Reset threshold value (V respond to any commands. After power up is applied and the V the t

Similarly, the t

delay is required before the device can be selected in order to perform a read operation.

VCSL

delay is required after the VCCrises above the Power-on Reset threshold value (V

PUW

device can perform a write (Program or Erase) operation. After initial power-up, the device will default in Standby mode.

Table 16-1. Initial Power-up/Reset Timing Restrictions

Symbol Parameter Min Typ Max Units

VCSL

PUW

POR

VCC(min.) to Chip Select low 70 µs

Power-Up Device Delay before Write Allowed 20 ms

Power-ON Reset Voltage 1.5 2.5 V

). At this time, all operations are disabled and the device does not

POR

AT45DB161D

is at the minimum operating voltage VCC(min.),

) before the

POR

17. System Considerations

The RapidS serial interface is controlled by the clock SCK, serial input SI and chip select CS pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches.

As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption.

3500O–DFLASH–11/2012

18. Electrical Specifications

Table 18-1. Absolute Maximum Ratings*

Temperature under Bias ................. -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

Storage Temperature...................... -65°C to +150°C

The "Absolute Maximum Ratings" are stress ratings only and functional operation of the device at these or any

All Input Voltages (except V

but including NC pins)

with Respect to Ground ....................-0.6V to +6.25V

other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Extremes referenced

All Output Voltages

with Respect to Ground ..............-0.6V to V

+ 0.6V

in the "Absolute Maximum Ratings" are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time

Table 18-2. DC and AC Operating Range

AT45DB161D (2.5V Version) AT45DB161D

Operating Temperature (Case) Ind. -40Cto85C -40Cto85C

Power Supply 2.5V to 3.6V 2.7V to 3.6V

Table 18-3. DC Characteristics

Symbol Parameter Condition Min Typ Max Units

Deep Power-down Current

CS, RESET, WP = VIH,all inputs at CMOS levels

15 25 µA

(1)

CC1

CC2

Notes: 1. I

2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5V toleran

Standby Current

Active Current, Read Operation

Active Current, Program/Erase Operation

CS, RESET, WP = VIH,all inputs at CMOS levels

f = 20MHz; I V

= 3.6V

f = 33MHz; I V

= 3.6V

f = 50MHz; I V

= 3.6V

f = 66MHz; I V

= 3.6V

= 3.6V 12 17 mA

OUT

= 0mA;

25 50 µA

710mA

812mA

10 14 mA

11 15 mA

Input Load Current VIN= CMOS levels 1 µA

Output Leakage Current V

= CMOS levels 1 µA

I/O

Input Low Voltage VCCx 0.3 V

Input High Voltage VCCx 0.7 V

Output Low Voltage IOL= 1.6mA; VCC= 2.7V 0.4 V

Output High Voltage IOH= -100µA VCC-0.2V V

during a buffer read is 20mA maximum @ 20MHz

CC1

AT45DB161D

3500O–DFLASH–11/2012

Table 18-4. AC Characteristics – RapidS/Serial Interface

AT45DB161D

(2.5V Version) AT45DB161D

Symbol Parameter

SCK

CAR1

CAR2

SCKR

SCKF

CSS

CSH

CSB

DIS

WPE

WPD

EDPD

RDPD

XFR

COMP

(1)

SCK Frequency 50 66 MHz

SCK Frequency for Continuous Array Read 50 66 MHz

SCK Frequency for Continuous Array Read (Low Frequency)

SCK High Time 6.8 6.8 ns

SCK Low Time 6.8 6.8 ns

SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns

SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns

Minimum CS High Time 50 50 ns

CS Setup Time 5 5 ns

CS Hold Time 5 5 ns

CS High to RDY/BUSY Low 100 100 ns

Data In Setup Time 2 2 ns

Data In Hold Time 3 3 ns

Output Hold Time 0 0 ns

Output Disable Time 27 35 27 35 ns

Output Valid 8 6 ns

WP Low to Protection Enabled 1 1 µs

WP High to Protection Disabled 1 1 µs

CS High to Deep Power-down Mode 3 3 µs

CS High to Standby Mode 35 35 µs

Page to Buffer Transfer Time 200 200 µs

Page to Buffer Compare Time 200 200 µs

Page Erase and Programming Time (512-/528-bytes)

Min Typ Max Min Typ Max Units

33 33 MHz

17 40 17 40 ms

RST

REC

Page Programming Time (512-/528-bytes) 3 6 3 6 ms

Page Erase Time (512-/528-bytes) 15 35 15 35 ms

Block Erase Time (4096-/4224-bytes) 45 100 45 100 ms

Sector Erase Time (131,072/135,168-bytes) 0.7 1.3 0.7 1.3 s

Chip Erase Time 12 25 12 25 s

RESET Pulse Width 10 10 µs

RESET Recovery Time 1 1 µs

Note: 1. Values are based on device characterization, not 100% tested in production

3500O–DFLASH–11/2012

19. Input Test Waveforms and Measurement Levels

2.4V

DRIVING

LEVELS

0.45V

tR,tF< 2ns (10% to 90%)

20. Output Test Load

DEVICE

UNDER

TEST

30pF

21. AC Waveforms

Six different timing waveforms are shown on page 32. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as tWL). Timing waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 66MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.

1.5V

AC MEASUREMENT LEVEL

Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the tWLperiod. These timing waveforms are valid over the full frequency range (maximum frequency = 66MHz) of the RapidS serial case.

21.1 Waveform 1 – SPI Mode 0 Compatible (for frequencies up to 66MHz)

SCK

HIGH IMPEDANCE

VALID IN

CSS

VALID OUT

CSH

DIS

HIGH IMPEDANCE

AT45DB161D

3500O–DFLASH–11/2012

21.2 Waveform 2 – SPI Mode 3 Compatible (for frequencies up to 66MHz)

SCK

CSS

HIGH Z

CSH

VALID OUT

VALID IN

DIS

HIGH IMPEDANCE

AT45DB161D

21.3 Waveform 3 – RapidS Mode 0 (F

SCK

CSS

HIGH IMPEDANCE

VALID IN

21.4 Waveform 4 – RapidS Mode 3 (F

SCK

CSS

HIGH Z

VAL I D IN

VALID OUT

= 66MHz)

MAX

VALID OUT

= 66MHz)

MAX

CSH

DIS

HIGH IMPEDANCE

DIS

HIGH IMPEDANCE

21.5 Utilizing the RapidS Function

To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK.

For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the falling edge of SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of SCK.

3500O–DFLASH–11/2012

Figure 21-1. RapidS Mode

Slave

SCK

MOSI

MISO

MOSI = Master Out, Slave In MISO = Master In, Slave Out The Master is the host controller and the Slave is the DataFlash

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK. The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.

A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK D. Last bit of BYTE-MOSI is clocked out from the Master E. Last bit of BYTE-MOSI is clocked into the slave F. Slave clocks out first bit of BYTE-SO G. Master clocks in first bit of BYTE-SO H. Slave clocks out second bit of BYTE-SO I. Master clocks in last bit of BYTE-SO

21.6 Reset Timing

2 3 4 5 6 7

C D

MSB LSB

BYTE-MOSI

8 1

2 3 4 5 6 7

MSB LSB

BYTE-SO

REC

SCK

RST

RESET

SO (OUTPUT)

HIGH IMPEDANCE HIGH IMPEDANCE

SI (INPUT)

Note: The CS signal should be in the high state before the RESET signal is deasserted

CSS

AT45DB161D

3500O–DFLASH–11/2012

AT45DB161D

21.7 Command Sequence for Read/Write Operations for Page Size 512-Bytes (Except Status Register Read, Manufacturer and Device ID Read)

SI (INPUT) CMD 8-bits

MSB

X X X X X X X X X X X X X X X X LSB

Don’t Care

Bits

Page Address

(A20 - A9)

8-bits

X X X X X X X X

Byte/Buffer Address

(A8 - A0/BFA8 - BFA0)

21.8 Command Sequence for Read/Write Operations for Page Size 528-Bytes (Except Status Register Read, Manufacturer and Device ID Read)

SI (INPUT)

MSB

CMD 8-bits

X X X X X X X X X X X X LSB

2 Don’t Care

Bits

Page Address

(PA11 - PA0)

8-bits

X X X X

8-bits

X X X X X X X X

Byte/Buffer Address

(BA9 - BA0/BFA9 - BFA0)

22. Write Operations

The following block diagram and waveforms illustrate the various write sequences available.

PAGE (512-/528-BYTES)

BUFFER 1 TO

MAIN MEMORY

PAGE PROGRAM

BUFFER 1

WRITE

FLASH MEMORY ARRAY

BUFFER 2 (512-/528-BYTES)BUFFER 1 (512-/528-BYTES)

I/O INTERFACE

BUFFER 2 TO MAIN MEMORY PAGE PROGRAM

BUFFER 2 WRITE

3500O–DFLASH–11/2012

22.1 Buffer Write

Completes writing into selected buffer

BINARY PAGE SIZE

15 DON'T CARE + BFA8-BFA0

SI (INPUT)

CMD

X···X, BFA9-8

BFA7-0

n+1

Last Byte

22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)

Starts self-timed erase/program operation

BINARY PAGE SIZE

A20-A9 + 9 DON'T CARE BITS

SI (INPUT)

Each transition

represents eight bits

23. Read Operations

The following block diagram and waveforms illustrate the various read sequences available.

PAGE (512-/528-BYTES)

MAIN MEMORY

PAGE TO

BUFFER 1

READ

CMD

PA11-6 PA5-0, XX

FLASH MEMORY ARRAY

BUFFER 2 (512-/528-BYTES)BUFFER 1 (512-/528-BYTES)

MAIN MEMORY PAGE READ

I/O INTERFACE

MAIN MEMORY PAGE TO BUFFER 2

BUFFER 2 READ

XXXX XX

n = 1st byte read n+1 = 2nd byte read

AT45DB161D

3500O–DFLASH–11/2012

23.1 Main Memory Page Read

AT45DB161D

SI (INPUT)

SO (OUTPUT)

CMD

ADDRESS FOR BINARY PAGE SIZE

A20-A16

PA11-6

A15-A8

, PA5-0, BA9-8

A7-A0

BA7-0

4 Dummy Bytes

n n+1

23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)

Starts reading page data into buffer

BINARY PAGE SIZE

A20-A9 + 9 DON'T CARE BITS

SI (INPUT)

SO (OUTPUT)

CMD

PA11-6

PA5-0, XX

XXXX XXXX

23.3 Buffer Read

SI (INPUT)

SO (OUTPUT)

CMD

Each transition represents eights bits

BINARY PAGE SIZE

15 DON'T CARE + BFA8-BFA0

X..X, BFA9-8

BFA7- 0

No Dummy Byte (opcodes D1H and D3H) 1 Dummy Byte (opcodes D4H and D6H)

n n+1

3500O–DFLASH–11/2012

24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3

24.1 Continuous Array Read (Legacy Opcode E8H)

2310

675410119812 63666765646233 3431 3229 30 68 71 727069

SCK

OPCODE

11101000

MSB MSB

HIGH-IMPEDANCE

ADDRESS BITS 32 DON'T CARE BITS

AAAA AAAAA

24.2 Continuous Array Read (Opcode 0BH)

2310

OPCODE

00001011

MSB MSB

HIGH-IMPEDANCE

675410119812 39424341403833 3431 3229 30 44 47 484645

ADDRESS BITS A20 - A0 DON'T CARE

AAAA AAAAA

XXXX XX

MSB

36 3735

XXXX XX

MSB

DATA BYTE 1

DDDDDDDDDD

MSB MSB

DATA BYTE 1

DDDDDDDDDD

MSB MSB

BIT 4095/4223

OF PAGE n

BIT 0 OF

PAGE n+1

24.3 Continuous Array Read (Low Frequency: Opcode 03H)

2310

SCK

OPCODE

00000011

MSB MSB

HIGH-IMPEDANCE

AT45DB161D

675410119812 373833 36353431 3229 30 39 40

ADDRESS BITS A20-A0

AAAA AAAAA

MSB MSB

DATA BYTE 1

DDDDDDDDDD

3500O–DFLASH–11/2012

24.4 Main Memory Page Read (Opcode: D2H)

AT45DB161D

2310

675410119812 63666765646233 3431 3229 30 68 71 727069

SCK

OPCODE

11010010

MSB MSB

HIGH-IMPEDANCE

AAAA AAAAA

24.5 Buffer Read (Opcode D4H or D6H)

SCK

2 3 1 0

OPCODE

1 1 0 1 0 1 0 0

MSB MSB

HIGH-IMPEDANCE

6 7 5 4 10 11 9 8 12 39 42 43 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45

ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = 14 DON'T CARE + BFA9-BFA0

X X X X A A A X X

ADDRESS BITS 32 DON'T CARE BITS

XXXX XX

MSB

DATA BYTE 1

DDDDDDDDDD

MSB MSB

DON'T CARE

X X X X X X X X

MSB

DATA BYTE 1

D D D D D D D D D D

MSB MSB

24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)

SCK

2 3 1 0

OPCODE

1 1 0 1 0 0 0 1

MSB MSB

HIGH-IMPEDANCE

6 7 5 4 10 11 9 8 12 37 38 33 36 35 34 31 32 29 30 39 40

ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = 14 DON'T CARE + BFA9-BFA0

X X X X A A A X X

DATA BYTE 1

D D D D D D D D D D

MSB MSB

3500O–DFLASH–11/2012

24.7 Read Sector Protection Register (Opcode 32H)

2310

675410119812 373833 36353431 3229 30 39 40

SCK

OPCODE

00110010

MSB MSB

HIGH-IMPEDANCE

XXXX XXXXX

DON'T CARE

24.8 Read Sector Lockdown Register (Opcode 35H)

SCK

2310

OPCODE

00110101

MSB MSB

HIGH-IMPEDANCE

675410119812 373833 36353431 3229 30 39 40

DON'T CARE

XXXX XXXXX

DATA BYTE 1

DDDDDDDDD

MSB MSB

DATA BYTE 1

DDDDDDDDD

MSB MSB

24.9 Read Security Register (Opcode 77H)

SCK

2310

OPCODE

01110111

MSB MSB

HIGH-IMPEDANCE

675410119812 373833 36353431 3229 30 39 40

XXXX XXXXX

DON'T CARE

DATA BYTE 1

DDDDDDDDD

MSB MSB

AT45DB161D

3500O–DFLASH–11/2012

24.10 Status Register Read (Opcode D7H)

AT45DB161D

2310

675410119812 212217 20191815 1613 14 23 24

SCK

OPCODE

11010111

MSB

HIGH-IMPEDANCE

STATUS REGISTER DATA STATUS REGISTER DATA

DDDDDD DDDD

MSB MSB

24.11 Manufacturer and Device Read (Opcode 9FH)

6 0

SCK

8 7 38

OPCODE

9FH

HIGH-IMPEDANCE

14 16 15 22 24 23 30 32 31

1FH DEVICE ID BYTE 1 DEVICE ID BYTE 2 00H

DDDDDDDD

MSB

Note: Each transition shown for SI and SO represents one byte (8-bits)

3500O–DFLASH–11/2012

25. Auto Page Rewrite Flowchart

Figure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially

MAIN MEMORY PAGE PROGRAM

THROUGH BUFFER

(82H, 85H)

START

provide address

and data

BUFFER WRITE

(84H, 87H)

BUFFER TO MAIN

MEMORY PAGE PROGRAM

(83H, 86H)

END

Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array

page-by-page

2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation

3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array

AT45DB161D

3500O–DFLASH–11/2012

Figure 25-2. Algorithm for Randomly Modifying Data

START

provide address of

page to modify

AT45DB161D

MAIN MEMORY PAGE

TO BUFFER TRANSFER

MAIN MEMORY PAGE PROGRAM

THROUGH BUFFER

(82H, 85H)

AUTO PAGE REWRITE

(53H, 55H)

(58H, 59H)

If planning to modify multiple bytes currently stored within a page of the Flash array

BUFFER WRITE

(84H, 87H)

BUFFER TO MAIN

MEMORY PAGE PROGRAM

(83H, 86H)

(2)

Notes: 1. To preserve data integrity, each page of an DataFlash sector must be updated/rewritten at least once within every

3500O–DFLASH–11/2012

INCREMENT PAGE

ADDRESS POINTER

END

10,000 cumulative page erase and program operations

2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command must use the address specified by the Page Address Pointer

3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Adesto’s Serial DataFlash”) for more details

(2)

26. Ordering Information

26.1 Ordering Code Detail

AT4 5D 16 SSU1D–B

Designator

Product Family

Device Density

16 = 16-megabit

Interface

1 = Serial

Device Revision

26.2 Green Package Options (Pb/Halide-free/RoHS Compliant)

Ordering Code

AT45DB161D-MU AT45DB161D-MU-SL954

AT45DB161D-MU-SL955

AT45DB161D-SU AT45DB161D-SU-SL954 AT45DB161D-SU-SL955

AT45DB161D-TU 28T

AT45DB161D-MU-2.5 8M1-A

AT45DB161D-TU-2.5 28T

AT45DB161D-CU 24C1 Matte Sn 2.7V to 3.6V 66

Notes: 1. The shipping carrier option is not marked on the devices

2. Standard parts are shipped with the page size set to 528-bytes. The user is able to configure these parts to a 512byte page size if desired

3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 512-bytes. Parts will have a 954 or SL954 marked on them

4. Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 512-bytes. Parts will have a 954 or SL954 marked on them

(1)(2)

Package Lead Finish Operating Voltage f

(3)

(4)

(3)

(4)

8M1-A

Matte Sn 2.7V to 3.6V 66

8S2

Matte Sn 2.5V to 3.6V 50AT45DB161D-SU-2.5 8S2

Device Grade

U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C)

Package Option

M = 8-lead, 6 x 5 x 1mm MLF (VDFN) S = 8-lead, 0.209" wide SOIC T = 28-lead, TSOP

C = 24 Ball BGA

(MHz) Operation Range

SCK

Industrial

(-40Cto85C)

2.7V to 3.6V

Package Type

™

8M1-A 8-pad,6x5x1.00mm Body, Very Thin Dual Flat Package No Lead MLF

8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

28T 28-lead, 8mm x 13.4mm, Plastic Thin Small Outline Package, Type I (TSOP)

24C1 24-Ball, 6mm x 8mm x 1,4mm Ball Grid Array with a 1mm pitch5x5BallMatrix

(VDFN)

AT45DB161D

3500O–DFLASH–11/2012

27. Packaging Information

27.1 8M1-A – MLF (VDFN)

Pin 1 ID

AT45DB161D

SIDE VIEW

TOP VIEW

Pin #1 Notch

(0.20 R)

BOTTOM VIEW

0.45

0.08

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – 0.85 1.00

A1 – – 0.05

A2 0.65 TYP

A3 0.20 TYP

b 0.35 0.40 0.48

D 5.90 6.00 6.10

D1 5.70 5.75 5.80

D2 3.20 3.40 3.60

E 4.90 5.00 5.10

E1 4.70 4.75 4.80

E2 3.80 4.00 4.20

e 1.27

L 0.50 0.60 0.75

– – 12

K 0.25 – –

MIN

NOM

MAX

NOTE

8/28/08

DRAWING NO. GPC

8M1-AYBR

REV.

Package Drawing Contact:

contact@adestotech.com

TITLE 8M1-A, 8-pad, 6 x 5 x 1.00mm Body, Thermally

Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN)

3500O–DFLASH–11/2012

27.2 8S2 – EIAJ SOIC

TOP VIEW

END VIEW

SIDE VIEW

TOP VIEW

SIDE VIEW

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. Determines the true geometric position.

4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

TITLE

Package Drawing Contact:

contact@adestotech.com

8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ)

END VIEW

SYMBOL

A 1.70 2.16

A1 0.05 0.25

b 0.35 0.48 4

C 0.15 0.35 4

D 5.13 5.35

E1 5.18 5.40 2

E 7.70 8.26

L 0.51 0.85

q 0° 8°

e 1.27 BSC 3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

DRAWING NO. GPC

8S2 STN F

NOTE

4/15/08

REV.

AT45DB161D

3500O–DFLASH–11/2012

27.3 28T – TSOP, Type 1

AT45DB161D

PIN 1

Pin 1 Identifier Area

SEATING PLANE

Notes: 1. This package conforms to JEDEC reference MO-183.

2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15mm per side and on D1 is 0.25mm per side.

3. Lead coplanarity is 0.10mm maximum.

0º ~ 5º

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.90 1.00 1.05

D 13.20 13.40 13.60

D1 11.70 11.80 11.90 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.55 BASIC

MIN

NOM

MAX

NOTE

Package Drawing Contact:

contact@adestotech.com

3500O–DFLASH–11/2012

TITLE

28T, 28-lead (8 x 13.4mm) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

28T

12/06/02

REV.

27.4 24C1 - Ball Grid Array

Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters.

8.10(0.319)

7.90(0.311)

6.10(0.240)

5.90(0.232)

A1 ID

SIDE VIEW

1.00 (0.039) REF

1.00 (0.0394) BSC

NON-ACCUMULATIVE

1.00 (0.0394) BSC

NON-ACCUMULATIVE

54 3 2 1

TOP VIEW

4.0 (0.157)

BOTTOM VIEW

0.30 (0.012)MIN

1.40 (0.055) MAX

2.00 (0.079) REF

4.0 (0.157)

0.46 (0.018) DIA BALL TYP

Package Drawing Contact:

contact@adestotech.com

AT45DB161D

TITLE

24C1, 24-ball (5 x 5 Array), 6 x 8 x 1.4 mm Body, 1.0mm

Ball Pitch Chip-scale Ball Grid Array Package (CBGA)

DRAWING NO.

24C1

3500O–DFLASH–11/2012

04/11/01

REV.

28. Revision History

Doc. Rev. Date Comments

3500O 11/2012 Update to Adesto Technologies.

3500N 05/2010

3500M 04/2009

3500L 03/2009

AT45DB161D

Changed t Changed t Changed from 10,000 to 20,000 cumulative page erase/program operations and added the

please contact Adesto statement in section 11.3

Updated Absolute Maximum Ratings Added 24C1 24 Ball BGA package Option Deleted DataFlash Card Package Option Removed Chip Erase Errata

Changed Deep Power-Down Current values

- Increased typical value from 5µA to 15µA

- Increased maximum value from 15µA to 25µA

(Typ) 1.6 to 0.7 and (Max) 5 to 1.3

(Typ) TBD to 12 and (Max) TBD to 25

3500K 02/2009 Changed t

3500J 04/2008

Added part number ordering code details for suffixes SL954/955 Added ordering code details

(Typ and Max) to 27ns and 35ns, respectively

DIS

Added additional text to “power of 2” binary page size option Removed SER/

3500I 08/2007

Changed t Changed t

Changed t

3500H 08/2006 Added t

SCKR

BYTE statement from SI and SO pin descriptions in Table 2-1

from 50µs to 70µs

VSCL

and t

XFR

from 30µs to 35µs

RDPD

and t

values from 400µs to 200µs

COMP

parameters to Table 18-4

SCKF

3500G 08/2006 Added errata regarding Chip Erase

3500F 07/2006 Corrected typographical errors

3500E 05/2006

Added Legacy Status Register Read opcode 57H. This opcode is supported on devices with date code 0636 and later

3500D 02/2006 Changed part 2 of the device ID to 00H

Added text, in “Programming the Configuration Register”, to indicate that power cycling is

3500C 01/2006

required to switch to “power of 2” page size after the opcode enable has been executed Added “Legacy Commands” table

Added 2.5V - 3.6V operating range

3500B 11/2005

Changed t Changed t Changed t Changed t

from 30µs to 50µs min

VCSL

from 10ms to 20ms max

PUW

from 8ns to 6ns max (2.7V device)

DIS

from 8ns to 6ns max (2.7V device)

3500A 09/2005 Initial Document Release

3500O–DFLASH–11/2012

29. Errata

29.1 No Errata Conditions

AT45DB161D

3500O–DFLASH–11/2012

Corporate Office

California | USA Adesto Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: (+1) 408.400.0578 Email: contact@adestotech.com

Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective owners.

Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.

Rainbow Electronics AT45DB161D User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

2. Pin Configurations and Pinouts

3. Block Diagram

4. Memory Array

5. Device Operation

6. Read Commands

6.1 Continuous Array Read (Legacy Command: E8H): Up to 66MHz

6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66MHz

6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz

6.4 Main Memory Page Read

6.5 Buffer Read

7. Program and Erase Commands

7.1 Buffer Write

7.2 Buffer to Main Memory Page Program with Built-in Erase

7.3 Buffer to Main Memory Page Program without Built-in Erase

7.4 Page Erase

7.5 Block Erase

7.6 Sector Erase

7.8 Main Memory Page Program Through Buffer

8. Sector Protection

8.1 Software Sector Protection

8.1.1 Enable Sector Protection Command

8.1.2 Disable Sector Protection Command

8.1.3 Various Aspects About Software Controlled Protection

9. Hardware Controlled Protection

9.1 Sector Protection Register

9.1.1 Erase Sector Protection Register Command

9.1.2 Program Sector Protection Register Command

9.1.3 Read Sector Protection Register Command

9.1.4 Various Aspects About the Sector Protection Register

10. Security Features

10.1 Sector Lockdown

10.1.1 Sector Lockdown Register

10.1.2 Reading the Sector Lockdown Register

10.2 Security Register

10.2.1 Programming the Security Register

10.2.2 Reading the Security Register

11. Additional Commands

11.1 Main Memory Page to Buffer Transfer

11.2 Main Memory Page to Buffer Compare

11.3 Auto Page Rewrite

11.4 Status Register Read

12. Deep Power-down

12.1 Resume from Deep Power-down

13. “Power of 2” Binary Page Size Option

13.1 Programming the Configuration Register

14. Manufacturer and Device ID Read

14.1 Manufacturer and Device ID Information

14.2 Operation Mode Summary

15. Command Tables

16. Power-on/Reset State

16.1 Initial Power-up/Reset Timing Restrictions

17. System Considerations

18. Electrical Specifications

19. Input Test Waveforms and Measurement Levels

20. Output Test Load

21. AC Waveforms

21.1 Waveform 1 – SPI Mode 0 Compatible (for frequencies up to 66MHz)

21.2 Waveform 2 – SPI Mode 3 Compatible (for frequencies up to 66MHz)

21.5 Utilizing the RapidS Function

21.6 Reset Timing

21.7 Command Sequence for Read/Write Operations for Page Size 512-Bytes (Except Status Register Read, Manufacturer and Device ID Read)

21.8 Command Sequence for Read/Write Operations for Page Size 528-Bytes (Except Status Register Read, Manufacturer and Device ID Read)

22. Write Operations

22.1 Buffer Write

22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)

23. Read Operations

23.1 Main Memory Page Read

23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)

23.3 Buffer Read

24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3

24.1 Continuous Array Read (Legacy Opcode E8H)

24.2 Continuous Array Read (Opcode 0BH)

24.3 Continuous Array Read (Low Frequency: Opcode 03H)

24.4 Main Memory Page Read (Opcode: D2H)