Rainbow Electronics AT45DB021B User Manual

Features

• Single 2.7V - 3.6V Supply

• Serial Peripheral Interface (SPI) Compatible

• Page Program Operation

– Single Cycle Reprogram (Erase and Program)
– 1024 Pages (264 Bytes/Page) Main Memory

• Supports Page and Block Erase Operations

• Two 264-byte SRAM Data Buffers – Allows Receiving of Data

while Reprogramming of Nonvolatile Memory

• Continuous Read Capability through Entire Array

– Ideal for Code Shadowing Applications

• Low Power Dissipation

– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical

• 20 MHz Max Clock Frequency

• Hardware Data Protection Feature

• 100% Compatible to AT45DB021 and AT45DB021A

• 5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins

• Commercial and Industrial Temperature Ranges

Description

The AT45DB021B is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 2,162,688 bits of memory are organized as 1024 pages of 264 bytes each. In addi­tion to the main memory, the AT45DB021B also contains two SRAM data buffers

of 264 bytes each. The buffers allow receiving of data while a page in the main mem-

ory is being reprogrammed, as well as reading or writing a continuous data stream.

2-megabit

2.7-volt Only
DataFlash

®

AT45DB021B

Pin Configurations

Pin Name Function

CS

SCK Serial Clock

SI Serial Input

SO Serial Output

WP

RESET

RDY/BUSY

CBGA Top View

through Package

A

B

C

Chip Select

Hardware Page Write
Protect Pin

Chip Reset

Ready/Busy

123

GND

RDY/BSY

SI

VCC

WP

RESET

SCK

CS

SO

GND

SCK

NC
NC
CS

SI
SO
NC
NC
NC
NC
NC
NC
NC

RDY/BUSY

RESET

WP

NC

NC
VCC
GND

NC

NC

NC

CS
SCK

SI

SO

28-SOIC

1

28

2

27

3

26

4

25

5

24

6

23

7

22

8

21

9

20

10

19

11

18

12

17

13

16

14

15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC

TSOP Top View

Ty p e 1

SI

SCK

RESET

CS

8-SOIC

1
2
3
4

28

NC

27

NC

26

NC

25

NC

24

NC

23

NC

22

NC

21

NC

20

NC

19

NC

18

NC

17

NC

16

NC

15

NC

SO

8

GND

7

VCC

6

WP

5

Rev. 1937F–DFLSH–10/02

1

Block Diagram

EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three
step Read-Modify-Write operation. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode
0 and mode 3. The simple serial interface facilitates hardware layout, increases system
reliability, minimizes switching noise, and reduces package size and active pin count.
The device is optimized for use in many commercial and industrial applications where
high density, low pin count, low voltage, and low power are essential. The device oper­ates at clock frequencies up to 20 MHz with a typical active read current consumption of
4mA.

To allow for simple in-system reprogrammability, the AT45DB021B does not require
high input voltages for programming. The device operates from a single power supply,

2.7V to 3.6V, for both the program and read operations. The AT45DB021B is enabled
through the chip select pin (CS

) and accessed via a three-wire interface consisting of

the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming cycles are self-timed, and no separate erase cycle is required before
programming.

When the device is shipped from Atmel, the most significant page of the memory array
may not be erased. In other words, the contents of the last page may not be filled with
FFH.

Memory Array

WP

PAGE (264 BYTES)

SCK

CS

RESET

VCC

GND

RDY/BUSY

FLASH MEMORY ARRAY

BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)

I/O INTERFACE

SOSI

To provide optimal flexibility, the memory array of the AT45DB021B is divided into three
levels of granularity comprised of sectors, blocks and pages. The Memory Architecture
Diagram illustrates the breakdown of each level and details the number of pages per
sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.

2

AT45DB021B

1937F–DFLSH–10/02

Memory Architecture Diagram

SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE

SECTOR 0a = 8 Pages

2112 bytes (2K + 64)

SECTOR 0

BLOCK 0

BLOCK 1

BLOCK 2

8 Pages

AT45DB021B

PAGE 0

PAGE 1

SECTOR 0b = 248 Pages

65,472 bytes (62K + 1984)

SECTOR 0c = 256 Pages

67,584 bytes (64K + 2K)

SECTOR 1 = 512 Pages

135,168 bytes (128K + 4K)

Device Operation

SECTOR 1

SECTOR 2

BLOCK 30

BLOCK 31

BLOCK 32

BLOCK 33

BLOCK 62

BLOCK 63

BLOCK 64

BLOCK 65

BLOCK 126

BLOCK 127

Block = 2112 bytes

(2K + 64)

BLOCK 0

BLOCK 1

PAGE 6

PAGE 7

PAGE 8

PAGE 9

PAGE 14

PAGE 15

PAGE 16

PAGE 17

PAGE 18

PAGE 1021

PAGE 1022

PAGE 1023

Page = 264 bytes

(256 + 8)

The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4 (pages 10
and 11). A valid instruction starts with the falling edge of CS
8-bit opcode and the desired buffer or main memory address location. While the CS

followed by the appropriate

pin
is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or
main memory address location through the SI (serial input) pin. All instructions,
addresses, and data are transferred with the most significant bit (MSB) first.

Buffer addressing is referenced in the datasheet using the terminology BFA8 -BFA0 to
denote the nine address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA9 - PA0 and BA8-BA0 where
PA9- PA0 denotes the 10 address bits required to designate a page address and BA8 ­BA0 denotes the nine address bits required to designate a byte address within the page.

Read Commands By specifying the appropriate opcode, data can be read from the main memory or from

either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 10 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.

CONTINUOUS ARRAY READ: By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock

1937F–DFLSH–10/02

3

cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked
intothedevicefollowedby24addressbitsand32don’t care bits. The first five bits of
the 24-bit address sequence are reserved for upward and downward compatibility to
larger and smaller density devices (see Notes under “Command Sequence for
Read/Write Operations” diagram). The next 10 address bits (PA9-PA0) specify which
page of the main memory array to read, and the last nine bits (BA8 -BA0) of the 24-bit
address sequence specify the starting byte address within the page. The 32 don’tcare
bits that follow the 24 address bits are needed to initialize the read operation. Following
the32don’t care bits, additional clock pulses on the SCK pin will result in serial data
being output on the SO (serial output) pin.

The CS
care bits, and the reading of data. When the end of a page in main memory is reached
during a Continuous Array Read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the
main memory array has been read, the device will continue reading back at the begin­ning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the
array.

A low-to-high transition on the CS
SO pin. The maximum SCK frequency allowable for the Continuous Array Read is
defined by the f
ers and leaves the contents of the buffers unchanged.

MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data
directly from any one of the 1024 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of 52H or D2H must be clocked into the device followed by 24 address bits and
32 don’t care bits. The first five bits of the 24-bit address sequence are reserved bits, the
next 10 address bits (PA9-PA0) specify the page address, and the next nine address
bits (BA8-BA0) specify the starting byte address within the page. The 32 don’tcarebits
which follow the 24 address bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial data being output on the SO
(serial output) pin. The CS
address bits, the don’t care bits and the reading of data. When the end of a page in main
memory is reached during a Main Memory Page Read, the device will continue reading
at the beginning of the same page. A low-to-high transition on the CS
the read operation and tri-state the SO pin.

pin must remain low during the loading of the opcode, the address bits, the don’t

pin will terminate the read operation and tri-state the

specification. The Continuous Array Read bypasses both data buff-

CAR

pin must remain low during the loading of the opcode, the

pin will terminate

BUFFER READ: Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read
data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To
perform a Buffer Read, the eight bits of the opcode must be followed by 15 don’tcare
bits, nine address bits, and eight don’t care bits. Since the buffer size is 264-bytes, nine
address bits (BFA8-BFA0) are required to specify the first byte of data to be read from
the buffer. The CS
bits, the don’t care bits and the reading of data. When the end of a buffer is reached, the
device will continue reading back at the beginning of the buffer. A low-to-high transition
on the CS

4

AT45DB021B

pin will terminate the read operation and tri-state the SO pin.

pin must remain low during the loading of the opcode, the address

1937F–DFLSH–10/02

AT45DB021B

STATUS REGISTER READ: The status register can be used to determine the device’s

ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode of 57H or D7H must be
loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the
status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the
next eight clock cycles. The five most-significant bits of the status register will contain
device information, while the remaining three least-significant bits are reserved for future
use and will have undefined values. After bit 0 of the status register has been shifted
out, the sequence will repeat itself (as long as CS
gled) starting again with bit 7. The data in the status register is constantly updated, so
each repeating sequence will output new data.

Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

remains low and SCK is being tog-

Program and Erase Commands

RDY/BUSY

Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. The user can continuously poll bit 7 of the status register by
stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue
to be output on the SO pin, and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations that can cause the device to be in a busy
state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory Page
Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page Program,
and Auto Page Rewrite.

The result of the most recent Main Memory Page to Buffer Compare operation is indi­cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.

The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the
AT45DB021B, the four bits are 0, 1, 0 and 1. The decimal value of these four binary bits
does not equate to the device density; the four bits represent a combinational code
relating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif­ferent density configurations.

BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2.
To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, must
be followed by 15 don't care bits and nine address bits (BFA8-BFA0). The nine address
bits specify the first byte in the buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the device will wrap around back to
the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to­high transition is detected on the CS

COMP0101XX

pin.

1937F–DFLSH–10/02

BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written
into either buffer 1 or buffer 2 can be programmed into the main memory. To start the
operation, an 8-bit opcode (83H for buffer 1 or 86H for buffer 2) must be followed by the
five reserved bits, 10 address bits (PA9-PA0) that specify the page in the main memory
to be written, and nine additional don’t care bits. When a low-to-high transition occurs on
the CS
program the data stored in the buffer into the specified page in the main memory. Both
the erase and the programming of the page are internally self-timed and should take

pin, the part will first erase the selected page in main memory to all 1s and then

5

place in a maximum time of tEP. During this time, the status register will indicate that the
part is busy.

BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: Aprevi­ously erased page within main memory can be programmed with the contents of either
buffer 1 or buffer 2. To start the operation, an 8-bit opcode (88H for buffer 1 or 89H for
buffer 2) must be followed by the five reserved bits, 10 address bits (PA9-PA0) that
specify the page in the main memory to be written, and nine additional don’tcarebits.
When a low-to-high transition occurs on the CS

pin, the part will program the data stored
in the buffer into the specified page in the main memory. It is necessary that the page in
main memory that is being programmed has been previously erased. The programming
of the page is internally self-timed and should take place in a maximum time of t

.Dur-

P

ing this time, the status register will indicate that the part is busy.

Successive page programming operations without doing a page erase are not recom­mended. In other words, changing bytes within a page from a “1” to a “0” during multiple
page programming operations without erasing that page is not recommended.

PAGE ERASE: The optional Page Erase command can be used to individually erase
any page in the main memory array allowing the Buffer to Main Memory Page Program
without Built-in Erase command to be utilized at a later time. To perform a Page Erase,
an opcode of 81H must be loaded into the device, followed by five reserved bits, ten
address bits (PA9- PA0), and nine don’t care bits. The ten address bits are used to spec­ify which page of the memory array is to be erased. When a low-to-high transition occurs
on the CS
nally self-timed and should take place in a maximum time of t

pin, the part will erase the selected page to 1s. The erase operation is inter-

. During this time, the

PE

status register will indicate that the part is busy.

BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer
to Main Memory Page Program without Built-in Erase command to be utilized to reduce
programming times when writing large amounts of data to the device. To perform a
Block Erase, an opcode of 50H must be loaded into the device, followed by five
reserved bits, seven address bits (PA9 -PA3), and 12 don’t care bits. The seven address
bits are used to specify which block of eight pages is to be erased. When a low-to-high
transition occurs on the CS

pin, the part will erase the selected block of eight pages to
1s. The erase operation is internally self-timed and should take place in a maximum
time of t

. During this time, the status register will indicate that the part is busy.

BE

Block Erase Addressing

PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block

0000000XXX 0

0000001XXX 1

0000010XXX 2

0000011XXX 3

•

•

•

1111100XXX124

1111101XXX125

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

1111110XXX126

1111111XXX127

6

AT45DB021B

1937F–DFLSH–10/02

AT45DB021B

MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-

tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase
operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro­grammed into a specified page in the main memory. To initiate the operation, an 8-bit
opcode (82H for buffer 1 or 85H for buffer 2) must be followed by the five reserved bits
and 20 address bits. The 10 most-significant address bits (PA9 - PA0) select the page in
the main memory where data is to be written, and the next nine address bits (BFA8­BFA0) select the first byte in the buffer to be written. After all address bits are shifted in,
the part will take data from the SI pin and store it in one of the data buffers. If the end of
the buffer is reached, the device will wrap around back to the beginning of the buffer.
When there is a low-to-high transition on the CS
page in main memory to all 1s and then program the data stored in the buffer into the
specified page in the main memory. Both the erase and the programming of the page
are internally self-timed and should take place in a maximum of time t
time, the status register will indicate that the part is busy.

Additional Commands MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred

from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by the five reserved bits,
10 address bits (PA9-PA0) which specify the page in main memory that is to be trans­ferred, and nine don’tcarebits.TheCS
load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of
the page of data from the main memory to the buffer will begin when the CS
tions from a low to a high state. During the transfer of a page of data (t
register can be read to determine whether the transfer has been completed or not.

pin must be low while toggling the SCK pin to

pin, the part will first erase the selected

.Duringthis

EP

pin transi-

), the status

XFR

MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode
(60H for buffer 1 and 61H for buffer 2) must be followed by 24 address bits consisting of
the five reserved bits, 10 address bits (PA9-PA0) which specify the page in the main
memory that is to be compared to the buffer, and nine don’tcarebits.TheCS

pin must
be low while toggling the SCK pin to load the opcode, the address bits and the don’t
care bits from the SI pin. On the low-to-high transition of the CS

pin, the 264 bytes in the
selected main memory page will be compared with the 264 bytes in buffer 1 or buffer 2.
During this time (t

), the status register will indicate that the part is busy. On comple-

XFR

tion of the compare operation, bit 6 of the status register is updated with the result of the
compare.

AUTO PAGE REWRITE: This mode is needed only if multiple bytes within a page or
multiple pages of data are modified in a random fashion. This mode is a combination of
two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page
Program with Built-in Erase. A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed
back into its original page of main memory. To start the rewrite operation, an 8-bit
opcode (58H for buffer 1 or 59H for buffer 2) must be followed by the five reserved bits,
10 address bits (PA9-PA0) that specify the page in main memory to be rewritten, and
nine additional don’t care bits. When a low-to-high transition occurs on the CS

pin, the
part will first transfer data from the page in main memory to a buffer and then program
the data from the buffer back into same page of main memory. The operation is inter­nally self-timed and should take place in a maximum time of t

. During this time, the

EP

status register will indicate that the part is busy.

1937F–DFLSH–10/02

7

If a sector is programmed or reprogrammed sequentially page-by-page, then the pro­gramming algorithm shown in Figure 1 on page 26 is recommended. Otherwise, if
multiple bytes in a page or several pages are programmed randomly in a sector, then
the programming algorithm shown in Figure 2 on page 27 is recommended. Each page
within a sector must be updated/rewritten at least once within every 10,000 cumulative
page erase/program operations in that sector.

Operation Mode Summary

The modes described can be separated into two groups – modes which make use of the
Flash memory array (Group A) and modes which do not make use of the Flash memory
array (Group B).

Group A modes consist of:

1. Main Memory Page Read

2. Main Memory Page to Buffer 1 (or 2) Transfer

3. Main Memory Page to Buffer 1 (or 2) Compare

4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase

5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase

6. Page Erase

7. Block Erase

8. Main Memory Page Program through Buffer

9. Auto Page Rewrite

Group B modes consist of:

1. Buffer1(or2)Read

2. Buffer1(or2)Write

3. Status Register Read

If a Group A mode is in progress (not fully completed), then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
progress, modes in Group B can be started.

This gives the Serial DataFlash the ability to virtually accommodate a continuous data
stream. While data is being programmed into main memory from buffer 1, data can be
loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’sSerial
DataFlash”) for more details.

Pin Descriptions SERIAL INPUT (SI): TheSIpinisaninput-onlypinandisusedtoshiftdataintothe

device. The SI pin is used for all data input, including opcodes and address sequences.

SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out
from the device.

SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow
of data to and from the DataFlash. Data is always clocked into the device on the rising
edge of SCK and clocked out of the device on the falling edge of SCK.

CHIP SELECT (CS

device is not selected, data will not be accepted on the SI pin, and the SO pin will
remain in a high-impedance state. A high-to-low transition on the CS
start an operation, and a low-to-high transition on the CS
operation.

8

AT45DB021B

): The DataFlash is selected when the CS pin is low. When the

pin is required to

pin is required to end an

1937F–DFLSH–10/02

AT45DB021B

WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory

cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive
the protect pin high and then use the program commands previously mentioned. The
WP

pin is internally pulled high; therefore, connection of the WP pin is not necessary if
this pin and feature will not be utilized. However, it is recommended that the WP
driven high externally whenever possible.

pin be

RESET

and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET
resume once the RESET

The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET
high; therefore, connection of the RESET
not be utilized. However, it is recommended that the RESET
nally whenever possible.

READY/BUSY

an internally self-timed operation. This pin, which is normally in a high state (through
a1kΩ external pull-up resistor), will be pulled low during programming operations, com-
pare operations, and during page-to-buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.

: A low state on the reset pin (RESET) will terminate the operation in progress

pin. Normal operation can

pin is brought back to a high level.

pin during power-on sequences. The RESET pin is also internally pulled

pin is not necessary if this pin and feature will

pinbedrivenhighexter-

: This open-drain output pin will be driven low when the device is busy in

Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the

device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance
state, and a high-to-low transition on the CS
tion. The SPI mode will be automatically selected on every falling edge of CS
sampling the inactive clock state.

pin will be required to start a valid instruc-

by

1937F–DFLSH–10/02

9

Table 1 . Read Commands

Command SCK Mode Opcode

Continuous Array Read

Inactive Clock Polarity Low or High 68H

SPI Mode 0 or 3 E8H

Main Memory Page Read

Buffer 1 Read

Buffer 2 Read

Status Register Read

Inactive Clock Polarity Low or High 52H

SPI Mode 0 or 3 D2H

Inactive Clock Polarity Low or High 54H

SPI Mode 0 or 3 D4H

Inactive Clock Polarity Low or High 56H

SPI Mode 0 or 3 D6H

Inactive Clock Polarity Low or High 57H

SPI Mode 0 or 3 D7H

Table 2 . Program and Erase Commands

Command SCK Mode Opcode

Buffer 1 Write Any 84H

Buffer 2 Write Any 87H

Buffer 1 to Main Memory Page Program with Built-in Erase Any 83H

Buffer 2 to Main Memory Page Program with Built-in Erase Any 86H

Buffer 1 to Main Memory Page Program without Built-in Erase Any 88H

Buffer 2 to Main Memory Page Program without Built-in Erase Any 89H

Page Erase Any 81H

Block Erase Any 50H

Main Memory Page Program through Buffer 1 Any 82H

Main Memory Page Program through Buffer 2 Any 85H

Table 3 . Additional Commands

Command SCK Mode Opcode

Main Memory Page to Buffer 1 Transfer Any 53H

Main Memory Page to Buffer 2 Transfer Any 55H

Main Memory Page to Buffer 1 Compare Any 60H

Main Memory Page to Buffer 2 Compare Any 61H

Auto Page Rewrite through Buffer 1 Any 58H

Auto Page Rewrite through Buffer 2 Any 59H

Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity

Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).

10

AT45DB021B

1937F–DFLSH–10/02

AT45DB021B

PA5

PA4

PA3

PA2

PA1

PA0

BA8

BA7

Table 4 . Detailed Bit-level Addressing Sequence

Address Byte Address Byte Address Byte

Additional

Don’t Care

Opcode Opcode

50H 01010000rrrrrPPPPPPPxxxxxxxxxxxx N/A

52H 01010010rrrrrPPPPPPPPPPBBBBBBBBB 4Bytes

53H 01010011rrrrrPPPPPPPPPPxxxxxxxxx N/A

54H 01010100xxxxxxxxxxxxxxxBBBBBBBBB 1Byte

55H 01010101rrrrrPPPPPPPPPPxxxxxxxxx N/A

56H 01010110xxxxxxxxxxxxxxxBBBBBBBBB 1Byte

57H 01010111 N/A N/A N/A N/A

58H 01011000rrrrrPPPPPPPPPPxxxxxxxxx N/A

59H 01011001rrrrrPPPPPPPPPPxxxxxxxxx N/A

60H 01100000rrrrrPPPPPPPPPPxxxxxxxxx N/A

61H 01100001rrrrrPPPPPPPPPPxxxxxxxxx N/A

68H 01101000rrrrrPPPPPPPPPPBBBBBBBBB 4Bytes

81H 10000001rrrrrPPPPPPPPPPxxxxxxxxx N/A

82H 10000010rrrrrPPPPPPPPPPBBBBBBBBB N/A

83H 10000011rrrrrPPPPPPPPPPxxxxxxxxx N/A

84H 10000100xxxxxxxxxxxxxxxBBBBBBBBB N/A

85H 10000101rrrrrPPPPPPPPPPBBBBBBBBB N/A

86H 10000110rrrrrPPPPPPPPPPxxxxxxxxx N/A

87H 10000111xxxxxxxxxxxxxxxBBBBBBBBB N/A

88H 10001000rrrrrPPPPPPPPPPxxxxxxxxx N/A

89H 10001001rrrrrPPPPPPPPPPxxxxxxxxx N/A

D2H 11010010rrrrrPPPPPPPPPPBBBBBBBBB 4Bytes

D4H 11010100xxxxxxxxxxxxxxxBBBBBBBBB 1Byte

D6H 11010110xxxxxxxxxxxxxxxBBBBBBBBB 1Byte

D7H 11010111 N/A N/A N/A N/A

E8H 11101000rrrrrPPPPPPPPPPBBBBBBBBB 4Bytes

Note: r = Reserved Bit

P = Page Address Bit
B = Byte/Buffer Address Bit
x=Don’tCare

Reserved

Reserved

Reserved

Reserved

Reserved

PA9

PA8

PA7

PA6

BA6

BA5

BA4

BA3

BA2

BA1

BA0

Bytes

Required

11

1937F–DFLSH–10/02

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

CC

+0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

DC and AC Operating Range

AT45DB021B

Operating Temperature (Case)

VCCPower Supply

(1)

Com.

Ind.

Note: 1. After power is applied and VCCis at the minimum specified datasheet value, the system should wait 20 ms before an

operational mode is started.

0°Cto70°C

-40°Cto85°C

2.7V to 3.6V

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

SB

(1)

I

CC1

I

CC2

I

LI

I

LO

V

IL

V

IH

V

OL

V

OH

Note: 1. I

Standby Current CS, RESET,WP=VCC, all inputs

210µA

at CMOS levels

Active Current, Read
Operation

Active Current,

f=15MHz;I
V

=3.6V

CC

OUT

=0mA;

410mA

VCC=3.6V 15 35 mA

Program/Erase Operation

Input Load Current VIN=CMOSlevels 1 µA

Output Leakage Current V

= CMOS levels 1 µA

I/O

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL=1.6mA;VCC=2.7V 0.4 V

Output High Voltage IOH=-100µA VCC-0.2V V

during a buffer read is 20mA maximum.

cc1

12

AT45DB021B

1937F–DFLSH–10/02

AT45DB021B

AC Characteristics

Symbol Parameter Min Max Units

f

SCK

f

CAR

t

WH

t

WL

t

CS

t

CSS

t

CSH

t

CSB

t

SU

t

H

t

HO

t

DIS

t

V

t

XFR

t

EP

t

P

t

PE

t

BE

t

RST

t

REC

SCK Frequency 20 MHz

SCK Frequency for Continuous Array Read 20 MHz

SCK High Time 22 ns

SCK Low Time 22 ns

Minimum CS High Time 250 ns

CS Setup Time 250 ns

CS Hold Time 250 ns

CS High to RDY/BUSY Low 200 ns

Data In Setup Time 5 ns

Data In Hold Time 10 ns

Output Hold Time 0 ns

Output Disable Time 18 ns

Output Valid 20 ns

Page to Buffer Transfer/Compare Time 250 µs

Page Erase and Programming Time 20 ms

Page Programming Time 14 ms

Page Erase Time 8ms

Block Erase Time 12 ms

RESET Pulse Width 10 µs

RESET Recovery Time 1 µs

1937F–DFLSH–10/02

13

Input Test Waveforms and Measurement Levels

Output Test Load

DRIVING

LEVELS

tR,tF< 3 ns (10% to 90%)

AC

2.4V

0.45V

DEVICE
UNDER

TEST

AC

2.0
MEASUREMENT

0.8
LEVEL

30 pF

AC Waveforms

Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0

Waveform 2 – Inactive ClockPolarityHighand SPI Mode 3

Two different timing diagrams are shown below. Waveform 1 shows the SCK signal
being low when CS
nal being high when CS

makes a high-to-low transition, and Waveform 2 shows the SCK sig-

makes a high-to-low transition. Both waveforms show valid
timing diagrams. The setup and hold times for the SI signal are referenced to the low-to­high transition on the SCK signal.

Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2
shows timing that is compatible with SPI Mode 3.

t

CS

SCK

HIGH IMPEDANCE

SO

SI

CS

SCK

t

CSS

VALID IN

t

WL

t

WH

t

t

CSS

t

SU

WH

t

WL

t

V

t

H

t

VALID OUT

HO

t

CSH

t

CSH

CS

t

DIS

HIGH IMPEDANCE

t

CS

14

AT45DB021B

SO

t

HIGH Z

SI

V

t

SU

VALID IN

t

HO

VALID OUT

t

H

t

DIS

HIGH IMPEDANCE

1937F–DFLSH–10/02

Reset Timing (Inactive Clock Polarity Low Shown)

CS

SCK

RESET

t

RST

t

REC

AT45DB021B

t

CSS

SO

HIGH IMPEDANCE HIGH IMPEDANCE

SI

Note: The CS signal should be in the high state before the RESET signal is deasserted.

Command Sequence for Read/Write Operations (except Status Register Read)

SI CMD 8 bits

MSB

Reserved for

larger densities

Page Address

(PA9-PA0)

Notes: 1. “r” designates bits reserved for larger densities.

2. It is recommended that “r” be a logical “0” for densities of 2M bits or smaller.

3. For densities larger than 2M bits, the “r” bits become the most significant Page Address bit for the appropriate density.

8 bits

8 bits

Byte/Buffer Address

(BA8-BA0/BFA8-BFA0)

LSBr r r r r X X X X X X X X X X X X X X X X X X X

1937F–DFLSH–10/02

15

Write Operations The following block diagram and waveforms illustrate the various write sequences

y

available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

BUFFER 1 TO

MAIN MEMORY

PAGE PROGRAM

BUFFER 1

WRITE

Main Memory Page Program through Buffers

CS

SI

CMD n n+1 Last Byte

rrrr r, PA9-7

PA6-0, BFA8 BFA7-0

Buffer Write

MAIN MEMORY

PAGE PROGRAM

THROUGH BUFFER 2

MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER 1

I/O INTERFACE

SI

· Completes writing into selected buffer

· Starts self-timed erase/program operation

BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM

BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)

BUFFER 2
WRITE

· Completes writing into selected buffer

CS

SI

CMD X

X···X, BFA8

BFA7-0

n

n+1

Last Byte

Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)

Starts self-timed erase/program operation

CS

X

n = 1st byte read
n+1 = 2nd byte read

1937F–DFLSH–10/02

Each transition represents

8 bits and 8 clock c

16

AT45DB021B

cles

SI

CMD rrrr r, PA9-7 PA6-0, X

AT45DB021B

y

Read Operations The following block diagram and waveforms illustrate the various read sequences

available.

FLASH MEMORY ARRAY

PAGE (264 BYTES)

MAIN MEMORY

PAGE TO

BUFFER 1

BUFFER 2 (264 BYTES)BUFFER 1 (264 BYTES)

BUFFER 1

READ

MAIN MEMORY PAGE READ

I/O INTERFACE

SO

Main Memory Page Read

CS

XXX

SO

SI

CMD

rrrr r, PA9-7

PA6-0, BA8

BA7-0 X

Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)

MAIN MEMORY
PAGE TO
BUFFER 2

BUFFER 2
READ

n n+1

Buffer Read

Each transition represents

8 bits and 8 clock c

1937F–DFLSH–10/02

CS

SI

SO

cles

CS

SO

Starts reading page data into buffer

SI

CMD

CMD

X

rrrr r, PA9-7

X···X, BFA8

PA6-0, X X

BFA7-0

X

n n+1

n=1stbyteread
n+1 = 2nd byte read

17

Detailed Bit-level Read Timing – Inactive Clock Polarity Low

Continuous Array Read (Opcode: 68H)

CS

SCK

SO

SI

t

SU

12 63 64 65 66 67 68

1XX

0

t

V

HIGH-IMPEDANCE

Main Memory Page Read (Opcode: 52H)

CS

SCK

SI

t

SU

12345 60 61 62 63 64 65 66 67

COMMAND OPCODE

0

10

1

0

DATA OUT

D7D

6D5

XXX

LSB MSB

D2D1D0D7D6D

BIT 2111

OF

PAGE n

XX

BIT 0

OF

PAGE n+1

5

18

SO

AT45DB021B

HIGH-IMPEDANCE

t

V

DATA OUT

D

7

MSB

D

D

6

5

1937F–DFLSH–10/02

AT45DB021B

Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)

Buffer Read (Opcode: 54H or 56H)

CS

SCK

SI

SO

t

SU

12345 36 37 38 39 40 41 42 43

COMMAND OPCODE

0

10

1

0

HIGH-IMPEDANCE

Status Register Read (Opcode: 57H)

CS

SCK

SI

t

SU

12345 7891011 12 16 17

COMMAND OPCODE

0

10

1

0

XXX

6

111

XX

t

V

DATA OUT

D

7

MSB

D

D

6

5

SO

1937F–DFLSH–10/02

HIGH-IMPEDANCE

t

V

STATUS REGISTER OUTPUT

D

D

7

MSB

D

6

5

D

1

D

D

0

LSB MSB

7

19

Detailed Bit-level Read Timing – Inactive Clock Polarity High

Continuous Array Read (Opcode: 68H)

CS

SCK

SI

SO

12 63 64 65 66 67

t

SU

1XXX

0

t

V

HIGH-IMPEDANCE

Main Memory Page Read (Opcode: 52H)

CS

SCK

SI

12345 61 62 63 64 65 66 67

t

SU

COMMAND OPCODE

1

0

0

10

DATA OUT

D7D6D

XXX

LSB MSB

5

D2D1D0D7D

BIT 2111

OF

PAGE n

XX

BIT 0

OF

PAGE n+1

D

6

5

68

20

SO

AT45DB021B

HIGH-IMPEDANCE

t

V

D

MSB

7

DATA OUT

D

D

6

5

D

4

1937F–DFLSH–10/02

AT45DB021B

Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)

Buffer Read (Opcode: 54H or 56H)

CS

SCK

SI

SO

12345 37 38 39 40 41 42 43

t

SU

COMMAND OPCODE

1

0

0

10

HIGH-IMPEDANCE

Status Register Read (Opcode: 57H)

CS

SCK

SI

SO

12345 7891011 12 17 18

t

SU

0

COMMAND OPCODE

0

10

1

HIGH-IMPEDANCE

XXX

6

111

t

V

D

MSB

XX

t

V

D

MSB

STATUS REGISTER OUTPUT

D

D

7

6

D

5

4

DATA OUT

D

7

D

6

D

0

LSB MSB

44

D

5

4

D

D

7

6

1937F–DFLSH–10/02

21

Detailed Bit-level Read Timing – SPI Mode 0

Continuous Array Read (Opcode: E8H)

CS

SCK

SI

SO

t

SU

12 62 63 64 65 66 67

1XXX

1

t

V

HIGH-IMPEDANCE

Main Memory Page Read (Opcode: D2H)

CS

SCK

SI

t

SU

12345 60 61 62 63 64 65 66 67

COMMAND OPCODE

0

10

1

1

DATA OUT

D7D

D

6

XXX

LSB MSB

5

D2D1D0D7D

BIT 2111

OF

PAGE n

XX

BIT 0

OF

PAGE n+1

D

6

5

22

SO

AT45DB021B

HIGH-IMPEDANCE

t

V

D

7

MSB

DATA OUT

D

D

6

5

D

4

1937F–DFLSH–10/02

Detailed Bit-level Read Timing – SPI Mode 0 (Continued)

Buffer Read (Opcode: D4H or D6H)

CS

AT45DB021B

SCK

SO

t

SU

SI

12345 36 37 38 39 40 41 42 43

COMMAND OPCODE

0

10

1

1

HIGH-IMPEDANCE

Status Register Read (Opcode: D7H)

CS

SCK

SI

SO

t

SU

12345 7891011 12 16 17

COMMAND OPCODE

0

10

1

1

HIGH-IMPEDANCE

XXX

6

111

t

V

D

MSB

7

XX

t

V

D

MSB

7

DATA OUT

D

6

STATUS REGISTER OUTPUT

D

6

D

D

4

5

D

D

5

1

D

4

D

D

0

LSB MSB

7

1937F–DFLSH–10/02

23

Detailed Bit-level Read Timing – SPI Mode 3

Continuous Array Read (Opcode: E8H)

CS

SCK

SI

SO

12 63 64 65 66 67

t

SU

1XXX

1

t

V

HIGH-IMPEDANCE

Main Memory Page Read (Opcode: D2H)

CS

SCK

SI

12345 61 62 63 64 65 66 67

t

SU

COMMAND OPCODE

0

10

1

1

DATA OUT

D7D6D

XXX

LSB MSB

5

D2D1D0D7D

BIT 2111

OF

PAGE n

XX

BIT 0

OF

PAGE n+1

D

6

5

68

24

SO

AT45DB021B

HIGH-IMPEDANCE

t

V

D

MSB

7

DATA OUT

D

D

6

5

D

4

1937F–DFLSH–10/02

Detailed Bit-level Read Timing – SPI Mode 3 (Continued)

Buffer Read (Opcode: D4H or D6H)

CS

AT45DB021B

SCK

12345 37 38 39 40 41 42 43

t

SU

COMMAND OPCODE

SI

SO

1

1

10

0

HIGH-IMPEDANCE

Status Register Read (Opcode: D7H)

CS

SCK

SI

12345 7891011 12 17 18

t

SU

COMMAND OPCODE

0

10

1

1

XXX

6

111

XX

t

V

D

MSB

7

DATA OUT

D

D

6

5

44

D

4

SO

1937F–DFLSH–10/02

HIGH-IMPEDANCE

t

V

D

MSB

STATUS REGISTER OUTPUT

D

D

7

6

D

5

4

D

D

0

LSB MSB

D

7

6

25

Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array

START

provide address

and data

BUFFER WRITE

(84H, 87H)

MAIN MEMORY PAGE PROGRAM

THROUGH BUFFER

(82H, 85H)

BUFFER TO MAIN

MEMORY PAGE PROGRAM

(83H, 86H)

END

Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array

page-by-page.

2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.

3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.

26

AT45DB021B

1937F–DFLSH–10/02

Figure 2. Algorithm for Randomly Modifying Data

AT45DB021B

START

provide address of

page to modify

TO BUFFER TRANSFER

MAIN MEMORY PAGE PROGRAM

THROUGH BUFFER

(82H, 85H)

AUTO PAGE REWRITE

MAIN MEMORY PAGE

(53H, 55H)

(58H, 59H)

INCREMENT PAGE

ADDRESS POINTER

If planning to modify multiple
bytes currently stored within
a page of the Flash array

BUFFER WRITE

(84H, 87H)

BUFFER TO MAIN

MEMORY PAGE PROGRAM

(83H, 86H)

(2)

(2)

END

Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000

cumulative page erase/program operations.

2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.

3. Other algorithms can be used to rewrite portions of the Flash array. Low power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.

Sector Addressing

PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 - PA0 Sector

0000000X 0

00XXXXX X 1

01XXXXX X 2

1XXXXXX X 3

27

1937F–DFLSH–10/02

Ordering Information

I

(mA)

f

SCK

(MHz)

20 10 0.01 AT45DB021B-CC

20 10 0.01 AT45DB021B-CI

CC

Ordering Code Package Operation RangeActive Standby

AT45DB021B-RC
AT45DB021B-SC
AT45DB021B-TC

AT45DB021B-RI
AT45DB021B-SI
AT45DB021B-TI

9C1
28R
8S2
28T

9C1
28R
8S2
28T

Commercial

(0°Cto70°C)

Industrial

(-40°Cto85°C)

Package Type

9C1 9-ball (3 x 3 Array), 1.0 mm Pitch, 5 x 5 mm Plastic Chip-scale Ball Grid Array Package (CBGA)

28R 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline Package (SOIC)

8S2 8-lead, 0.210" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

28T 28-lead, Plastic Thin Small Outline Package (TSOP)

28

AT45DB021B

1937F–DFLSH–10/02

Packaging Information

9C1 – CBGA

Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.

AT45DB021B

5.10(0.201)

4.90(0.193)

A1 ID

5.10(0.201)

4.90(0.193)

1.50(0.059) REF

1.00 (0.0394) BSC

NON-ACCUMULATIVE

1.00 (0.0394) BSC

NON-ACCUMULATIVE

SIDE VIEW

TOP VIEW

1.20(0.047)MAX

321

A

B

C

BOTTOM VIEW

2.0 (0.079)

1.50(0.059) REF

2.0 (0.079)

0.40 (0.016)
DIA BALL TYP

0.25(0.010)MIN

2325 Orchard Parkway

R

San Jose, CA 95131

1937F–DFLSH–10/02

TITLE

9C1, 9-ball (3 x 3 Array), 5 x 5 x 1.2 mm Body, 1.0 mm Ball

Pitch Chip-scale Ball Grid Array Package (CBGA)

DRAWING NO.

9C1

04/11/01

REV.

A

29

28R – SOIC

Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.

0.508(0.020)

0.356(0.014)

PIN 1

0º ~ 8º

1.27(0.050) BSC

18.50(0.728)

18.00(0.708)

0.014(0.356)

0.002(0.051)

1.27(0.050)

0.94(0.037)

8.79(0.346)

8.59(0.338)

12.50(0.494)

11.70(0.460)

2.79(0.110)

2.39(0.094)

0.305(0.012)

0.203(0.008)

30

2325 Orchard Parkway

R

San Jose, CA 95131

AT45DB021B

TITLE

28R, 28-lead, 0.330" Body, Plastic Gull Wing Small Outline (SOIC)

DRAWING NO.

28R

1937F–DFLSH–10/02

04/11/01

REV.

A

8S2 – EIAJ SOIC

AT45DB021B

1

H

N

Top View

e

b

A

D

COMMON DIMENSIONS

(Unit of Measure = mm)

Side View

SYMBOL

A 1.78 2.03

A1

C

L

E

End View

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.

A1 0.05 0.33

b 0.35 0.51 5

C 0.18 0.25 5

D 5.13 5.38

E 5.13 5.41 2, 3

H 7.62 8.38

L 0.51 0.89

e 1.27 BSC 4

MIN

NOM

MAX

NOTE

5/2/02

2325 Orchard Parkway

R

San Jose, CA 95131

1937F–DFLSH–10/02

TITLE

8S2, 8-lead, 0.209" Body, Plastic Small

Outline Package (EIAJ)

DRAWING NO.

8S2

REV.

B

31

28T – TSOP

PIN 1

Pin 1 Identifier

D1

D

e

E

b

A2

A

A1

Notes: 1. This package conforms to JEDEC reference MO-183.

2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

0º ~ 5º

SEATING PLANE

SYMBOL

c

L

L1

GAGE PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A ––1.20

A1 0.05 – 0.15

A2 0.90 1.00 1.05

D 13.20 13.40 13.60

D1 11.70 11.80 11.90 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.55 BASIC

NOM

MAX

NOTE

32

2325 Orchard Parkway

R

San Jose, CA 95131

AT45DB021B

TITLE

28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline

Package, Type I (TSOP)

DRAWING NO.

28T

1937F–DFLSH–10/02

10/18/01

REV.

B

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East Kilbride G75 0QR, Scotland
TEL [phone]
FAX [phone]

RF/Automotive

Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL [phone]
FAX [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL [phone]
FAX [phone]

Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom

Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
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FAX [phone]

e-mail

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© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
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