– 15 mA Active Current
– 40 µA CMOS Standby Current
•
Fast Read Access Time - 150 ns
•
Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Sectors (64 bytes / sec tor)
– Internal Address and Data Latches for 64 Bytes
•
Fast Sector Program Cycle Time - 20 ms Max.
•
Internal Program Control and Timer
•
DAT A Polling for End of Program Detection
•
Typical Endurance > 10,000 Cycles
•
CMOS and TTL Compatible Inputs and Outputs
•
Commercial and Industrial Temperature Ranges
256K (32K x 8)
3-volt Only
Flash Memory
Description
The AT29LV256 is a 3-volt-only in-system Flash Programmable Erasable Read Only
Memory (PEROM). Its 256K of mem ory is orga nized as 32,768 words by 8 bi ts. Manufactured with Atmel ’s advanced nonvolatile CMOS technology , the device offers
access times to 150 ns with power dissipation of just 54 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less
than 40 µA. The device endurance is such that any sector can typically be written to in
excess of 10,000 times.
To allow for simple in-system reprogrammability, the
AT29LV256 does not require high input voltages for programming. Thre e-vol t-only c omman ds dete rmine th e operation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the
AT29LV256 is performed on a sector basis; 64 bytes of
data are loaded into the device and then simultaneou sly
programmed.
Block Diagram
During a reprogram cycle, the address locations and 64
bytes of data are captured at microprocessor speed and
internally latched, freeing the address and data bus for
other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and
then program the latched data using an internal control
timer. The end of a program cycle can be detected by
polling of I/O7. Once the end of a program cy cl e has
DATA
been detected, a new access for a read or program can
begin.
Device Operation
READ:
When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE
control gives designers flexibility in preventing bus contention.
SOFTWARE DATA PROTECTION PROGRAMMING:
AT29LV256 has 512 individual secto rs, each 64 by tes.
Using the software data protection feature, byte loads are
used to enter the 64 bytes o f a sector to be programmed.
The AT29LV256 can only be progr ammed or reprogrammed using the software data protection feature. The
device is programmed on a se ctor basis. If a byte of data
within the sect or is to be ch anged, dat a for the en tire 64byte sector must be loaded in to the device. The
AT29LV256 automatically does a sector erase prior to
loading the data into the sector. An erase command is not
required.
Software data protection p rotec ts the dev ice from inadv ertent programming. A series of three program commands to
specific addresses with specific data must be presented to
the device before programming may occur. The same three
program commands must begin each program operation.
All software program co mmands must ob ey the sec tor program timing specifications. Power transitions will not reset
The AT29LV256 is ac cessed like an EPROM .
and OE are low and WE is high, the data stored
or OE is high. This dual-line
The
the software data pr otection feature, however th e softwa re
feature will guard against inadvertent program cycles during power transitions.
Any attempt to write to the device without the 3-byte command sequen ce will start the int ernal wri te tim ers. N o data
will be written to the device; however, for the duration of
, a read operation will effectively be a polling operation.
t
WC
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a l ow pulse
on the WE
and OE
or WE, whichever occurs last. The data is latched by
CE
the first rising edge of CE
The 64 bytes of data must be lo ade d into eac h sect or. Any
byte that is not loaded during the programming of its sector
will be erased to read FFh. Once the bytes of a sector are
loaded into the device, they are simult aneously programmed during the internal programming period. After the
first data byte h as been load ed in to the de vice, s ucces sive
bytes are entered in the same manner. Each new byte to
be programmed must ha ve its hi gh to low t ransiti on on WE
(or CE) within 150 µs of the low to high transition of WE (or
) of the preceding byte. If a high to low transition is not
CE
detected within 150 µs of t he la st lo w t o hig h tra ns ition, th e
load period will end and the internal programming period
or CE input with CE or WE low (respectively)
high. The address is lat ched on the falling edge of
or WE.
2
AT29LV256
AT29LV256
will start. A6 to A14 spec ify the sector ad dress . The sect or
address must be valid during each high to low transition of
(or CE). A0 to A5 specify the byte addre ss within the
WE
sector. The bytes may be loade d in any order; sequ ential
loading is not required. Once a programming operation has
been initiated, an d for the dura tion o f t
, a read operation
WC
will effectively be a polling operation.
HARDWARE DATA PROTE CTION:
Hardware features
protect against inadvertent programs to the AT29LV256 in
the following ways: (a) V
(typical), the program function is inhibited; (b) V
delay—once V
has reached the VCC sense level, the
CC
sense—if VCC is below 1.8V
CC
power on
CC
device will automa tically t ime out 10 ms (typic al) befo re
programming; (c) Progr am inh ibit— ol ding an y one o f OE
low, CE high or WE high inh ibits program cycles; and
(d) Noise filter—p ulses of les s than 15 ns (t ypical) on th e
or CE inputs will not initiate a program cycle.
WE
INPUT LEVELS:
supply, the address inputs and control inputs (OE
) may be driven from 0 to 5.5V without adversely affect-
WE
While operati ng with a 3. 3V ±10% p ower
, CE and
ing the operation of the devic e. The I/O lin es can only be
driven from 0 to 3.6 volts.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product. In addi tion, users may wis h to use the
software product identification mode to identify the part (i.e.
using the device code), and hav e the syst em softw are use
the appropriate sector size for program operations. In this
manner, the user can have a common board design for
256K to 4-megabit densities and, with each density’s sector
size in a memory ma p, ha ve the sy st em s oft war e ap pl y th e
appropriate sector size.
For details, see O perat ing Mode s (for ha rdware operat ion)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA
POLLING:
The AT29LV256 features DATA
polling
to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA
polling may
begin at any time during the program cycle.
TOGGLE BIT:
In addition to DATA
polling the
AT29LV256 pr ovides anothe r meth od for determ ining the
end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Exami ning the to ggle bit
may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE:
The entire device can
be erased by using a 6-byte software code. Please see
Software Chip Erase application note for details.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature.....................................-65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on A9 (including NC Pins)
with Respect to Ground...................................-0.6V to +13.5V
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the de vic e. T his is a stres s r ating o nly an d
functional opera tion of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reli abi li ty.
Address to Output Delay150200250ns
CE to Output Delay150200250ns
OE to Output De lay07001000120ns
CE or OE to Output Float040050060ns
Output Hold from OE, CE or Address,
whichever occurred f irst
AT29LV256
AT29L V256-15AT29LV256-20AT29LV256-25
UnitsMinMaxMinMaxMinMax
000ns
AC Read Waveforms
Notes: 1. CE may be delayed up to t
(1)(2)(3)(4)
ACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE with out im pa ct on tCE or by t
without impact on t
is specified from OE or CE whichever occurs first (CL = 5 pF).
3. t
DF
ACC
.
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
- tCE after the address transition without impact on t
Output Test Load
ACC
.
- tOE after an address change
ACC
t
, tF < 5 ns
R
Pin Capacitance
f = 1 MHz, T = 25°C
SymbolTypMaxUnitsConditions
C
IN
C
OUT
Note:1. These parameters are characterized and not 100% tested.
(1)
46pFV
812pFV
IN
OUT
= 0V
= 0V
5
AC Byte Load Characteristics
SymbolParameterMinMaxUnits
, t
t
AS
t
AH
t
CS
t
CH
t
WP
t
DS
tDH, t
t
WPH
OES
OEH
Address, OE Set-up Time10ns
Address Hold Time100ns
Chip Select Set-up Time0ns
Chip Select Hold Time0ns
Write Pulse Width (WE or CE)200ns
Data Set-up Time100ns
Data, OE Hold Time10ns
Write Pulse Width High200ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
(1)(2)
6
AT29LV256
AT29LV256
Program Cyc le Characteristics
SymbolParameterMinMaxUnits
t
WC
t
AS
t
AH
t
DS
t
DH
t
WP
t
BLC
t
WPH
Software Protected Program Waveform
Write Cycle Time20ms
Address Set-up Time10ns
Address Hold Time100ns
Data Set-up Time100ns
Data Hold Time10ns
Write Pulse Width 200ns
Byte Load Cycle Time150
Write Pulse Width High200ns
(1)(2)(3)
s
µ
Notes: 1. OE must be high when WE and CE are both low.
2. A6 through A14 must spe cify the se ctor addres s during each hig h to low transiti on of WE (or CE) after the software code has
been entered.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
Marks bearing
Terms and product names in this document may be trademarks of others.
and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Printed on recycled paper.
0563B–10/98//xM
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