Rainbow Electronics AT29LV010A User Manual

Features

• Single Supply Voltage, Range 3V to 3.6V

• 3-volt Only Read and Write Operation

• Software Protected Programming

• Fast Read Access Time - 120 ns

• Low Power Dissipation

– 15mAActiveCurrent
– 40 µA CMOS Standby Current

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program)
– 1024 Sectors (128 Bytes/Sector)
– Internal Address and Data Latches for 128 Bytes

• Two 8K Bytes Boot Blocks with Lockout

• Fast Sector Program Cycle Time - 20 ms

• Internal Program Control and Timer

• DATA Polling for End of Program Detection

• Typical Endurance > 10,000 Cycles

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

1-megabit
(128K x 8)
3-volt Only
Flash Memory

Description

The AT29LV010A is a 3-volt only in-system Flash programmable and erasable read
only memory (Flash). Its 1 megabit of memory is organized as 131,072 bytes by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 120 ns with power dissipation of just 54 mW over the commercial tem­perature range. When the device is deselected, the CMOS standby current is less
than 40 µA. The device endurance is such that any sector can typically be written to in
excess of 10,000 times.

Pin Configurations

Pin Name Function

A0 - A16 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

I/O0

Chip Enable

Output Enable

Write Enable

PLCC Top View

A12

A15

A16NCVCCWENC

432

1

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

323130

14151617181920

I/O1

I/O2

I/O3

I/O4

I/O5

GND

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

A11

A13
A14

WE

VCC

A16
A15
A12

A9
A8

NC

NC

A7
A6
A5
A4

TSOP Top View

Type 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

AT29LV010A

Rev. 0520D–FLASH–05/02

1

Block Diagram

To allow for simple in-system reprogrammability, the AT29LV010A does not require high
input voltages for programming. Three-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from an EPROM. Repro­gramming the AT29LV010A is performed on a sector basis; 128 bytes of data are
loaded into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are captured at
microprocessor speed and internally latched, freeing the address and data bus for other
operations. Following the initiation of a program cycle, the device will automatically
erase the sector and then program the latched data using an internal control timer. The
end of a program cycle can be detected by DATA
gram cycle has been detected, a new access for a read or program can begin.

polling of I/O7. Once the end of a pro-

Device Operation

READ: The AT29LV010A is accessed like an EPROM. When CE and OE are low and

WE

is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.

SOFTWARE DATA PROTECTION PROGRAMMING: The AT29LV010A has 1024 indi­vidual sectors, each 128 bytes. Using the software data protection feature, byte loads
are used to enter the 128 bytes of a sector to be programmed. The AT29LV010A can
only be programmed or reprogrammed using the software data protection feature. The
device is programmed on a sector basis. If a byte of data within the sector is to be
changed, data for the entire 128-byte sector must be loaded into the device. The data in
any byte that is not loaded during the programming of its sector will be indeterminate.
The AT29LV010A automatically does a sector erase prior to loading the data into the
sector. An erase command is not required.

Software data protection protects the device from inadvertent programming. A series of
three program commands to specific addresses with specific data must be presented to
the device before programming may occur. The same three program commands must
begin each program operation. All software program commands must obey the sector
program timing specifications. Power transitions will not reset the software data protec­tion feature; however, the software feature will guard against inadvertent program cycles
during power transitions.

Any attempt to write to the device without the 3-byte command sequence will start the
internal write timers. No data will be written to the device; however, for the duration of
t

, a read operation will effectively be a polling operation.

WC

2

AT29LV010A

0520D–FLASH–05/02

AT29LV010A

After the software data protection’s 3-byte command code is given, a byte load is per­formed by applying a low pulse on the WE
and OE

high. The address is latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE

The 128 bytes of data must be loaded into each sector. Any byte that is not loaded dur­ing the programming of its sector will be erased to read FFh. Once the bytes of a sector
are loaded into the device, they are simultaneously programmed during the internal pro­gramming period. After the first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to be programmed must have its
high to low transition on WE
CE

) of the preceding byte. If a high to low transition is not detected within 150 µs of the

(or CE)within150µs of the low to high transition of WE (or

last low to high transition, the load period will end and the internal programming period
will start. A7 to A16 specify the sector address. The sector address must be valid during
each high to low transition of WE

(or CE). A0 to A6 specify the byte address within the
sector. The bytes may be loaded in any order; sequential loading is not required. Once a
programming operation has been initiated, and for the duration of t
will effectively be a polling operation.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
programs to the AT29LV010A in the following ways: (a) V
(typical), the program function is inhibited; (b) V
reached the V

sense level, the device will automatically time out 10 ms (typical)

CC

before programming; (c) Program inhibit – holding any one of OE
high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on
the WE

or CE inputs will not initiate a program cycle.

or CE input with CE or WE low (respectively)

or WE.

, a read operation

WC

sense – if VCCis below 1.8V

CC

power on delay – once VCChas

CC

low, CE high or WE

INPUT LEVELS: While operating with a 3.3V ± 0.3V power supply, the address inputs
and control inputs (OE
affecting the operation of the device. The I/O lines can be driven from 0 to V

,CEand WE) may be driven from 0 to 5.5V without adversely

+0.6V.

CC

PRODUCT IDENTIFICATION: The product identification mode identifies the device
and manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e. using the device code), and
have the system software use the appropriate sector size for program operations. In this
manner, the user can have a common board design for 256K to 4-megabit densities
and, with each density’s sector size in a memory map, have the system software apply
the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identifi­cation. The manufacturer and device code is the same for both modes.

DATA POLLING: The AT29LV010A features DATA

polling to indicate the end of a
program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once the program cycle has been
completed, true data is valid on all outputs and the next cycle may begin. DATA

polling

may begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA

polling the AT29LV010A provides another method
for determining the end of a program or erase cycle. During a program or erase opera­tion, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro­gram cycle.

0520D–FLASH–05/02

3

OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte

software code. Please see Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT: The AT29LV010A has two designated
memory blocks that have a programming lockout feature. This feature prevents pro­gramming of data in the designated block once the feature has been enabled. Each of
these blocks consists of 8K bytes; the programming lockout feature can be set indepen­dently for either block. While the lockout feature does not have to be activated, it can be
activated for either or both blocks.

These two 8K memory sections are referred to as
bring up a system can be contained in a boot block. The AT29LV010A blocks are
located in the first 8K bytes of memory and the last 8K bytes of memory. The boot block
programming lockout feature can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the programming lockout feature
has been activated, the data in that block can no longer be erased or programmed; data
in other memory locations can still be changed through the regular programming meth­ods. To activate the lockout feature, a series of seven program commands to specific
addresses with specific data must be performed. Please see Boot Block Lockout Fea­ture Enable Algorithm.

If the boot block lockout feature has been activated on either block, the chip erase func­tion will be disabled.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product
Identification Entry and Exit sections. When the device is in the software product identifi­cation mode, a read from location 00002H will show if programming the lower address
boot block is locked out while reading location 1FFF2H will do so for the upper boot
block. If the data is FE, the corresponding block can be programmed; if the data is FF,
the program lockout feature has been activated and the corresponding block cannot be
programmed. The software product identification exit mode should be used to return to
standard operation.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

CC

+0.6V

boot blocks

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

. Secure code which will

Voltage on A9 (including NC Pins)

with Respect to Ground ...................................-0.6V to +13.5V

4

AT29LV010A

0520D–FLASH–05/02

DC and AC Operating Range

AT29LV010A

AT29LV010A-12 AT29LV010A-15 AT29LV010A-20 AT29LV010A-25

Operating
Temperature (Case)

V

Power Supply

CC

(1)

Com. 0°C-70°C0°C-70°C

Ind. -40°C-85°C-40°C-85°C

3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V 3.3V ± 0.3V

0°C-70°C 0°C-70°C

-40°C-85°C -40°C-85°C

Notes: 1. After power is applied and VCCis at the minimum specified data sheet value, the system should wait 20 ms before an oper-

ational mode is started.

2.

Not recommended for New Designs.

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

5V Chip Erase V

Standby/Write Inhibit V

IL

V

IL

IL

IH

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

Product Identification

Hardware V

Software

Notes: 1. X can be V

(5)

or VIH.

IL

IL

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code is 1F. The Device Code is 35.

5. See details under Software Product Identification Entry/Exit.

V

IL

V

IH

V

IH

(1)

X

IL

IH

V

IL

V

IH

V

IL

V

IL

Ai D

Ai D

Ai

OUT

IN

XXHighZ

IH

X

XHighZ

V

IH

A1 - A16 = VIL,A9=VH,

A1 - A16 = VIL,A9=VH,

A0 = VIL,A1-A16=V

A0 = VIH,A1-A16=V

(3)

(3)

A0 = V

A0 = V

IL

IL

Manufacturer Code

IL

Device Code

IH

Manufacturer Code

Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH

0520D–FLASH–05/02

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

CC

Com. 40 µA

1 µA

1 µA

Ind. 50 µA

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

OUT

CC

=0mA;VCC=3.6V 15 mA

1mA

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL=1.6mA;VCC=3.0V 0.45 V

Output High Voltage IOH=-100µA; VCC=3.0V 2.4 V

5