Rainbow Electronics AT29C512 User Manual

Features

• Fast Read Access Time – 70 ns

• 5-volt Only Reprogramming

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program)
– 512 Sectors (128 Bytes/Sector)
– Internal Address and Data Latches for 128 Bytes

• Internal Program Control and Timer

• Hardware and Software Data Protection

• FastSectorProgramCycleTime–10ms

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 50mAActiveCurrent
–100µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

Description

The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only
memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man­ufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW over the commercial tem­perature range. When the device is deselected, the CMOS standby current is less
than 100 µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.

512K (64K x 8)
5-volt Only
Flash Memory

AT29C512

Pin Configurations

Pin Name Function

A0 - A15 Addresses

CE

OE

WE

I/O0 - I

/

O7 Data Inputs/Outputs

NC No Connect

1

A11

2

A9

3

A8

4

A13

5

A14

6

NC

7

WE

8

VCC

9

NC

10

NC

11

A15

12

A12

13

A7

14

A6

15

A5

16

A4

Chip Enable

Output Enable

Write Enable

TSOP Top View

Type 1

DIP Top View

1

NC

2

NC

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14

I/O1

15

I/O2

16

GND

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

PLCC Top View

A12

A15NCNC

432

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14151617181920

I/O1

I/O2

GND

1

I/O3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

VCCWENC

323130

I/O4

I/O5

29
28
27
26
25
24
23
22
21

I/O6

VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

Rev. 0456E–FLASH–5/02

1

Block Diagram

To allow for simple in-system reprogrammability, the AT29C512 does not require high input
voltages for programming. Five-volt-only commands determine the operation of the device.
Reading data out of the device is similar to reading from an EPROM. Reprogramming the
AT29C512 is performed on a sector basis; 128 bytes of data are loaded into the device and
then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and then program the latched data using
an internal control timer. The end of a program cycle can be detected by DATA
Once the end of a program cycle has been detected, a new access for a read or program can
begin.

polling of I/O7.

Device Operation

READ: TheAT29C512isaccessedlikeanEPROM.WhenCEand OE are low and WE is

high, the data stored at the memory location determined by the address pins is asserted on
the outputs. The outputs are put in the high impedance state whenever CE
dual-line control gives designers flexibility in preventing bus contention.

BYTE LOAD: Byte loads are used to enter the 128 bytes of a sector to be programmed or
the software codes for data protection. A byte load is performed by applying a low pulse on the

or CE input with CE or WE low (respectively) and OE high. The address is latched on the

WE
falling edge of CE
CE

or WE.

PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a sector
is to be changed, data for the entire sector must be loaded into the device. Any byte that is not
loaded during the programming of its sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they are simultaneously programmed during the internal program­ming period. After the first data byte has been loaded into the device, successive bytes are
entered in the same manner. Each new byte to be programmed must have its high-to-low tran­sition on WE
byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition,
the load period will end and the internal programming period will start. A7 to A15 specify the
sector address. The sector address must be valid during each high-to-low transition of WE
CE

). A0 to A6 specify the byte address within the sector. The bytes may be loaded in any
order; sequential loading is not required. Once a programming operation has been initiated,
and for the duration of t

or WE, whichever occurs last. The data is latched by the first rising edge of

(or CE) within 150 µs of the low-to-high transition of WE (or CE) of the preceding

, a read operation will effectively be a polling operation.

WC

or OE is high. This

(or

2

AT29C512

0456E–FLASH–5/02

AT29C512

SOFTWARE DATA PROTECTION: A software controlled data protection feature is avail-

able on the AT29C512. Once the software protection is enabled a software algorithm must be
issued to the device before a program may be performed. The software protection feature may
be enabled or disabled by the user; when shipped from Atmel, the software data protection
feature is disabled. To enable the software data protection, a series of three program com­mands to specific addresses with specific data must be performed. After the software data
protection is enabled the same three program commands must begin each program cycle in
order for the programs to occur. All software program commands must obey the sector pro­gram timing specifications. Once set, the software data protection feature remains active
unless its disable command is issued. Power transitions will not reset the software data pro­tection feature; however, the software feature will guard against inadvertent program cycles
during power transitions.

Once set, software data protection will remain active unless the disable command sequence is
issued.

After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device; however, for the dura­tion of t

After the software data protection’s 3-byte command code is given, a byte load is performed
by applying a low pulse on the WE
The address is latched on the falling edge of CE
latched by the first rising edge of CE
sector by the same procedure as outlined in the program section under device operation.

, a read operation will effectively be a polling operation.

WC

or CE input with CE or WE low (respectively) and OE high.

or WE, whichever occurs last. The data is

or WE. The 128 bytes of data must be loaded into each

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro­grams to the AT29C512 in the following ways: (a) V
the program function is inhibited; (b) V

power on delay – once VCChas reached the V

CC

sense – if VCCis below 3.8V (typical),

CC

CC

sense level, the device will automatically time out 5 ms (typical) before programming; (c) Pro­gram inhibit – holding any one of OE
Noise filter – pulses of less than 15 ns (typical) on the WE

low, CE high or WE high inhibits program cycles; and (d)

or CE inputs will not initiate a pro-

gram cycle.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product. In addition, users may wish to use the software product identi­fication mode to identify the part (i.e., using the device code), and have the system software
use the appropriate sector size for program operations. In this manner, the user can have a
common board design for 256K to 4-megabit densities and, with each density’s sector size in
a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.

0456E–FLASH–5/02

3

DATA POLLING: The AT29C512 features DATA polling to indicate the end of a program

cycle. During a program cycle an attempted read of the last byte loaded will result in the com­plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA

polling may begin at any time during

the program cycle.

TOGGLE BIT: In addition to DATA
mining the end of a program or erase cycle. During a program or erase operation, successive
attempts to read data from the device will result in I/O6 toggling between one and zero. Once
the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examin­ing the toggle bit may begin at any time during a program cycle.

OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte soft­ware code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages
(including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

CC

+0.6V

polling the AT29C512 provides another method for deter-

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

4

AT29C512

0456E–FLASH–5/02

DC and AC Operating Range

AT29C512

AT29C512-70 AT29C512-90 AT29C512-12 AT29C512-15

Operating
Temperature (Case)

Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%

V

CC

Note:

Not recommended for New Designs.

Com. 0°C-70°C0°C-70°C

Ind. -40°C-85°C

0°C-70°C 0°C-70°C

-40°C-85°C -40°C-85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

5V Chip Erase V

Standby/Write Inhibit V

IL

V

IL

IL

IH

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

Product Identification

Hardware V

Software

(5)

IL

Notes: 1. X can be VILor VIH.

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1F, Device Code: 5D.

5. See details under Software Product Identification Entry/Exit.

V

IL

V

IH

V

IH

(1)

X

IL

IH

V

IL

V

IH

V

IL

V

IL

Ai D

Ai D

Ai

OUT

IN

XXHighZ

IH

X

XHighZ

V

IH

A1 - A15 = VIL,A9=VH,

A1-A15 = VIL,A9=VH,

A0 = V

A0 = V

(3)

A0 = VILManufacturer Code

(3)

A0 = V

IL

IH

Device Code

IH

Manufacturer Code

Device Code

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

0456E–FLASH–5/02

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

CC

Com. 100 µA

10 µA

10 µA

Ind. 300 µA

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

OUT

CC

= 0 mA 50 mA

3mA

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output High Voltage IOH=-400µA2.4V

Output High Voltage CMOS IOH=-100µA; VCC=4.5V 4.2 V

5

AC Read Characteristics

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

(1)

(2)

(3)(4)

Address to Output Delay 70 90 120 150 ns

CE to Output Delay 70 90 120 150 ns

OE to Output Delay 0 35 0 40 0 50 0 70 ns

CE or OE to Output Float 0 10 0 25 0 30 0 40 ns

Output Hold from OE,CEor
Address, whichever
occurred first

Note:

Not recommended for New Designs.

AC Read Waveforms

(1)(2)(3)(4)

AT29C512-70 AT29C512-90

00

AT29C512-12 AT29C512-15

Min Max Min Max

0 0 ns

UnitsMin Max Min Max

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE whichever occurs first (CL = 5 pF).

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

ACC-tCE

after the address transition without impact on t

ACC

.

ACC-tOE

after an address change

6

AT29C512

0456E–FLASH–5/02