Rainbow Electronics AT29C256 User Manual

Features

• Fast Read Access Time – 70 ns

• 5-volt Only Reprogramming

• Page Program Operation

– Single Cycle Reprogram (Erase and Program)
– Internal Address and Data Latches for 64 Bytes

• Internal Program Control and Timer

• Hardware and Software Data Protection

• Fast Program Cycle Times

– Page(64Byte)ProgramTime–10ms
– Chip Erase Time– 10 ms

• DATA Polling for End of Program Detection

• Low-power Dissipation

– 50mAActiveCurrent
–300 µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

Description

The AT29C256 is a five-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.

256K (32K x 8)
5-volt Only
Flash Memory

AT29C256

Pin Configurations

Pin Name Function

A0 - A14 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

PLCC and LCC Top View

Note: PLCC package pins 1 and 17 are

DON’T CONNECT.

Chip Enable

Output Enable

Write Enable

A7

432

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

NC

13

I/O0

14151617181920

I/O1

A12WEDC

I/O2

GND

1

DC

VCC

A14

323130

I/O3

I/O4

A13

29
28
27
26
25
24
23
22
21

I/O5

A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6

DIP Top View

WE

A12

I/O0
I/O1
I/O2

GND

TSOP Top View

22

OE

23

A11

24

A9

25

A8

26

A13

27

A14

28

VCC

1

WE

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

A7
A6
A5
A4
A3
A2
A1
A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14

Type 1

28

VCC

27

A14

26

A13

25

A8

24

A9

23

A11

22

OE

21

A10

20

CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

21

A10

20

CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

14

GND

13

I/O2

12

I/O1

11

I/O0

10

A0

9

A1

8

A2

Rev. 0046O–FLASH–06/02

1

Block Diagram

To allow for simple in-system reprogrammability, the AT29C256 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are
loaded into the device and then simultaneously programmed. The contents of the entire
device may be erased by using a six-byte software code (although erasure before pro­gramming is not needed).

During a reprogram cycle, the address locations and 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA
access for a read, program or chip erase can begin.

polling of I/O7. Once the end of a program cycle has been detected a new

Device Operation

READ: The AT29C256 is accessed like a static RAM. When CE and OE are low and

WE

is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE

or OE is high. This dual-line control gives designers flexibility in preventing bus

contention.

BYTE LOAD: A byte load is performed by applying a low pulse on the WE
with CE
edge of CE
CE
software codes for data protection and chip erasure.

or WE low (respectively) and OE high. The address is latched on the falling

or WE, whichever occurs last. The data is latched by the first rising edge of

or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the

or CE input

2

AT29C256

0046O–FLASH–06/02

AT29C256

PROGRAM: Thedeviceisreprogrammedonapagebasis.Ifabyteofdatawithina

page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded during the programming of its page will be indeterminate. Once the
bytes of a page are loaded into the device, they are simultaneously programmed during
the internal programming period. After the first data byte has been loaded into the
device, successive bytes are entered in the same manner. Each new byte to be pro­grammed must have its high-to-low transition on WE
high transition of WE

(or CE) of the preceding byte. If a high-to-low transition is not
detected within 150 µs of the last low-to-high transition, the load period will end and the
internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE
the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has been initiated, and for the
duration of t

, a read operation will effectively be a polling operation.

WC

SOFTWARE DATA PROTECTION: A software controlled data protection feature is
available on the AT29C256. Once the software protection is enabled a software algo­rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com­mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the page program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft­ware feature will guard against inadvertent program cycles during power transitions.

(or CE) within 150 µs of the low-to-

(or CE). A0 to A5 specify

Once set, software data protection will remain active unless the disable command
sequence is issued.

After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; how­ever, for the duration of t

, a read operation will effectively be a polling operation.

WC

After the software data protection’s three-byte command code is given, a byte load is
performed by applying a low pulse on the WE
tively) and OE

high. The address is latched on the falling edge of CE or WE, whichever

occurs last. The data is latched by the first rising edge of CE

or CE input with CE or WE low (respec-

or WE. The 64 bytes of
data must be loaded into each sector by the same procedure as outlined in the program
section under device operation.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
programs to the AT29C256 in the following ways: (a) V
(typical), the program function is inhibited; (b) V
reached the V

sense level, the device will automatically time out 5 ms (typical) before

CC

CC

programming; (c) Program inhibit – holding any one of OE

sense – if VCCis below 3.8V

CC

power on delay – once VCChas

low, CE high or WE high
inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the
WE

or CE inputs will not initiate a program cycle.

0046O–FLASH–06/02

3

PRODUCT IDENTIFICATION: The product identification mode identifies the device

and manufacturer and may be accessed by a hardware operation. For details, see
Operating Modes or Product Identification.

DATA POLLING: The AT29C256 features DATA
gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com­pleted, true data is valid on all outputs and the next cycle may begin. DATA
begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA
determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.

OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a six-byte
software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

CC

+0.6V

polling to indicate the end of a pro-

polling may

polling the AT29C256 provides another method for

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

4

AT29C256

0046O–FLASH–06/02

DC and AC Operating Range

AT29C256

AT29C256-70 AT29C256-90 AT29C256-12 AT29C256-15

Operating
Temperature (Case)

V

Power Supply 5V ± 5% 5V± 10% 5V± 10% 5V± 10%

CC

Note:

Not recommended for New Designs.

Com. 0°C-70°C0°C-70°C0°C-70°C

Ind. -40°C-85°C-40°C-85°C-40°C-85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

5V Chip Erase V

Standby/Write Inhibit V

IL

V

IL

IL

IH

Write Inhibit X X V

Write Inhibit X V

Output Disable X V

High Voltage Chip Erase V

IL

Product Identification

V

Hardware

Software

(5)

IL

Notes: 1. X can be VILor VIH.

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1F, Device Code: DC.

5. See details under Software Product Identification Entry/Exit.

V

IL

V

IH

V

IH

(1)

X

IL

IH

(3)

V

H

V

IL

V

IH

V

IL

V

IL

Ai D

Ai D

Ai

OUT

IN

XXHighZ

IH

X

XHighZ

V

IL

V

IH

A1-A14 = VIL,A9=VH,A0=VILManufacturer Code

XHighZ

A1-A14 = VIL,A9=VH,A0=VIHDevice Code

A0 = V

A0 = V

IL

IH

Manufacturer Code

Device Code

0°C-70°C

-40°C-85°C

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

0046O–FLASH–06/02

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

CC

= 0 mA 50 mA

OUT

CC

10 µA

10 µA

300 µA

3mA

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output High Voltage IOH=-400µA 2.4 V

Output High Voltage CMOS IOH=-100µA;VCC=4.5V 4.2 V

5

AC Read Characteristics

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

Note:

(1)

(2)

(3)(4)

Address to Output Delay 70 90 120 150 ns

CE to Output Delay 70 90 120 150 ns

OE to Output Delay 0 40 0 40 0 50 0 70 ns

CE or OE to Output Float 0 25 0 25 0 30 0 40 ns

Output Hold from OE,CEor Address,
whichever occurred first

Not recommended for New Designs.

AC Read Waveforms

(1)(2)(3)(4)

AT29C256-70 AT29C256-90 AT29C256-12

AT29C256-15

Min Max

0000 ns

UnitsMin Max Min Max Min Max

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE whichever occurs first (CL = 5 pF).

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

6

AT29C256

ACC-tCE

after the address transition without impact on t

ACC

.

ACC-tOE

after an address change

0046O–FLASH–06/02