Rainbow Electronics AT29C1024 User Manual

Features

•

Fast Read Access Time - 70 ns

•

5-Volt Only Reprogramming

•

Sector Program Operation

– Single Cycle Reprogram (Erase and Program) – 512 Sectors (128 words/sector) – Internal Address and Data Latches for 128 Words

•

Internal Program Control and Timer

•

Hardware and Software Data Protection

•

Fast Sector Program Cycle Time - 10 ms

•

DAT A Polling for End of Program Detection

•

Low Power Dissipation

– 60 mA Active Current – 200 µA CMOS Standby Current

•

Typical Endurance > 10,000 Cycles

•

Single 5V ± 10% Supply

•

CMOS and TTL Compatible Inputs and Outputs

•

Commercial and Industrial Temperature Ranges

Description

The AT29C102 4 is a 5-vol t-only in -system Flash pr ogrammab le and eras able rea d only memory (PERO M). It s 1 megabit of memory is or g ani ze d a s 6 5,5 36 words by 1 6 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power di ssipation of ju st 330 mW. When the device is deselected, the CMO S standby current is less than 200 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times.

(continued)

Pin Configurations

1-Megabit (64K x 16) 5-volt Only Flash Memory

AT29C1024

Pin Name Function

A0 - A15 Addresses CE OE WE

Chip Enable Output Enable

Write Enable I/O0 - I/O15 Data Inputs/Outputs NC No Connect DC Don’t Connect

PLCC Top View

I/O13

I/O14

I/O12 I/O11 I/O10

I/O9 I/O8

GND

NC I/O7 I/O6 I/O5 I/O4

I/O15CENCNCVCCWENC

65432

7 8 9 10 11 12 13 14 15 16 17

1819202122232425262728

I/O3

I/O2

I/O1

I/O0

A15

4443424140

A0A1A2A3A4

A14

39 38 37 36 35 34 33 32 31 30 29

A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5

VSS

A10 A11

NC A12 A13 A14 A15

VCC

TSOP Top View

Type 1

1 2

8 9

12 13

14 15 16 17 18 19 20 21 22 23 24

VSS

O10

O11

O12

O13

O14

O15

Rev. 0571A–10/98

To allow for simple in-system reprogrammability, the AT29C1024 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device . Rea ding d ata out of the de vic e is s imilar to reading from an EPROM. Reprogramming the AT29C1024 is performed on a sector basis; 128 word s of data are loaded into the device and then simultaneou sly programmed.

Block Diagram

During a reprogr am cycle, the address locations and 128 words of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then progra m the l atched dat a usin g an in terna l control timer. The end of a program cycle can be detected by DATA gram cycle has been detected, a new access for a read or program can begin.

polling of I/O7 or I/O15. Once the end of a pro-

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE control gives designers flexibility in preventing bus contention.

DATA LOAD:

words of a sector to be p rogramm ed or the s oftware codes for data protection. A data load is performed by applying a low pulse on the WE (respectively) and OE falling edge of CE is latched by the first rising edge of CE

PROGRAM:

basis. If a word of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any word that is not loaded during the programming of its sector will be erased to read FFH. Once the words of a sector are loaded into the device, they ar e simu ltaneously programmed during the internal programming period. After the first data word has been loaded into the device, successive words are entered in the same manner. Each new word to be programmed must have i ts hig h to low tra nsiti on on WE (or CE) within 150 µs of the low to high transition of WE (or CE detected within 150 µs of the last low to high transition, the

The AT29C1024 is accessed like an EP ROM. and OE are low and WE is high, the data stored

or OE is high. This dual-line

Data loads are used to enter the 128

or CE input with CE or WE low

high. The address is latched on the

or WE, whichever occurs last. The data

or WE.

The device is reprogrammed on a sector

) of the preceding word. If a high to low transition is not

load period will end and the internal programming period will start. A7 to A1 5 specify the sector address . The sector address must be val id durin g each hig h to low trans ition of

(or CE). A0 to A6 specify the word addr ess within the

WE sector. The words may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, an d for the du ration o f t will effectively be a polling operation.

SOFTWARE DATA PROTECTION:

trolled data protection feature is available on the AT29C1024. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to speci fic addresses with specific data must be performed. A fter the software d ata protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software progra m co mm ands must ob ey the se ctor program timing specifications. Once set, software data protection will remain active unless th e disable comman d sequence is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions.

, a read operation

A software con-

AT29C1024

After setting SDP, any attempt to write to the device without the 3-word command sequence will start the internal write timers. No data will be writt en to t he dev ice; h owever, f or the duration of t

, a read operation will effectively be a

polling operation. After the software data prot ection’s 3-wor d command code

is given, a sector of data is loaded into the device using the sector programming timing specifications.

HARDWARE DATA PROTE CTION:

Hardware features protect against inadvertent programs to the AT29C1024 in the following ways: (a) V (typical), the program function is inhibited; (b) V delay—once V

has reached the VCC sense level, the

sense—if VCC is below 3.8V

power on

device will automatic ally tim e ou t 5 ms ( typic al) befo re programming; (c) Program inhibit—holding any one of OE

high or WE high inhibits program cycles ; and (d) Nois e

CE filter—pulses of less than 15 ns (typical) on the WE

low,

or CE

inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addi tion, users may wis h to use the software product identification mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program operations. In this

manner, the user can have a common board design for various Flash densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size.

For details, see O perat ing Mode s (for ha rdware operat ion) or Software Product Identification. The manufacturer and device code is the same for both modes.

POLLING:

DATA

The AT29C1024 features DATA

polling to indicate the end of a program cycle. During a program cycle an attempted read of the last word loaded will result in the complement of the loaded data on I/O7 and I/O15. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

TOGGLE BIT:

In addition to DATA

polling the AT29C1024 provide s anoth er meth od for de termining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 and I/O14 toggling between one and zero. Once the program cycle has completed, I/O6 and I/O14 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a pr ogram cycle.

OPTIONAL CHIP ERASE MODE:

The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................-55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the de vic e. T his is a stres s r ating o nly an d functional opera tion of the device at these or an y other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reli abi li ty.

DC and AC Operating Range

Operating Temperature (Case)

Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C

AT29C1024-70 AT29C1024-90 AT29C1024-12 AT29C1024-15

Power Supply 5 V

5% 5 V ± 10% 5 V ± 10% 5 V

Operating Modes

Mode CE OE WE Ai I/O

Read V Program

(2)

5V Chip Erase V Standby/Write Inhibit V

Program Inhibit X X V Program Inhibit X V Output Disable X V Product Identification

Hardware V

Software

(5)

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 1F, Device Code: 25.

5. See details under Software Product Identification Entry/Exit.

(1)

Ai D Ai D Ai

XXHigh Z

X XHigh Z

A1 - A15 = VIL, A9 = VH,

A0 = V A0 = V

A1 - A15 = VIL, A9 = VH,

(3)

A0 = VILManufacturer Code

(3)

A0 = VIHDevice Code

10%

OUT

(4)

Manufacturer Code Device Code

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

SB1

SB2

ICCV V

OH1

OH2

Input Load Current VIN = 0V to V Output Leakage Current V

= 0V to V

I/O

10 10

Com. 200

VCC Standby Current CMOS CE = V

VCC Standby Current TTL CE = 2.0V to V

Active Current f = 5 MHz; I

- 0.3V to V

OUT

Ind. 200

3mA

= 0 mA 60 mA Input Low Voltage 0.8 V Input High Vo ltage 2.0 V Output Low Voltage IOL = 2.1 mA 0.45 V Output High Voltage IOH = -400 µA2.4V Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

AT29C1024

AC Read Characteristics

Symbol Parameter

t t t t

ACC

(1)

(2)

(3)(4)

Address to Output Delay 70 90 120 150 ns CE to Output Delay 70 90 120 150 ns OE to Output Delay 0 35 0 45 0 60 0 70 ns CE or OE to Output Float 0 25 0 25 0 30 0 40 ns Output Hold from OE, CE or

Address, whichever occurred first

AT29C1024

AT29C1024-70 AT29C1024-90 AT29C1024-12 AT29C1024-15

UnitsMin Max Min Max Min Max Min Max

0000ns

AC Read Waveforms

Notes: 1. CE may be delayed up to t

(1)(2)(3)(4)

ADDRESS

OUTPUT

ACC

2. OE may be delayed up to tCE - tOE after the falling edge of CE with out im pa ct on tCE or by t without impact on t

is specified from OE or CE whichever occurs first (CL = 5 pF).

3. t

ACC

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and Measurement Level

ADDRESS VALID

tCE

tACC

HIGHZ

tOE

tDF

tOH

OUTPUT

VALID

- tCE after the address transition without impact on t

Output Test Load

70 ns 90/120/150 ns

5.0V

ACC

- tOE after an address change

ACC

5.0V

1.8K OUTPUT

tR, tF < 5 ns

1.3K

30p

1.3K

Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Ty p Max Units Conditions

OUT

Note: 1. This parameter is characterized and is not 100% tested.

(1)

46pFV 812pFV

OUT

= 0 V

100p

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