Rainbow Electronics AT29C040A User Manual

Features

• Fast Read Access Time – 90 ns

• 5-volt Only Reprogramming

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 Bytes/Sector)
– Internal Address and Data Latches for 256 Bytes

• Internal Program Control and Timer

• Hardware and Software Data Protection

• Two 16K Bytes Boot Blocks with Lockout

• FastSectorProgramCycleTime–10ms

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 40mAActiveCurrent
– 100 µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

4-megabit
(512K x 8)
5-volt Only
256-byte Sector

Description

The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 90 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt only Flash family.

Pin Configurations

Pin Name Function

A0 - A18 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

Chip Enable

Output Enable

Write Enable

DIP Top View

1

A18

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14

I/O1

15

I/O2

16

GND

VCC

32

WE

31

A17

30

A14

29

A13

28

A8

27

A9

26

A11

25

OE

24

A10

23

CE

22

I/O7

21

I/O6

20

I/O5

19

I/O4

18

I/O3

17

A11

A13
A14
A17

WE

VCC

A18
A16
A15
A12

A9
A8

A7
A6
A5
A4

PLCC Top View

A18

A12

A15

A16

VCCWEA17

432

1

I/O2

GND

I/O3

323130

I/O4

I/O5

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

I/O0

A7
A6
A5
A4
A3
A2
A1
A0

5
6
7
8
9
10
11
12
13

14151617181920

I/O1

TSOP Top View – Type 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

Flash Memory

AT29C040A

Rev. 0333I–FLASH–05/02

1

Block Diagram

To allow for simple in-system reprogrammability, the AT29C040A does not require high input
voltages for programming. Five-volt-only commands determine the operation of the device.
Reading data out of the device is similar to reading from an EPROM. Reprogramming the
AT29C040A is performed on a sector basis; 256 bytes of data are loaded into the device and
then simultaneously programmed.

During a reprogram cycle, the address locations and 256 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and then program the latched data using
an internal control timer. The end of a program cycle can be detected by DATA
Once the end of a program cycle has been detected, a new access for a read or program can
begin.

polling of I/O7.

Device Operation

READ: The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is

high, the data stored at the memory location determined by the address pins is asserted on
the outputs. The outputs are put in the high impedance state whenever CE
dual-line control gives designers flexibility in preventing bus contention.

BYTE LOAD: Byte loads are used to enter the 256 bytes of a sector to be programmed or
the software codes for data protection. A byte load is performed by applying a low pulse on the

or CE input with CE or WE low (respectively) and OE high. The address is latched on the

WE
falling edge of CE
CE

or WE.

PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a sector
is to be changed, data for the entire sector must be loaded into the device. Any byte that is not
loaded during the programming of its sector will be erased to read FFH. Once the bytes of a
sector are loaded into the device, they are simultaneously programmed during the internal
programming period. After the first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to be programmed must have its high
to low transition on WE
preceding byte. If a high to low transition is not detected within 150 µs of the last low to high
transition, the load period will end and the internal programming period will start. A8 to A18
specify the sector address. The sector address must be valid during each high to low transition
of WE
in any order; sequential loading is not required. Once a programming operation has been initi­ated, and for the duration of t

(or CE). A0 to A7 specify the byte address within the sector. The bytes may be loaded

or WE, whichever occurs last. The data is latched by the first rising edge of

(or CE) within 150 µs of the low to high transition of WE (or CE)ofthe

, a read operation will effectively be a polling operation.

WC

or OE is high. This

2

AT29C040A

0333I–FLASH–05/02

AT29C040A

SOFTWARE DATA PROTECTION: A software controlled data protection feature is avail-

able on the AT29C040A. Once the software protection is enabled a software algorithm must
be issued to the device before a program may be performed. The software protection feature
may be enabled or disabled by the user; when shipped from Atmel, the software data protec­tion feature is disabled. To enable the software data protection, a series of three program
commands to specific addresses with specific data must be performed. After the software data
protection is enabled the same three program commands must begin each program cycle in
order for the programs to occur. All software program commands must obey the sector pro­gram timing specifications. The SDP feature protects all sectors, not just a single sector. Once
set, the software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the software fea­ture will guard against inadvertent program cycles during power transitions.

After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; however, for
the duration of t

After the software data protection’s 3-byte command code is given, a byte load is performed
by applying a low pulse on the WE
The address is latched on the falling edge of CE
latched by the first rising edge of CE
sector by the same procedure as outlined in the program section under device operation.

, a read operation will effectively be a polling operation.

WC

or CE input with CE or WE low (respectively) and OE high.

or WE, whichever occurs last. The data is

or WE. The 256 bytes of data must be loaded into each

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro­grams to the AT29C040A in the following ways: (a) V
the program function is inhibited; (b) V

power on delay – once VCChas reached the V

CC

sense – if VCCis below 3.8V (typical),

CC

CC

sense level, the device will automatically time out 5 ms (typical) before programming; (c) Pro­gram inhibit – holding any one of OE
Noise filter – pulses of less than 15 ns (typical) on the WE

low, CE high or WE high inhibits program cycles; and (d)

or CE inputs will not initiate a pro-

gram cycle.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product. In addition, users may wish to use the software product identi­fication mode to identify the part (i.e. using the device code), and have the system software
use the appropriate sector size for program operations. In this manner, the user can have a
common board design for 256K to 4-megabit densities and, with each density’ssectorsizein
a memory map, have the system software apply the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.

DATA

POLLING: The AT29C040A features DATA polling to indicate the end of a program

cycle. During a program cycle an attempted read of the last byte loaded will result in the com­plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA

polling may begin at any time during

the program cycle.

TOGGLE BIT: In addition to DATA

polling the AT29C040A provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc­cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.

0333I–FLASH–05/02

OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte soft­ware code. Please see Software Chip Erase application note for details.

3

BOOT BLOCK PROGRAMMING LOCKOUT: The AT29C040A has two designated memory

blocks that have a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. Each of these blocks consists of 16K
bytes; the programming lockout feature can be set independently for either block. While the
lockout feature does not have to be activated, it can be activated for either or both blocks.

These two 16K memory sections are referred to as
up a system can be contained in a boot block. The AT29C040A blocks are located in the first
16K bytes of memory and the last 16K bytes of memory. The boot block programming lockout
feature can therefore support systems that boot from the lower addresses of memory or the
higher addresses. Once the programming lockout feature has been activated, the data in that
block can no longer be erased or programmed; data in other memory locations can still be
changed through the regular programming methods. To activate the lockout feature, a series
of seven program commands to specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.

If the boot block lockout feature has been activated on either block, the chip erase function will
be disabled.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product Identifi­cation Entry and Exit sections. When the device is in the software product identification mode,
a read from location 00002H will show if programming the lower address boot block is locked
out while reading location 7FFF2H will do so for the upper boot block. If the data is FE, the cor­responding block can be programmed; if the data is FF, the program lockout feature has been
activated and the corresponding block cannot be programmed. The software product identifi­cation exit mode should be used to return to standard operation.

Absolute Maximum Ratings*

Temperature Under Bias ................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

CC

+0.6V

boot blocks

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

. Secure code which will bring

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

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AT29C040A

0333I–FLASH–05/02

DC and AC Operating Range

AT29C040A

AT29C040A-90 AT29C040A-12 AT29C040A-15 AT29C040A-20

Operating
Temperature (Case)

V

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

CC

Note:

Not recommended for New Designs.

Com. 0°C-70°C0°C-70°C0°C-70°C

Ind. -40°C-85°C-40°C-85°C-40°C-85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

Standby/Write Inhibit V

IL

V

IL

IH

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

Product Identification

Hardware V

Software

(5)

IL

Notes: 1. X can be VILor VIH.

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1F, Device Code: A4.

5. See details under Software Product Identification Entry/Exit.

V

IL

V

IH

(1)

X

IL

IH

V

IL

V

IH

V

IL

Ai D

Ai D

OUT

IN

XXHighZ

IH

X

XHighZ

V

IH

A1 - A18 = VIL,A9=VH,

A1 - A18 = VIL,A9=VH,

A0 = V

A0 = V

(3)

A0 = VILManufacturer Code

(3)

A0 = V

IL

IH

Device Code

IH

Manufacturer Code

Device Code

0°C-70°C

-40°C-85°C

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

0333I–FLASH–05/02

Input Load Current VIN=0VtoV

Output Leakage Current V

=0VtoV

I/O

CC

CC

VCCStandby Current CMOS CE =VCC-0.3VtoV

CC

Com. 100 µA

10 µA

10 µA

Ind. 300 µA

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

OUT

CC

= 0 mA 40 mA

3mA

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output High Voltage IOH=-400µA 2.4 V

Output High Voltage CMOS IOH=-100µA;VCC=4.5V 4.2 V

5

AC Read Characteristics

Symbol Parameter

t

t

t

t

t

ACC

CE

OE

DF

OH

(1)

(2)

(3)(4)

Address to Output Delay 90 120 150 200 ns

CE to Output Delay 90 120 150 200 ns

OE to Output Delay 0 40 0 50 0 70 0 80 ns

CE or OE to Output Float 0 25 0 30 0 40 0 50 ns

Output Hold from OE,CEor
Address, whichever occurred first

Note:

Not recommended for New Designs.

AC Read Waveforms

(1)(2)(3)(4)

AT29C040A-90 AT29C040A-12 AT29C040A-15

AT29C040A-20

Min Max

0000 ns

UnitsMin Max Min Max Min Max

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE whichever occurs first (CL = 5 pF).

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

ACC-tCE

after the address transition without impact on t

ACC

.

ACC-tOE

after an address change

6

AT29C040A

0333I–FLASH–05/02