Rainbow Electronics AT29C010A User Manual

Features

• Fast Read Access Time – 70 ns

• 5-volt Only Reprogramming

• Sector Program Operation

– Single Cycle Reprogram (Erase and Program)
– 1024 Sectors (128 Bytes/sector)
– Internal Address and Data Latches for 128 Bytes

• Two 8K Bytes Boot Blocks with Lockout

• Internal Program Control and Timer

• Hardware and Software Data Protection

• Fast Sector Program Cycle Time – 10 ms

• DATA Polling for End of Program Detection

• Low Power Dissipation

– 50mAActiveCurrent
– 100 µA CMOS Standby Current

• Typical Endurance > 10,000 Cycles

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• Commercial and Industrial Temperature Ranges

1-Megabit
(128K x 8)
5-volt Only
Flash Memory

Description

The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 70 ns with power dissipation of just 275 mW over the commer­cial temperature range. When the device is deselected, the CMOS standby current is

Pin Configurations

Pin Name Function

A0 - A16 Addresses

CE

OE

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

A11

A9

A8
A13
A14

NC

WE

VCC

NC
A16
A15
A12

A7
A6
A5
A4

Chip Enable

Output Enable

Write Enable

TSOP Top View

Type 1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

OE

32

A10

31

CE

30

I/O7

29

I/O6

28

I/O5

27

I/O4

26

I/O3

25

GND

24

I/O2

23

I/O1

22

I/O0

21

A0

20

A1

19

A2

18

A3

17

DIP Top View

1

NC

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14

I/O1

15

I/O2

16

GND

PLCC Top View

A12

A15

A16NCVCCWENC

432

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

I/O0

14151617181920

I/O1

I/O2

GND

1

I/O3

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

323130

I/O4

I/O5

VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

29
28
27
26
25
24
23
22
21

I/O6

A14
A13
A8
A9
A11
OE
A10
CE
I/O7

AT29C010A

Rev. 0394D–FLASH–05/02

1

Block Diagram

less than 100 µA. The device endurance is such that any sector can typically be written
to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C010A does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from an EPROM. Repro­gramming the AT29C010A is performed on a sector basis; 128 bytes of data are loaded
into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the sector and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA
access for a read or program can begin.

polling of I/O7. Once the end of a program cycle has been detected, a new

Device Operation

READ: The AT29C010A is accessed like an EPROM. When CE and OE are low and

WE

is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.

BYTE LOAD: Byte loads are used to enter the 128 bytes of a sector to be programmed
or the software codes for data protection. A byte load is performed by applying a low
pulse on the WE
address is latched on the falling edge of CE
latched by the first rising edge of CE

PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a
sector is to be changed, data for the entire sector must be loaded into the device. The
data in any byte that is not loaded during the programming of its sector will be indetermi­nate. Once the bytes of a sector are loaded into the device, they are simultaneously
programmed during the internal programming period. After the first data byte has been
loaded into the device, successive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition on WE
of the low to high transition of WE
tion is not detected within 150 µs of the last low to high transition, the load period will
end and the internal programming period will start. A7 to A16 specify the sector address.

or CE input with CE or WE low (respectively) and OE high. The

or WE, whichever occurs last. The data is

or WE.

(or CE)within150µs

(or CE) of the preceding byte. If a high to low transi-

2

AT29C010A

0394D–FLASH–05/02

AT29C010A

The sector address must be valid during each high to low transition of WE (or CE). A0 to
A6 specify the byte address within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming operation has been initiated,
and for the duration of t

SOFTWARE DATA PROTECTION: A software controlled data protection feature is
available on the AT29C010A. Once the software protection is enabled a software algo­rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com­mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the sector program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft­ware feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command
sequence is issued.

After setting SDP, any attempt to write to the device without the 3-byte command
sequence will start the internal write timers. No data will be written to the device; how­ever, for the duration of t

After the software data protection’s 3-byte command code is given, a byte load is per­formed by applying a low pulse on the WE
and OE

high. The address is latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE
be loaded into each sector by the same procedure as outlined in the program section
under device operation.

, a read operation will effectively be a polling operation.

WC

, a read operation will effectively be a polling operation.

WC

or CE input with CE or WE low (respectively)

or WE. The 128 bytes of data must

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro­grams to the AT29C010A in the following ways: (a) V
(typical), the program function is inhibited; (b) V
reached the V

sense level, the device will automatically time out 5 ms (typical) before

CC

CC

programming; (c) Program inhibit – holding any one of OE

sense – if VCCis below 3.8V

CC

power on delay – once VCChas

low, CE high or WE high
inhibits program cycles; and (d) Noise filter—pulses of less than 15 ns (typical) on the
WE

or CE inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e. using the device code), and
have the system software use the appropriate sector size for program operations. In this
manner, the user can have a common board design for 256K to 4-megabit densities
and, with each density’s sector size in a memory map, have the system software apply
the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identifi­cation. The manufacturer and device code is the same for both modes.

DATA

POLLING: The AT29C010A features DATA polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com­pleted, true data is valid on all outputs and the next cycle may begin. DATA

polling may

begin at any time during the program cycle.

0394D–FLASH–05/02

3

TOGGLE BIT: In addition to DATA polling the AT29C010A provides another method

for determining the end of a program or erase cycle. During a program or erase opera­tion, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a pro­gram cycle.

OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte
software code. Please see Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT: The AT29C010A has two designated
memory blocks that have a programming lockout feature. This feature prevents pro­gramming of data in the designated block once the feature has been enabled. Each of
these blocks consists of 8K bytes; the programming lockout feature can be set indepen­dently for either block. While the lockout feature does not have to be activated, it can be
activated for either or both blocks.

These two 8K memory sections are referred to as

boot blocks

. Secure code which will
bring up a system can be contained in a boot block. The AT29C010A blocks are located
in the first 8K bytes of memory and the last 8K bytes of memory. The boot block pro­gramming lockout feature can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the programming lockout feature
has been activated, the data in that block can no longer be erased or programmed; data
in other memory locations can still be changed through the regular programming meth­ods. To activate the lockout feature, a series of seven program commands to specific
addresses with specific data must be performed. Please see Boot Block Lockout Fea­ture Enable Algorithm.

If the boot block lockout feature has been activated on either block, the chip erase func­tion will be disabled.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product
Identification Entry and Exit sections. When the device is in the software product identifi­cation mode, a read from location 00002 will show if programming the lower address
boot block is locked out while reading location 1FFF2 will do so for the upper boot block.
If the data is FE, the corresponding block can be programmed; if the data is FF, the pro­gram lockout feature has been activated and the corresponding block cannot be pro­grammed. The software product identification exit mode should be used to return to
standard operation.

Absolute Maximum Ratings*

Temperature Under Bias ................................ -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

4

AT29C010A

CC

+0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

0394D–FLASH–05/02

DC and AC Operating Range

AT29C010A

AT29C010A-70 AT29C010A-90 AT29C010A-12 AT29C010A-15

Operating
Temperature (Case)

Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10%

V

CC

Note:

Not recommended for New Designs.

Com. 0°C-70°C0°C-70°C0°C-70°C

Ind. -40°C-85°C-40°C-85°C

Operating Modes

Mode CE OE WE Ai I/O

Read V

Program

(2)

5V Chip Erase V

Standby/Write Inhibit V

IL

V

IL

IL

IH

Program Inhibit X X V

Program Inhibit X V

Output Disable X V

Product Identification

Hardware V

Software

(5)

IL

Notes: 1. X can be VILor VIH.

2. Refer to AC Programming Waveforms.

3. V

= 12.0V ± 0.5V.

H

4. Manufacturer Code: 1F, Device Code: 5D.

5. See details under Software Product Identification Entry/Exit.

V

IL

V

IH

V

IH

(1)

X

IL

IH

V

IL

V

IH

V

IL

V

IL

Ai D

Ai D

Ai

OUT

IN

XXHighZ

IH

X

XHighZ

V

IH

A1 - A16 = VIL,A9=VH,

A1 - A16 = VIL,A9=VH,

A0 = V

A0 = V

(3)

A0 = V

(3)

A0 = V

IL

IH

Manufacturer Code

IL

Device Code

IH

Manufacturer Code

Device Code

0°C-70°C

-40°C-85°C

(4)

(4)

(4)

(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB1

I

SB2

I

CC

V

IL

V

IH

V

OL

V

OH1

V

OH2

0394D–FLASH–05/02

Input Load Current VIN=0VtoV

Output Leakage Current V

VCCStandby Current CMOS CE =VCC-0.3VtoV

VCCStandby Current TTL CE =2.0VtoV

VCCActive Current f = 5 MHz; I

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage IOL=2.1mA 0.45 V

Output High Voltage IOH=-400µA 2.4 V

Output High Voltage CMOS IOH=-100µA;VCC=4.5V 4.2 V

=0VtoV

I/O

CC

CC

CC

0° -40°C30µA

Com. 100 µA

Ind. 300 µA

CC

= 0 mA 50 mA

OUT

10 µA

10 µA

3mA

5

AC Read Characteristics

Symbol Parameter

t

ACC

t

CE

t

OE

t

DF

t

OH

(1)

(2)

(3)(4)

Address to Output Delay 70 90 120 150 ns

CE to Output Delay 70 90 120 150 ns

OE to Output Delay 0 35 0 40 0 50 0 70 ns

CE or OE to Output Float 0 25 0 25 0 30 0 40 ns

Output Hold from OE,CEor
Address, whichever occurred first

Note:

Not recommended for New Designs.

AC Read Waveforms

(1)(2)(3)(4)

AT29C010A-70 AT29C010A-90 AT29C010A-12

AT29C010A-15

Min Max

0000 ns

UnitsMin Max Min Max Min Max

Notes: 1. CE may be delayed up to t

2. OE

may be delayed up to tCE-tOEafter the falling edge of CE without impact on tCEor by t

without impact on t

3. t

is specified from OE or CE whichever occurs first (CL = 5 pF).

DF

ACC

.

4. This parameter is characterized and is not 100% tested.

ACC-tCE

after the address transition without impact on t

ACC

.

ACC-tOE

after an address change

6

AT29C010A

0394D–FLASH–05/02