Rainbow Electronics AT28C64X User Manual

Features

• Fast Read Access Time – 120 ns

• Fast Byte Write – 200 µs or 1 ms

• Self-timed Byte Write Cycle

– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write

• Direct Microprocessor Control

– READY/BUSY
– DATA Polling

• Low Power

– 30 mA Active Current
– 100 µA CMOS Standby Current

• High Reliability

– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years

• 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-wide Pinout

• Commercial and Industrial Temperature Ranges

Open Drain Output

64K (8K x 8)
Parallel
EEPROMs

AT28C64

Description

The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile elec­trically erasable and programmable read only memory with popular, easy-to-use fea­tures. The device is manufactured with Atmel’s reliable nonvolatile technology.

(continued)

Pin Configurations

Pin Name Function

A0 - A12 Addresses

CE

OE

WE Write Enable

I/O0 - I/O7 Data Inputs/Outputs

RDY/BUSY

NC No Connect

DC Don’t Connect

OE

A11

A9
A8

NC

WE

RDY/BUSY (or NC)

VCC

A12

A7
A6
A5
A4
A3

Chip Enable

Output Enable

Ready/Busy Output

TSOP

Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14

RDY/BUSY (or NC)

28

A10

27

CE

26

I/O7

25

I/O6

24

I/O5

23

I/O4

22

I/O3

21

GND

20

I/O2

19

I/O1

18

I/O0

17

A0

16

A1

15

A2

Note: PLCC package pins 1 and 17 are
DON’T CONNECT.

I/O0

A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

NC

13

PDIP, SOIC

Top V ie w

1
2
3
4
5
6
7
8
9
10
11
12
13
14

LCC, PLCC

Top V ie w

A7

A12

RDY/BUSY (or NC)

DC

VCCWENC

432

1

323130

14151617181920

DC

I/O1

I/O2

I/O3

VSS

28
27
26
25
24
23
22
21
20
19
18
17
16
15

I/O4

29
28
27
26
25
24
23
22
21

I/O5

VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6

AT28C64X

Rev. 0001H–12/99

1

The AT28C64 is accessed like a Static RAM for the read or
write cycles without the need for external components. Dur­ing a byte write, the address and data are latched inter­nally, freeing the microprocessor address and data bus for
other operations. Following the initiation of a write cycle,
the device will go to a busy state and automatically clear
and write the latched data using an internal control timer.
The device includes two methods for detecting the end of a
write cycle, level detection of RDY/BUSY
N.C.) and DATA

Polling of I/O7. Once the end of a write

(unless pin 1 is

Block Diagram

cycle has been detected, a new access for a read or write
can begin.

The CMOS technology offers fast access times of 120 ns at
low power dissipation. When the chip is deselected the
standby current is less than 100 µA.

Atmel’s AT28C64 has additional features to ensure high
quality and manufacturability. The device utilizes error cor­rection internally for extended endurance and for improved
data retention characteristics. An extra 32 bytes of
EEPROM are available for device identification or tracking.

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

and A9

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

2

AT28C64(X)

Device Operation

READ: The AT28C64 is accessed like a Static RAM.

When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high
impedance state whenever CE
control gives designers increased flexibility in preventing
bus contention.

BYTE WRITE: Writing data into the AT28C64 is similar to
writing into a Static RAM. A low pulse on the WE
input with OE high and CE or WE low (respectively) ini­tiates a byte write. The address location is latched on the
falling edge of WE
rising edge. Internally, the device performs a self-clear
before write. Once a byte write has been started, it will
automatically time itself to completion. Once a program­ming operation has been initiated and for the duration of
t

WC

FAST BYTE WRITE: The AT28C64E offers a byte write
time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.

READY/BUSY

that can be used to detect the end of a write cycle.
RDY/BUSY
is released at the completion of the write. The open drain
connection allows for OR-tying of several devices to the

and OE are low and WE is high, the data stored

or OE is high. This dual line

or CE

(or CE); the new data is latched on the

, a read operation will effectively be a polling operation.

: Pin 1 is an open drain RDY/BUSY output

is actively pulled low during the write cycle and

AT28C64(X)

same RDY/BUSY
nected for the AT28C64X.

DATA

POLLING: The AT28C64 provides DATA Polling to

signal the completion of a write cycle. During a write cycle,
an attempted read of the data being written results in the
complement of that data for I/O
indeterminate). When the write cycle is finished, true data
appears on all outputs.

WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) V
if V

is below 3.8V (typical) the write function is inhibited;

CC

(b) V

power on delay – once VCC has reached 3.8V the

CC

device will automatically time out 5 ms (typical) before
allowing a byte write; and (c) write inhibit – holding any one

low, CE high or WE high inhibits byte write cycles.

of OE

CHIP CLEAR: The contents of the entire memory of the
AT28C64 may be set to the high state by the CHIP CLEAR
operation. By setting CE
cleared when a 10 msec low pulse is applied to WE

DEVICE IDENTIFICATION: An extra 32 bytes of
EEPROM memory are available to the user for device iden­tification. By raising A9 to 12 ± 0.5V and using address
locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.

line. The RDY/BUSY pin is not con-

(the other outputs are

7

sense –

CC

low and OE to 12 volts, the chip is

.

3

DC and AC Operating Range

AT28C64-12 AT28C64-15 AT28C64-20 AT28C64-25

Operating
Temperature (Case)

V

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

CC

Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C

Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C

Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write

Standby/Write Inhibit V

IL

V

IL

IH

Write Inhibit X X V

Write Inhibit X V

Output Disable X V

Chip Erase V

IL

V

V

IL

V

IH

(1)

X

IL

IH

(3)

H

V

IH

V

IL

D

OUT

D

X High Z

IH

X

X High Z

V

IL

High Z

IN

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms.

= 12.0V ± 0.5V.

3. V

H

DC Characteristics

Symbol Parameter Condition Min Max Units

I

I

I

I

LI

LO

SB1

SB2

Input Load Current VIN = 0V to VCC + 1V 10 µA

Output Leakage Current V

VCC Standby Current CMOS CE = V

= 0V to V

I/O

CC

CC

10 µA

- 0.3V to VCC + 1.0V 100 µA

Com. 2 mA

VCC Standby Current TTL CE = 2.0V to VCC + 1.0V

Ind. 3 mA

I

CC

V

IL

V

IH

V

OL

V

OH

4

V

Active Current AC

CC

Input Low Voltage 0.8 V

Input High Voltage 2.0 V

Output Low Voltage

Output High Voltage IOH = -400 µA 2.4 V

AT28C64(X)

f = 5 MHz; I
CE

= V

IL

= 2.1 mA

I

OL

= 4.0 mA for RDY/BUSY

OUT

= 0 mA

Com. 30 mA

Ind. 45 mA

0.45 V