Features
• Fast Read Access Time – 120 ns
• Fast Byte Write – 200 µs or 1 ms
• Self-timed Byte Write Cycle
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
• Direct Microprocessor Control
– READY/BUSY
– DATA Polling
• Low Power
– 30 mA Active Current
– 100 µA CMOS Standby Current
• High Reliability
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
• 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-wide Pinout
• Commercial and Industrial Temperature Ranges
Open Drain Output
64K (8K x 8)
Parallel
EEPROMs
AT28C64
Description
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile electrically erasable and programmable read only memory with popular, easy-to-use features. The device is manufactured with Atmel’s reliable nonvolatile technology.
(continued)
Pin Configurations
Pin Name Function
A0 - A12 Addresses
CE
OE
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
RDY/BUSY
NC No Connect
DC Don’t Connect
OE
A11
A9
A8
NC
WE
RDY/BUSY (or NC)
VCC
A12
A7
A6
A5
A4
A3
Chip Enable
Output Enable
Ready/Busy Output
TSOP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RDY/BUSY (or NC)
28
A10
27
CE
26
I/O7
25
I/O6
24
I/O5
23
I/O4
22
I/O3
21
GND
20
I/O2
19
I/O1
18
I/O0
17
A0
16
A1
15
A2
Note: PLCC package pins 1 and 17 are
DON’T CONNECT.
I/O0
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
NC
13
PDIP, SOIC
Top V ie w
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LCC, PLCC
Top V ie w
A7
A12
RDY/BUSY (or NC)
DC
VCCWENC
432
1
323130
14151617181920
DC
I/O1
I/O2
I/O3
VSS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
I/O4
29
28
27
26
25
24
23
22
21
I/O5
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
AT28C64X
Rev. 0001H–12/99
1
The AT28C64 is accessed like a Static RAM for the read or
write cycles without the need for external components. During a byte write, the address and data are latched internally, freeing the microprocessor address and data bus for
other operations. Following the initiation of a write cycle,
the device will go to a busy state and automatically clear
and write the latched data using an internal control timer.
The device includes two methods for detecting the end of a
write cycle, level detection of RDY/BUSY
N.C.) and DATA
Polling of I/O7. Once the end of a write
(unless pin 1 is
Block Diagram
cycle has been detected, a new access for a read or write
can begin.
The CMOS technology offers fast access times of 120 ns at
low power dissipation. When the chip is deselected the
standby current is less than 100 µA.
Atmel’s AT28C64 has additional features to ensure high
quality and manufacturability. The device utilizes error correction internally for extended endurance and for improved
data retention characteristics. An extra 32 bytes of
EEPROM are available for device identification or tracking.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to V
Voltage on OE
with Respect to Ground...................................-0.6V to +13.5V
and A9
+ 0.6V
CC
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
2
AT28C64(X)
Device Operation
READ: The AT28C64 is accessed like a Static RAM.
When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high
impedance state whenever CE
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C64 is similar to
writing into a Static RAM. A low pulse on the WE
input with OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the
falling edge of WE
rising edge. Internally, the device performs a self-clear
before write. Once a byte write has been started, it will
automatically time itself to completion. Once a programming operation has been initiated and for the duration of
t
WC
FAST BYTE WRITE: The AT28C64E offers a byte write
time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
READY/BUSY
that can be used to detect the end of a write cycle.
RDY/BUSY
is released at the completion of the write. The open drain
connection allows for OR-tying of several devices to the
and OE are low and WE is high, the data stored
or OE is high. This dual line
or CE
(or CE); the new data is latched on the
, a read operation will effectively be a polling operation.
: Pin 1 is an open drain RDY/BUSY output
is actively pulled low during the write cycle and
AT28C64(X)
same RDY/BUSY
nected for the AT28C64X.
DATA
POLLING: The AT28C64 provides DATA Polling to
signal the completion of a write cycle. During a write cycle,
an attempted read of the data being written results in the
complement of that data for I/O
indeterminate). When the write cycle is finished, true data
appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) V
if V
is below 3.8V (typical) the write function is inhibited;
CC
(b) V
power on delay – once VCC has reached 3.8V the
CC
device will automatically time out 5 ms (typical) before
allowing a byte write; and (c) write inhibit – holding any one
low, CE high or WE high inhibits byte write cycles.
of OE
CHIP CLEAR: The contents of the entire memory of the
AT28C64 may be set to the high state by the CHIP CLEAR
operation. By setting CE
cleared when a 10 msec low pulse is applied to WE
DEVICE IDENTIFICATION: An extra 32 bytes of
EEPROM memory are available to the user for device identification. By raising A9 to 12 ± 0.5V and using address
locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
line. The RDY/BUSY pin is not con-
(the other outputs are
7
sense –
CC
low and OE to 12 volts, the chip is
.
3
DC and AC Operating Range
AT28C64-12 AT28C64-15 AT28C64-20 AT28C64-25
Operating
Temperature (Case)
V
Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
CC
Com. 0°C - 70°C0°C - 70°C0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C-40°C - 85°C-40°C - 85°C
Operating Modes
Mode CE OE WE I/O
Read V
(2)
Write
Standby/Write Inhibit V
IL
V
IL
IH
Write Inhibit X X V
Write Inhibit X V
Output Disable X V
Chip Erase V
IL
V
V
IL
V
IH
(1)
X
IL
IH
(3)
H
V
IH
V
IL
D
OUT
D
X High Z
IH
X
X High Z
V
IL
High Z
IN
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
= 12.0V ± 0.5V.
3. V
H
DC Characteristics
Symbol Parameter Condition Min Max Units
I
I
I
I
LI
LO
SB1
SB2
Input Load Current VIN = 0V to VCC + 1V 10 µA
Output Leakage Current V
VCC Standby Current CMOS CE = V
= 0V to V
I/O
CC
CC
10 µA
- 0.3V to VCC + 1.0V 100 µA
Com. 2 mA
VCC Standby Current TTL CE = 2.0V to VCC + 1.0V
Ind. 3 mA
I
CC
V
IL
V
IH
V
OL
V
OH
4
V
Active Current AC
CC
Input Low Voltage 0.8 V
Input High Voltage 2.0 V
Output Low Voltage
Output High Voltage IOH = -400 µA 2.4 V
AT28C64(X)
f = 5 MHz; I
CE
= V
IL
= 2.1 mA
I
OL
= 4.0 mA for RDY/BUSY
OUT
= 0 mA
Com. 30 mA
Ind. 45 mA
0.45 V
AC Read Characteristics
tR, tF < 20 ns
Symbol Parameter
AT28C64(X)
AT28C64-12 AT28C64-15 AT28C64-20 AT28C64-25
UnitsMin Max Min Max Min Max Min Max
t
t
t
t
t
ACC
CE
OE
DF
OH
(1)
(2)
(3)(4)
Address to Output Delay 120 150 200 250 ns
CE to Output Delay 120 150 200 250 ns
OE to Output Delay 10601070108010100ns
CE or OE High to Output Float 045050055060ns
Output Hold from OE, CE or
Address, whichever occurred first
AC Read Waveforms
0000ns
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by t
without impact on t
ACC
.
- tCE after the address transition without impact on t
ACC
ACC
.
- tOE after an address change
ACC
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Output Test Load
Measurement Level
Pin Capacitance
f = 1 MHz, T = 25°C
Symbol Typ Max Units Conditions
C
IN
C
OUT
Note: 1. This parameter is characterized and is not 100% tested.
(1)
46pFV
812pFV
IN
OUT
= 0V
= 0V
5
AC Write Characteristics
Symbol Parameter Min Max Units
t
, t
AS
OES
t
AH
t
WP
t
DS
t
, t
DH
OEH
t
, t
CS
CH
t
DB
Address, OE Setup Time 10 ns
Address Hold Time 50 ns
Write Pulse Width (WE or CE) 100 1000 ns
Data Setup Time 50 ns
Data, OE Hold Time 10 ns
CE to WE and WE to CE Setup and Hold Time 0 ns
Time to Device Busy 50 ns
AT 2 8C 6 4 1 ms
t
WC
Write Cycle Time (option available)
AT28C64E 200 µs
AC Write Waveforms
WE Controlled
CE Controlled
6
AT28C64(X)
AT28C64(X)
Data Polling Characteristics
Symbol Parameter Min Typ Max Units
t
DH
t
OEH
t
OE
t
WR
Notes: 1. These parameters are characterized and not 100% tested.
Data Hold Time 10 ns
OE Hold Time 10 ns
OE to Output Delay
Write Recovery Time 0 ns
2. See “AC Read Characteristics”.
(2)
(1)
Data Polling Waveforms
ns
Chip Erase Waveforms
tS = tH = 1 µsec (min.)
t
= 10 msec (min.)
W
VH = 12.0 ± 0.5V
7
8
AT28C64(X)
AT28C64 Ordering Information
I
t
ACC
(ns)
120 30 0.1 AT28C64(E)-12JC
150 30 0.1 AT28C64(E)-15JC
200 30 0.1 AT28C64(E)-20JC
250 30 0.1 AT28C64(E)-25JC
(mA)
CC
Ordering Code Package Operation RangeActive Standby
AT28C64(E)-12PC
AT28C64(E)-12SC
AT28C64(E)-12TC
45 0.1 AT28C64(E)-12JI
AT28C64(E)-12PI
AT28C64(E)-12SI
AT28C64(E)-12TI
AT28C64(E)-15PC
AT28C64(E)-15SC
AT28C64(E)-15TC
45 0.1 AT28C64(E)-15JI
AT28C64(E)-15PI
AT28C64(E)-15SI
AT28C64(E)-15TI
AT28C64(E)-20PC
AT28C64(E)-20SC
AT28C64(E)-20TC
45 0.1 AT28C64(E)-20JI
AT28C64(E)-20PI
AT28C64(E)-20SI
AT28C64(E)-20TI
AT28C64(E)-25PC
AT28C64(E)-25SC
AT28C64(E)-25TC
45 0.1 AT28C64(E)-25JI
AT28C64(E)-25PI
AT28C64(E)-25SI
AT28C64(E)-25TI
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
AT28C64(X)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6 28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28S 28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 1 ms
E High Endurance Option: Endurance = 100K Write Cycles; Write Time = 200 µs
9
AT28C64X Ordering Information
I
t
ACC
(ns)
150 30 0.1 AT28C64X-15JC
200 30 0.1 AT28C64X-20JC
250 30 0.1 AT28C64X-25JC
(mA)
CC
Ordering Code Package Operation RangeActive Standby
AT28C64X-15PC
AT28C64X-15SC
AT28C64X-15TC
45 0.1 AT28C64X-15JI
AT28C64X-15PI
AT28C64X-15SI
AT28C64X-15TI
AT28C64X-20PC
AT28C64X-20SC
AT28C64X-20TC
45 0.1 AT28C64X-20JI
AT28C64X-20PI
AT28C64X-20SI
AT28C64X-20TI
AT28C64X-25PC
AT28C64X-25SC
AT28C64X-25TC
45 0.1 AT28C64X-25JI
AT28C64X-25PI
AT28C64X-25SI
AT28C64X-25TI
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
32J
28P6
28S
28T
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers Speed Package and Temperature Combinations
AT28C64 X 12 JC, JI, PC, PI, SC, SI, TC, TI
AT28C64 X 15 JC, JI, PC, PI, SC, SI, TC, TI
AT28C64 X 20 JC, JI, PC, PI, SC, SI, TC, TI
AT28C64 X 25 JC, JI, PC, PI, SC, SI, TC, TI
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6 28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28S 28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28T 28-lead, Plastic Thin Small Outline Package (TSOP)
10
AT28C64(X)
Packaging Information
AT28C64(X)
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45˚
.032(.813)
.026(.660)
.050(1.27) TYP
PIN NO. 1
IDENTIFY
.553(14.0)
.547(13.9)
.300(7.62) REF
.430(10.9)
.390(9.90)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
.025(.635) X 30˚ - 45˚
.595(15.1)
.585(14.9)
AT CONTACT
POINTS
.022(.559) X 45˚ MAX (3X)
.012(.305)
.008(.203)
.021(.533)
.013(.330)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.530(13.5)
.490(12.4)
28P6, 28-lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
1.47(37.3)
.220(5.59)
SEATING
PLANE
.161(4.09)
.125(3.18)
MAX
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
1.44(36.6)
1.300(33.02) REF
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
.690(17.5)
.610(15.5)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
.005(.127)
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
0
REF
15
MAX
MIN
28S, 28-lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
28T, 28-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
0.55 (0.022)
BSC
0
REF
5
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
0.20 (0.008)
0.10 (0.004)
0.70 (0.028)
0.30 (0.012)
11.9 (0.469)
11.7 (0.461)
0.27 (0.011)
0.18 (0.007)
13.7 (0.539)
13.1 (0.516)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.15 (0.006)
*Controlling dimension: millimeters
11
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.
®
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Terms and product names in this document may be trademarks of others.
and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Printed on recycled paper.
0001H–12/99/xM
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