Rainbow Electronics AT28C0101 User Manual

Features

•

Fast Read Access Time - 120 ns

•

Automatic Page Write Operation

Internal Address and Data Latches for 128-Bytes Internal Control Timer

•

Fast Write Cycle Time

Page Write Cycle Time - 10 ms Maximum 1 to 128-Byte Page Write Operation

•

Low Power Dissipation

80 mA Active Current 300 µA CMOS Standby Current

•

Hardware and Software Data Protection

•

DAT A Polling for End of Write Detection

•

High Reliability CMOS Technology

Endurance: 104 or 105 Cycles Data Retention: 10 Years

•

Single 5V ± 10% Supply

•

CMOS and TTL Compatible Inputs and Outputs

•

JEDEC Approved Byte-Wide Pinout

Description

The AT28C010 i s a high -perf ormanc e E lectr ica lly E rasab le a nd P rog rammab le R ea d Only Memory. Its one meg abit of memory is orga nized as 131,072 wor ds by 8 bits. Manufactured with A tmel ’s a dvanc ed no nv ola til e CMO S technology, the device offe rs access times to 120 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 300 µA.

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AT28C010 Mil

1-Megabit (128K x 8) Paged Parallel EEPROMs

AT28C010 Military

Pin Configuration

Pin Name Function

A0 - A16 Addresses CE Chip Enable OE Outp ut Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect

CERDIP, FLATPACK

Top View

NC A16 A15 A12

I/O0 I/O1 I/O2

GND

1 2 3 4 5

13 14 15 16

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

A12

44 LCC

Top View

A15

A16NCNCNCNC

65432

7 8

1819202122232425262728

I/O0

I/O1

I/O2

VCCWENCNCA14

4443424140

I/O3

VSS

I/O4

I/O5

I/O6

39 38 37 36 35 34 33 32 31 30 29

I/O7

A13 A8 A9 A11 NC NC NC NC OE A10 CE

I/O0

32 LCC

Top View

A12

A15

A16NCVCCWENC

432

323130

14151617181920

I/O1

I/O2

I/O3

I/O4

I/O5

GND

PGA

Top View

29 28 27 26 25 24 23 22 21

I/O6

A14 A13 A8 A9 A11 OE A10 CE I/O7

Rev. 0010C–10/98

The AT28C010 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contai ns a 128- byte pa ge r egist er to a llow writing of up to 128-bytes simultane ous ly . Durin g a write c ycle , the address and 1 to 128-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by

Block Diagram

POLLING of I/O7. Once the end of a write cy cle has

DATA been detected a new access for a read or write can begin.

Atmel's 28C010 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 128-bytes of EEPROM for device identification or tracking.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

and A9

+ 0.6V

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This i s a stress rating o nl y and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f or e xtended p eriods ma y aff ect de vice reliability.

AT28C010 Mil

Device Operation

READ:

When CE at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE line control gives designers flexibility in preventing bus contention in their system.

BYTE WRITE:

or WE low (respec tive ly ) and OE high initiates a write cycle. The address is latched on the fallin g edge of CE whichever occurs last. The data is latched by the first rising edge of CE will automatically time itself to completion. Once a programming operation has been in itiate d and for the du ratio n of t tion.

PAGE WRITE:

allows 1 to 128-bytes o f data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followe d by 1 t o 127 add itional bytes. Each successive byte must be written within 150 µs (t exceeded the AT28C010 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the s tate of the A7 - A16 inputs. For each WE tion, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes wi thin the page are to be written. The bytes may be lo ade d in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

DATA

indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA cycle.

TOGGLE BIT:

provides another m etho d for determining th e end of a wr it e cycle. During the write operation, successive attempts to read data from th e device will resul t in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop togglin g and v alid dat a will be read. Re ading th e toggle bit may begin at any time during the write cycle.

DATA PROTECTION:

vertent writes may oc cur during transitio ns of the hos t sys-

The AT28C010 is accessed like a Static RAM.

and OE are low and WE is high, the data stored

or OE is high. This dual-

A low pulse on the W E

or CE input with CE

or WE,

or WE. Once a byte write has been started it

, a read operation will effectively be a polling opera-

The page write operatio n of the AT28C01 0

) of the previous byte. If the t

BLC

limit is

high to low transition during the page write opera-

POLLING:

The AT28C010 features DATA

Polling to

Polling may begin at an ytim e d uring the wr ite

In addition to DATA

Polling the AT28C010

If precautions are not taken, inad-

AT28C010 Mil

tem power supply. Atmel has incorp orated both har dware and software features that will protect the memory against inadvertent writes.

HARDWARE PROTECTION:

against inadvertent writes to the AT28C010 in the following ways: (a) V

sense - if VCC is below 3.8V (typical) the write

function is inhibited; (b) V reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE

low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE

or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION:

data protection feat ure has been impleme nted on the AT28C010. When enabl ed, the software da ta protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C010 is shipped from Atmel with SDP disabled.

SDP is enabled by the host system issuing a series of three write commands; th ree specifi c bytes of dat a are writ ten to three specific addre sses ( refer to S oftware Da ta Pro tectio n Algorithm). After writing the 3-byte command sequence and after t

the entire AT28C010 will be protected against

inadvertent write operations. It should be noted, that once protected the hos t may still perfor m a byte or page writ e to the AT28C010. This is done by preceding the data to be written by the same 3-byte command sequence used to enable SDP.

Once set, SDP will remain activ e unless the disable c ommand sequence is i ssued. Power transitions d o no t di sabl e SDP and SDP will protect the AT28C010 during power-up and power-down conditions . A ll comman d s eque nc es must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in eit her a by te or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be writt en to the de vice; h owever , for the duration of t

, read operations will effectively be poll-

ing operations.

DEVICE IDENTIFICATI ON:

EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the regular memory array.

OPTIONAL CHIP ERASE MODE:

be erased using a 6-byte software code. Please see Software Chip Erase application note for details.

Hardware features protect

power-on delay - once VCC has

A software controlled

An extra 128-bytes of

The entire device can

DC and AC Operating Range

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

Operating Temperature (Case)

Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C

Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write Standby/Write Inhibit V

Write Inhibit X X V Write Inhibit X V Output Disable X V

V V

(1)

X High Z

X X High Z

OUT

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms

DC Characteristics

Symbol Parameter Condition Min Max Units

SB1

SB2

OH1

OH2

Input Load Current VIN = 0V to VCC + 1V 10 µA Output Leakage Current V

= 0V to V

I/O

10 µA VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 300 µA VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA VCC Active Current f = 5 MHz; I

= 0 mA 80 mA

OUT

Input Low Voltage 0.8 V Input High Voltage 2.0 V Output Low Voltage IOL = 2.1 mA 0.45 V Output High Voltage IOH = -400 µA2.4V Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4,2 V

AT28C010 Mil

AC Read Characteristics

Symbol Parameter

ACC

(1)

(2)

tOE

(3, 4)

AC Read Waveforms

Address to Output Delay 120 150 200 250 ns CE to Output Delay 120 150 200 250 ns OE to Output Delay 050055055055ns CE or OE to Output Float 050055055055ns Output Hold from OE, CE or

Address, whichever occurred first

(1)(2)(3)(4)

AT28C010 Mil

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

UnitsMin Max Min Max Min Max Min Max

0000ns

Notes: 1. CE may be delayed up to t

2. OE may be delayed up to tCE - tOE after the falling edge of CE with out im pa ct on tCE or by t without impact in t

ACC

- tCE after the address transition without impact on t

ACC

- tOE after an address change

ACC

3. tDF is specified from OE or CE wichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

Input Test Waveforms and

Output Test Load

Measurement Level

Pin Capacitance

f = 1 MHz, T = 25°C

Symbol Ty p Max Units Conditions

OUT

Note: 1. This parameter is 100% characterized and is not 100% tested.

(1)

410pFV 812pFV

OUT

= 0V

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