Rainbow Electronics AT28BV64B User Manual

Features

5
6
7
8
9
10
11
12
13

29
28
27
26
25
24
23
22
21

A6
A5
A4
A3
A2
A1
A0

NC

I/O0

A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6

432

1

323130

14151617181920

I/O1

I/O2

GND

DC

I/O3

I/O4

I/O5

A7

A12NCDC

VCCWENC

• Single 2.7V to 3.6V Supply

• Hardware and Software Data Protection

• Low Power Dissipation

– 15 mA Active Current
–20 µA CMOS Standby Current

• Fast Read Access Time - 200 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer

• Fast Write Cycle Time s

– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation

• DATA Polling for End of Write Detection

• High-reliability CMOS Technology

– Endurance: 100,000 Cycles
– Data Retention: 10 Years

• JEDEC Approved Byte-wide Pinout

• Commercial and Industrial Temperature Ranges

Description

The AT28BV64B is a hi gh-pe rforman ce ele ctri cally e rasa ble progr ammab le re ad only
memory (EEPROM). Its 64 K o f memory is organized as 8 ,192 wor ds by 8 bi ts . Ma nu­factured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power di ssipation of j ust 54 mW. When the device is
deselected, the CMOS standby current is less than 20 µA.

(continued)

64K (8K x 8)

Battery-Voltage

™

Parallel EEPROM
with Page Write
and Software
Data Protection

AT28BV64B

Pin Configurations

Pin Name Function

A0 - A12 Addresses
CE
OE
WE
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect

Note: PLCC packag e pins 1 and 17

Chip Enable
Output En able
Write Enable

PLCC

Top View

are DON’T CONNECT.

A11

WE

VCC

A12

PDIP, SOIC

Top View

1

A12

I/O0
I/O1
I/O2

GND

NC

A7
A6
A5
A4
A3
A2
A1
A0

28
2
3
4
5
6
7
8
9
10
11
12
13
14

VCC

27

WE

26

NC

25

A8

24

A9

23

A11

22

OE

21

A10

20

CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

3-Volt, 64K

2

E

PROM with

Data Protection

TSOP

Top View

1

OE

2
3

A9

4

A8

5

NC

6
7
8

NC

9
10

A7

11

A6

12

A5

13

A4

14

A3

28

A10

27

CE

26

I/O7

25

I/O6

24

I/O5

23

I/O4

22

I/O3

21

GND

20

I/O2

19

I/O1

18

I/O0

17

A0

16

A1

15

A2

Rev. 0299F–05/28/99

1

The AT28BV64B is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 64 byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 byte s of dat a are inte rnall y latch ed,
freeing the addre ss and data bus f or o ther ope ratio ns. Fo l­lowing the initiation of a write cycle, the device will automat­ically write the latched data using an internal control timer.
The end of a write cycle can be detected by DATA

polling of

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

All Input Voltages
(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

+ 0.6V

CC

I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.

Atmel’s AT28BV6 4B ha s add iti ona l f eatu re s to ens ure hig h
quality and manufacturability. A software data protection
mechanism guards against inadvertent writes. The device
also includes an extra 64 bytes o f EEPROM for device
identification or tracking.

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operati on of th e devi ce at th ese o r any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

2

and A9

AT28BV64B

Device Operation

READ: The AT28BV64B is accessed like a static RAM.

When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE
line control gives designers flexibility in preventing bus con­tention in their systems.

BYTE WRITE: A low puls e on the WE
or WE low (respec tive ly ) and OE high initiates a write cycle.
The address is latched on the fallin g edge of CE
whichever occurs last. The data is latched by the first rising
edge of CE
will automatically time itself to completion. Once a pro­gramming operation has been in itiate d and for the du ratio n
of t
tion.

PAGE WRITE: The page write operation of the
AT28BV64B allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write oper ation is in itiated in the same ma nner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 100 µs (t

exceeded, the AT28BV64B will cease acce pting data an d
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 to A12 inputs . For
each WE
tion, A6 to A12 must be the same.

The A0 to A5 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.

DATA

to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA
cycle.

TOGGLE BIT: In addition to DATA
provides another m etho d for determining th e end of a wr it e
cycle. During the write operation, successive attempts to

and OE are low and WE is high, the data stored

or OE is high. This dual-

or CE input with CE

or WE,

or WE. Once a byte write ha s been st arted, it

, a read operation will effectively be a polling opera-

WC

) of the previous byte. If the t

BLC

BLC

limit is

high to low transition during the page write opera-

POLLING: The AT28BV64B featur es DATA Polling

Polling may begin at anytime during the write

Polling, the AT28BV64B

AT28BV64B

read data from the d evice will result i n I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop togglin g and v alid data will be read. R eading th e
toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inad­vertent writes may oc cur during transiti ons of the ho st sys­tem power supply. Atmel has incorp orated both har dware
and software features that will protect the memory against
inadvertent writes.

HARDWARE PROTECTION: Hardware features protect
against inadvert ent writ es to the AT2 8BV64 B in the foll ow­ing ways: (a) V

1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write; (b) write inhibitholding
any one of OE
cycles; and ( c) no ise filt erpulses of less than 15 ns (typi­cal) on the WE

S O FTW A RE D A TA P RO T ECTI ON: A soft ware-controlled
data protection feat ure has been impleme nted on the
AT28BV64B. Software data protection (SDP) helps prevent
inadvertent writes from corrupting the data in the device.
SDP can prevent inadvertent writes during power-up and
power-down as well as any other potential periods of sys­tem instability.

The AT28BV 64B can only be written us ing the soft ware
data protection feature

to specific ad dress es with sp ecif ic data mus t be p resen ted
to the device before writing in the byte or page mode. The
same three write commands must begin each write opera­tion. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command se quence is not writ ten to the device; th e
addresses in the command sequence can be utilized just
like any other location in the device.

Any attempt to write to the device without the 3-byte
sequence will sta rt th e i nte rn al writ e timers. No data will be
written to the device; ho wever, for th e durat ion of t
operations will effectively be polling operations.

DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for devi ce identificatio n.
By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH, the additional bytes may be written to or
read from in the same manner as the regular memory
array.

power-on delay—once VCC has reached

CC

low, CE high or WE high inhibits write

or CE inputs will not initiate a write cycle.

. A series of three write commands

, read

WC

3

DC and AC Operating Range

AT28BV64B-20 AT28BV64B-25

Operating
Temperature (Case)

V

Power Supply 2.7V to 3.6V 2.7V to 3.6V

CC

Com. 0°C - 70°C0°C - 70°C
Ind. -40°C - 85°C-40°C - 85°C

Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write
Standby/Write Inhibit V

IL

V

IL

IH

Write Inhibit X X V
Write Inhibit X V
Output Disable X V
Chip Erase V

IL

V

IL

V

IH

(1)

X

IL

IH

(3)

V

H

V

IH

V

IL

D

OUT

D

X High Z

IH

X
X High Z

V

IL

High Z

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.
= 12.0V ± 0.5V.

3. V

H

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB

I

CC

V

IL

V

IH

V

OL

V

OH

Input Load Current VIN = 0V to VCC + 1V 10 µA

Output Leakage Current V

VCC Standby Current CMOS

V

Active Current f = 5 MHz; I

CC

= 0V to V

I/O

= V

CE

+ 1V

V

CC

- 0.3V to

CC

OUT

CC

10 µA
Com. 20 µA
Ind. 50 µA

= 0 mA 15 mA
Input Low Voltage 0.6 V
Input High Voltage 2.0 V
Output Low Voltage IOL = 1.6 mA 0.45 V
Output High Voltage IOH = -100 µA 2.0 V

IN

4

AT28BV64B