Rainbow Electronics AT28BV256 User Manual

Features

5
6
7
8
9
10
11
12
13

29
28
27
26
25
24
23
22
21

A6
A5
A4
A3
A2
A1
A0

NC

I/O0

A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6

432

1

323130

14151617181920

I/O1

I/O2

GND

DC

I/O3

I/O4

I/O5

A7

A12

A14DCVCCWEA13

• Single 2.7V - 3.6V Supply

• Fast Read Access Time – 200 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer

• Fast Write Cycle Times

– Page Write Cycle Time: 10 ms Maximum
– 1- to 64-byte Page Write Operation

• Low Power Dissipation

– 15 mA Active Current
– 20 µA CMOS Standby Current

• Hardware and Software Data Protection

• DATA Polling for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 10,000 Cycles
– Data Retention: 10 Years

• JEDEC Approved Byte-wide Pinout

• Commercial and Industrial Temperature Ranges

256K (32K x 8)

Battery-Voltage

Parallel
EEPROMs

™

Description

The AT28BV256 is a high-performance Electrically Erasable and Programmable Read
Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac­tured with Atmel’s advanced nonvolatile CMOS technology, the device offers access
times to 200 ns with power dissipation of just 54 mW. When the device is deselected,

OE

A11

A13

WE

VCC

A14
A12

µA.

A9
A8

A7
A6
A5
A4
A3

(continued)

PDIP, SOIC

Top V ie w

1

A14

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11

I/O0

12

I/O1

13

I/O2

14

GND

TSOP

Top V ie w

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28

VCC

27

WE

26

A13

25

A8

24

A9

23

A11

22

OE

21

A10

20

CE

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

I/O3

28

A10

27

CE

26

I/O7

25

I/O6

24

I/O5

23

I/O4

22

I/O3

21

GND

20

I/O2

19

I/O1

18

I/O0

17

A0

16

A1

15

A2

the CMOS standby current is less than 200

Pin Configurations

Pin Name Function

A0 - A14 Addresses

CE

OE Output Enable

WE

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

DC Don’t Connect

Note: PLCC package pins 1 and 17
are DON’T CONNECT.

Chip Enable

Write Enable

PLCC

Top View

AT28BV256

Rev. 0273G–11/99

1

The AT28BV256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 bytes of data are internally latched,
freeing the address and data bus for other operations. Fol­lowing the initiation of a write cycle, the device will automat­ically write the latched data using an internal control timer.
The end of a write cycle can be detected by DATA

polling

Block Diagram

of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.

Atmel’s 28BV256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protec­tion mechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.

Absolute Maximum Ratings*

Temperature under Bias ................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

and A9

+ 0.6V

CC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability

2

AT28BV256

Device Operation

READ: The AT28BV256 is accessed like a Static RAM.

When CE
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE
line control gives designers flexibility in preventing bus con­tention in their system.

BYTE WRITE: A low pulse on the WE
CE
cycle. The address is latched on the falling edge of CE
WE
rising edge of CE
started it will automatically time itself to completion. Once a
programming operation has been initiated and for the dura­tion of t
operation.

PAGE WRITE: The page write operation of the
AT28BV256 allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 150
exceeded the AT28BV256 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 - A14 inputs. For
each WE
tion, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnec­essary cycling of other bytes within the page does not
occur.

DATA

to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA
cycle.

TOGGLE BIT: In addition to DATA
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to

and OE are low and WE is high, the data stored

or OE is high. This dual-

or CE input with

or WE low (respectively) and OE high initiates a write

or

, whichever occurs last. The data is latched by the first

or WE. Once a byte write has been

, a read operation will effectively be a polling

WC

µs (t

) of the previous byte. If the t

BLC

BLC

limit is

high to low transition during the page write opera-

POLLING: The AT28BV256 features DATA Polling

Polling may begin at anytime during the write

Polling the AT28BV256

AT28BV256

read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inad­vertent writes may occur during transitions of the host sys­tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.

HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28BV256 in the follow­ing ways: (a) V

1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write; (b) write inhibit—holding
any one of OE
cycles; and (c) noise filter—pulses of less than 15 ns (typi­cal) on the WE

SOFTWARE DATA PROTECTION: A software-controlled
data protection feature has been implemented on the
AT28BV256. Software data protection (SDP) helps prevent
inadvertent writes from corrupting the data in the device.
SDP can prevent inadvertent writes during power-up and
power-down as well as any other potential periods of sys­tem instability.

The AT28BV256 can only be written using the software
data protection feature. A series of three write commands
to specific addresses with specific data must be presented
to the device before writing in the byte or page mode. The
same three write commands must begin each write opera­tion. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command sequence is not written to the device; the
address in the command sequence can be utilized just like
any other location in the device.

Any attempt to write to the device without the 3-byte
sequence will start the internal write timers. No data will be
written to the device; however, for the duration of t
operations will effectively be polling operations.

DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V
7FC0H to 7FFFH the additional bytes may be written to or
read from in the same manner as the regular memory
array.

power-on delay—once VCC has reached

CC

low, CE high or WE high inhibits write

or CE inputs will not initiate a write cycle.

, read

WC

± 0.5V and using address locations

3

DC and AC Operating Range

AT28BV256-20 AT28BV256-25

Operating
Temperature (Case)

V

Power Supply 2.7V - 3.6V 2.7V - 3.6V

CC

Com. 0°C - 70°C0°C - 70°C

Ind. -40°C - 85°C-40°C - 85°C

Operating Modes

Mode CE OE WE I/O

Read V

(2)

Write

Standby/Write Inhibit V

IL

V

IL

IH

Write Inhibit X X V

Write Inhibit X V

Output Disable X V

Chip Erase V

IL

V

IL

V

IH

(1)

X

IL

IH

(3)

V

H

V

IH

V

IL

D

OUT

D

IN

XHigh Z

IH

X

XHigh Z

V

IL

High Z

Notes: 1. X can be VIL or VIH.

2. Refer to AC programming waveforms.

= 12.0V ± 0.5V.

3. V

H

DC Characteristics

Symbol Parameter Condition Min Max Units

I

LI

I

LO

I

SB

I

CC

V

IL

V

IH

V

OL

V

OH

Input Load Current VIN = 0V to VCC + 1V 10 µA

Output Leakage Current V

= 0V to V

I/O

CC

10 µA

Com. 20 µA

VCC Standby Current CMOS CE = V

V

Active Current f = 5 MHz; I

CC

- 0.3V to VCC + 1V

CC

= 0 mA 15 mA

OUT

Ind. 50 µA

Input Low Voltage 0.6 V

Input High Voltage 2.0 V

Output Low Voltage IOL = 1.6 mA 0.3 V

Output High Voltage IOH = -100 µA2.0V

4

AT28BV256