Rainbow Electronics AT26DF081A User Manual

Features

• Single 2.7V - 3.6V Supply

• Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3

• 70 MHz Maximum Clock Frequency

• Flexible, Uniform Erase Architecture

– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase

• Individual Sector Protection with Global Protect/Unprotect Feature

– One 32-Kbyte Top Boot Sector
– Two 8-Kbyte Sectors
– One 16-Kbyte Sector
– Fifteen 64-Kbyte Sectors

• Hardware Controlled Locking of Protected Sectors

• Flexible Programming Options

– Byte/Page Program (1 to 256 Bytes)
– Sequential Program Mode Capability

• Automatic Checking and Reporting of Erase/Program Failures

• JEDEC Standard Manufacturer and Device ID Read Methodology

• Low Power Dissipation

– 5 mA Active Read Current (Typical)
– 25 µA Deep Power-down Current (Typical)

• Endurance: 100,000 Program/Erase Cycles

• Data Retention: 20 Years

• Complies with Full Industrial Temperature Range

• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (150-mil and 200-mil wide)

8-megabit

2.7-volt
Minimum
SPI Serial Flash
Memory

AT26DF081A

1. Description

The AT26DF081A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer-based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT26DF081A, with its eras\e granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT26DF081A have been opti­mized to meet the needs of today’s code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi­tional code routines and data storage segments to be added while still maintaining the
same overall device density.

3600H–DFLASH–11/2012

The AT26DF081A also offers a sophisticated method for protecting individual sectors against
erroneous or malicious program and erase operations. By providing the ability to individually pro­tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while
keeping the remaining sectors of the memory array securely protected. This is useful in applica­tions where program code is patched or updated on a subroutine or module basis, or in
applications where data storage segments need to be modified without running the risk of errant
modifications to the program code segments. In addition to individual sector protection capabili­ties, the AT26DF081A incorporates Global Protect and Global Unprotect features that allow the
entire memory array to be either protected or unprotected all at once. This reduces overhead
during the manufacturing process since sectors do not have to be unprotected one-by-one prior
to initial programming.

Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and
erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for
programming and erasing.

2

AT26DF081A

3600H–DFLASH–11/2012

2. Pin Descriptions and Pinouts

Table 2-1. Pin Descriptions

Symbol Name and Function

CS

SCK

SI

CHIP SELECT: Asserting the
device will be deselected and normally be placed in standby mode (not Deep Power-down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.

A high-to-low transition on the
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.

SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.

CS pin selects the device. When the CS pin is deasserted, the

CS pin is required to start an operation, and a low-to-high transition

AT26DF081A

Asserted

State Type

Low Input

Input

Input

SO

WP

HOLD

V

CC

GND

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.

WRITE PROTECT: The
section “Protection Commands and Features” on page 15 for more details on protection features
and the

The
not be used. However, it is recommended that the
whenever possible.

HOLD: The
resetting the device. While the
SI pin will be ignored, and the SO pin will be in a high-impedance state.

The
condition to start. A Hold condition pauses serial communication only and does not have an effect
on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold”

on page 30 for additional details on the Hold operation.

The
However, it is recommended that the
possible.

DEVICE POWER SUPPLY: The VCCpin is used to supply the source voltage to the device.
Operations at invalid V

GROUND: The ground reference for the power supply. GND should be connected to the
system ground.

WP pin.

WP pin is internally pulled-high and may be left floating if hardware-controlled protection will

HOLD pin is used to temporarily pause serial communication without deselecting or

CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold

HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.

WP pin controls the hardware locking feature of the device. Please refer to

WP pin also be externally connected to V

HOLD pin is asserted, transitions on the SCK pin and data on the

HOLD pin also be externally connected to VCCwhenever

voltages may produce spurious results and should not be attempted.

CC

CC

Output

Low Input

Low Input

Power

Power

3600H–DFLASH–11/2012

3

3. Block Diagram

Figure 2-1. 8-SOIC Top View

1

CS
SO

WP

GND

2
3
4

8
7
6
5

VCC
HOLD
SCK
SI

CS

SCK

SI

INTERFACE

CONTROL

SO

WP

4. Memory Array

CONTROL AND

PROTECTION LOGIC

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

AND

LOGIC

Y-DECODER

Y-GATING

FLASH

MEMORY

X-DECODER

ARRAY

ADDRESS LATCH

To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys­ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break­down of each physical sector.

4

AT26DF081A

3600H–DFLASH–11/2012

Figure 4-1. Memory Architecture Diagram

r

AT26DF081A

Block Erase Detail Page Program Detail

Internal Sectoring fo

Sector Protection Block Erase Block Erase Block Erase Page Program

Function (D8h Command) (52h Command) (20h Command) (02h Command)

32KB

(Sector 18)

8KB

(Sector 17)

8KB

(Sector 16)

16KB

(Sector 15)

64KB

(Sector 14)

• •

•

64KB

(Sector 0)

64KB 32KB 4KB 1-256 Byte

Range

0FFFFFh – 0FF000h 256 Bytes 0FFFFFh – 0FFF00h

0FEFFFh – 0FE000h 256 Bytes 0FFEFFh – 0FFE00h
0FDFFFh – 0FD000h 256 Bytes 0FFDFFh – 0FFD00h
0FCFFFh – 0FC000h 256 Bytes 0FFCFFh – 0FFC00h
0FBFFFh – 0FB000h 256 Bytes 0FFBFFh – 0FFB00h
0FAFFFh – 0FA000h 256 Bytes 0FFAFFh – 0FFA00h

0F9FFFh – 0F9000h 256 Bytes 0FF9FFh – 0FF900h

0F8FFFh – 0F8000h 256 Bytes 0FF8FFh – 0FF800h

0F7FFFh – 0F7000h 256 Bytes 0FF7FFh – 0FF700h

0F6FFFh – 0F6000h 256 Bytes 0FF6FFh – 0FF600h

0F5FFFh – 0F5000h 256 Bytes 0FF5FFh – 0FF500h

0F4FFFh – 0F4000h 256 Bytes 0FF4FFh – 0FF400h

0F3FFFh – 0F3000h 256 Bytes 0FF3FFh – 0FF300h

0F2FFFh – 0F2000h 256 Bytes 0FF2FFh – 0FF200h

0F1FFFh – 0F1000h 256 Bytes 0FF1FFh – 0FF100h

0F0FFFh – 0F0000h 256 Bytes 0FF0FFh – 0FF000h
0EFFFFh – 0EF000h 256 Bytes 0FEFFFh – 0FEF00h
0EEFFFh – 0EE000h 256 Bytes 0FEEFFh – 0FEE00h
0EDFFFh – 0ED000h 256 Bytes 0FEDFFh – 0FED00h
0ECFFFh – 0EC000h 256 Bytes 0FECFFh – 0FEC00h
0EBFFFh – 0EB000h 256 Bytes 0FEBFFh – 0FEB00h
0EAFFFh – 0EA000h 256 Bytes 0FEAFFh – 0FEA00h

0E9FFFh – 0E9000h 256 Bytes 0FE9FFh – 0FE900h

0E8FFFh – 0E8000h 256 Bytes 0FE8FFh – 0FE800h

0E7FFFh – 0E7000h

0E6FFFh – 0E6000h

0E5FFFh – 0E5000h

0E4FFFh – 0E4000h 256 Bytes 0017FFh – 001700h

0E3FFFh – 0E3000h 256 Bytes 0016FFh – 001600h

0E2FFFh – 0E2000h 256 Bytes 0015FFh – 001500h

0E1FFFh – 0E1000h 256 Bytes 0014FFh – 001400h

0E0FFFh – 0E0000h 256 Bytes 0013FFh – 001300h

00FFFFh – 00F000h 256 Bytes 000FFFh – 000F00h

00EFFFh – 00E000h 256 Bytes 000EFFh – 000E00h
00DFFFh – 00D000h 256 Bytes 000DFFh – 000D00h
00CFFFh – 00C000h 256 Bytes 000CFFh – 000C00h

00BFFFh – 00B000h 256 Bytes 000BFFh – 000B00h

00AFFFh – 00A000h 256 Bytes 000AFFh – 000A00h

009FFFh – 009000h 256 Bytes 0009FFh – 000900h
008FFFh – 008000h 256 Bytes 0008FFh – 000800h
007FFFh – 007000h 256 Bytes 0007FFh – 000700h
006FFFh – 006000h 256 Bytes 0006FFh – 000600h
005FFFh – 005000h 256 Bytes 0005FFh – 000500h
004FFFh – 004000h 256 Bytes 0004FFh – 000400h
003FFFh – 003000h 256 Bytes 0003FFh – 000300h
002FFFh – 002000h 256 Bytes 0002FFh – 000200h
001FFFh – 001000h 256 Bytes 0001FFh – 000100h
000FFFh – 000000h 256 Bytes 0000FFh – 000000h

•

• •

256 Bytes 0012FFh – 001200h
256 Bytes 0011FFh – 001100h
256 Bytes 0010FFh – 001000h

64KB

64KB

64KB

4KB
4KB
4KB

32KB

32KB

32KB

32KB

• • •

32KB

32KB

• •

•

4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB

4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB

•

• •

Page AddressBlock Address

Range

3600H–DFLASH–11/2012

5

5. Device Operation

The AT26DF081A is controlled by a set of instructions that are sent from a host controller, com­monly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via
the SPI bus which is comprised of four signal lines: Chip Select (
Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT26DF081A supports the two most common modes, SPI
modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.

Figure 5-1. SPI Mode 0 and 3

CS

SCK

CS), Serial Clock (SCK), Serial

SI

SO

MSBLSB

6. Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus.
Following the opcode, instruction dependent information such as address and data bytes would
then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with
the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT26DF081A will be ignored by the device and no operation will
be started. The device will continue to ignore any data presented on the SI pin until the start of
the next operation (CS pin being deasserted and then reasserted). In addition, if the CSpinis
deasserted before complete opcode and address information is sent to the device, then no oper­ation will be performed and the device will simply return to the idle state and wait for the next
operation.

Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23 - A0. Since the upper address limit of the AT26DF081A memory array is
0FFFFFh, address bits A23 - A20 are always ignored by the device.

MSB

LSB

6

AT26DF081A

3600H–DFLASH–11/2012

AT26DF081A

Table 6-1. Command Listing

Command Opcode Address Bytes Dummy Bytes Data Bytes

Read Commands

Read Array 0Bh 0000 1011 3 1 1+

Read Array (Low Frequency) 03h 0000 0011 3 0 1+

Program and Erase Commands

Block Erase (4 Kbytes) 20h 0010 0000 3 0 0

Block Erase (32 Kbytes) 52h 0101 0010 3 0 0

Block Erase (64 Kbytes) D8h 1101 1000 3 0 0

Chip Erase

Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 3 0 1+

Sequential Program Mode

Protection Commands

Write Enable 06h 0000 0110 0 0 0

Write Disable 04h 0000 0100 0 0 0

Protect Sector 36h 0011 0110 3 0 0

Unprotect Sector 39h 0011 1001 3 0 0

Global Protect/Unprotect Use Write Status Register command

Read Sector Protection Registers 3Ch 0011 1100 3 0 1+

Status Register Commands

Read Status Register 05h 0000 0101 0 0 1+

Write Status Register 01h 0000 0001 0 0 1

Miscellaneous Commands

Read Manufacturer and Device ID 9Fh 1001 1111 0 0 1 to 4

Deep Power-down B9h 1011 1001 0 0 0

60h 0110 0000 0 0 0

C7h 1100 0111 0 0 0

ADh 1010 1101 3, 0

AFh 1010 1111 3, 0

(1)

(1)

01

01

Resume from Deep Power-down ABh 1010 1011 0 0 0

Note: 1. Three address bytes are only required for the first operation to designate the address to start programming at. Afterwards,

the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require
clocking in of the opcode and the data byte until the Sequential Program Mode has been exited.

3600H–DFLASH–11/2012

7

7. Read Commands

7.1 Read Array

The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the SCK signal once the initial starting address has been speci­fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.

Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode
depends on the maximum SCK frequency that will be used to read data from the device. The
0Bh opcode can be used at any SCK frequency up to the maximum specified by f
opcode can be used for lower frequency read operations up to the maximum specified by f

To perform the Read Array operation, the
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. If the 0Bh opcode is used, then one don't care byte must also be
clocked in after the three address bytes.

After the three address bytes (and the one don't care byte if using opcode 0Bh) have been
clocked in, additional clock cycles will result in serial data being output on the SO pin. The data
is always output with the MSB of a byte first. When the last byte (0FFFFFh) of the memory array
has been read, the device will continue reading back at the beginning of the array (000000h).
No delays will be incurred when wrapping around from the end of the array to the beginning
of the array.

.The03h

SCK

RDLF

CS pin must first be asserted and the appropriate

.

Deasserting the
ance state. The CS pin can be deasserted at any time and does not require that a full byte
of data be read.

Figure 7-1. Read Array – 0Bh Opcode

CS

SCK

SI

SO

2 310

OPCODE

00001011

MSB MSB

HIGH-IMPEDANCE

CS pin will terminate the read operation and put the SO pin into a high-imped-

6754101198 12 39 42 43414037 3833 36353431 3229304447484645

ADDRESS BITS A23-A0 DON'T CARE

AAAA AAAA A

XXXXXXXX

MSB

DATA BYTE 1

DDDDDDDDDD

MSBMSB

8

AT26DF081A

3600H–DFLASH–11/2012

Figure 7-2. Read Array – 03h Opcode

CS

AT26DF081A

SCK

SO

2 310

OPCODE

SI

00000011

MSB MSB

HIGH-IMPEDANCE

6754101198 12 37 3833 36353431 322930 39 40

8. Program and Erase Commands

8.1 Byte/Page Program

The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of
data to be programmed into previously erased memory locations. An erased memory location is
one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page
Program command can be started, the Write Enable command must have been previously
issued to the device (see “Write Enable” on page 15 command description) to set the Write
Enable Latch (WEL) bit of the Status Register to a logical “1” state.

To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device
followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the
device and will be stored in an internal buffer.

ADDRESS BITS A23-A0

AAAA AAAA A

DATA BYTE 1

DDDDDDDDDD

MSBMSB

If the starting memory address denoted by A23 - A0 does not fall on an even 256-byte page
boundary (A7 - A0 are not all 0’s), then special circumstances regarding which memory locations
will be programmed will apply. In this situation, any data that is sent to the device that goes
beyond the end of the page will wrap around back to the beginning of the same page. For exam­ple, if the starting address denoted by A23 - A0 is 0000FEh, and three bytes of data are sent to
the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining
bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change.
In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes
sent will be latched into the internal buffer.

When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro­gram it into the appropriate memory array locations based on the starting address specified by
A23 - A0 and the number of data bytes sent to the device. If less than 256 bytes of data were
sent to the device, then the remaining bytes within the page will not be altered. The program­ming of the data bytes is internally self-timed and should take place in a time of tPP.

The three address bytes and at least one complete byte of data must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries
(multiples of eight bits); otherwise, the device will abort the operation and no data will be pro­grammed into the memory array. In addition, if the address specified by A23 - A0 points to a
memory location within a sector that is in the protected state (see section “Protect Sector” on

page 16), then the Byte/Page Program command will not be executed, and the device will return

to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be

3600H–DFLASH–11/2012

9

reset back to the logical “0” state if the program cycle aborts due to an incomplete address being
sent, an incomplete byte of data being sent, or because the memory location to be programmed
is protected.

While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tPPtime to determine if the data bytes have finished programming. At
some point before the program cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.

The Byte/Page Program mode is the default programming mode after the device powers-up or
resumes from a device reset.

Figure 8-1. Byte Program

CS

SCK

SI

SO

Figure 8-2. Page Program

CS

SCK

SI

SO

00000010

MSB MSB

HIGH-IMPEDANCE

2 310

OPCODE

00000010

MSB MSB

HIGH-IMPEDANCE

2 310

OPCODE

6754 983937 3833 36353431 322930

ADDRESS BITS A23-A0 DATA IN BYTE 1

AA AAAA

6754101198 12 3937 3833 36353431 322930

ADDRESS BITS A23-A0 DATA IN

AAAA AAAA A

DDDDDDDD

MSB

DDDDDDDD

MSB

DATA IN BYTE n

DDDDDDDD

MSB

10

AT26DF081A

3600H–DFLASH–11/2012

8.2 Sequential Program Mode

The Sequential Program Mode improves throughput over the Byte/Page Program command
when the Byte/Page Program command is used to program single bytes only into consecutive
address locations. For example, some systems may be designed to program only a single byte
of information at a time and cannot utilize a buffered Page Program operation due to design
restrictions. In such a case, the system would normally have to perform multiple Byte Program
operations in order to program data into sequential memory locations. This approach can add
considerable system overhead and SPI bus traffic.

The Sequential Programming Mode helps reduce system overhead and bus traffic by incorporat­ing an internal address counter that keeps track of the byte location to program, thereby
eliminating the need to supply an address sequence to the device for every byte to program.
When using the Sequential Program mode, all address locations to be programmed must be in
the erased state. Before the Sequential Program mode can first be entered, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Reg­ister to a logical “1” state.

AT26DF081A

To start the Sequential Program Mode, the
of ADh or AFh must be clocked into the device. For the first program cycle, three address bytes
must be clocked in after the opcode to designate the first byte location to program. After the
address bytes have been clocked in, the byte of data to be programmed can be sent to the
device. Deasserting the CS pin will start the internally self-timed program operation, and the byte
of data will be programmed into the memory location specified by A23 - A0.

After the first byte has been successfully programmed, a second byte can be programmed by
simply reasserting the CS pin, clocking in the ADh or AFh opcode, and then clocking in the next
byte of data. When the CS pin is deasserted, the second byte of data will be programmed into
the next sequential memory location. The process would be repeated for any additional bytes.
There is no need to reissue the Write Enable command once the Sequential Program Mode has
been entered.

When the last desired byte has been programmed into the memory array, the Sequential
Program Mode operation can be terminated by reasserting the CS pin and sending the
Write Disable command to the device to reset the WEL bit in the Status Register back to the
logical “0” state.

If more than one byte of data is ever clocked in during each program cycle, then only the last
byte of data sent on the SI pin will be stored in the internal latches. The programming of each
byte is internally self-timed and should take place in a time of tBP. For each program cycle, a
complete byte of data must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation, the byte of data will not be programmed into the memory array,
and the WEL bit in the Status Register will be reset back to the logical “0” state.

CS pin must first be asserted, and either an opcode

3600H–DFLASH–11/2012

If the address initially specified by A23 - A0 points to a memory location within a sector that is in
the protected state, then the Sequential Program Mode command will not be executed, and the
device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Sta­tus Register will also be reset back to the logical “0” state.

There is no address wrapping when using the Sequential Program Mode. Therefore, when the
last byte (0FFFFFh) of the memory array has been programmed, the device will automatically
exit the Sequential Program mode and reset the WEL bit in the Status Register back to the logi­cal “0” state. In addition, the Sequential Program mode will not automatically skip over protected

11

sectors; therefore, once the highest unprotected memory location in a programming sequence
has been programmed, the device will automatically exit the Sequential Program mode and
reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0
was currently being programmed, once the last byte of Sector 0 was programmed, the Sequen­tial Program mode would automatically end. To continue programming with Sector 2, the
Sequential Program mode would have to be restarted by supplying the ADh or AFh opcode, the
three address bytes, and the first byte of Sector 2 to program.

While the device is programming a byte, the Status Register can be read and will indicate that
the device is busy. For faster throughput, it is recommended that the Status Register be polled at
the end of each program cycle rather than waiting the tBPtime to determine if the byte has fin­ished programming before starting the next Sequential Program mode cycle.

The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.

Figure 8-3. Sequential Program Mode – Status Register Polling

CS

Seqeuntial Program Mode

Command

Opcode

SI

SO

Note: Each transition shown for SI represents one byte (8 bits)

A23-16 A15-8 A7-0 05hData

First Address to Program

HIGH-IMPEDANCE

Status Register Read

Command

STATUS REGISTER

Seqeuntial Program Mode

Command

Opcode

DATA

Seqeuntial Program Mode

Data 05h 04h

STATUS REGISTER

DATA

Figure 8-4. Sequential Program Mode – Waiting Maximum Byte Program Time

CS

t

Seqeuntial Program Mode

Command

Opcode

SI

SO

Note: Each transition shown for SI represents one byte (8 bits)

A23-16 A15-8 A7-0 Data

First Address to Program

HIGH-IMPEDANCE

BP

Seqeuntial Program Mode

Command

Opcode

Data 04h

t

BP

Seqeuntial Program Mode

Command

Command

Opcode

Opcode

Data 05h

Data

Write Disable

Command

t

BP

STATUS REGISTER

Write Disable

Command

DATA

12

AT26DF081A

3600H–DFLASH–11/2012