Rainbow Electronics AT25DQ161 User Manual
AT25DQ161
16-Mbit, 2.7V Minimum SPI Serial Flash Memory
with Dual-I/O and Quad-I/O Support
DATASHEET
Not Recommended for New Designs
Use AT25DQ321
Features
Single 2.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 and 3
Supports RapidS
Supports Dual- and Quad-Input Program
Supports Dual- and Quad-Output Read
Very high operating frequencies
100MHz for RapidS
85MHz for SPI
Clock-to-output time (t
Flexible, optimized erase architecture for code + data storage applications
Uniform 4KB, 32KB, and 64KB Block Erase
Full Chip Erase
Individual sector protection with Global Protect/Unprotect feature
32 sectors of 64KB each
Hardware controlled locking of protected sectors via WP pin
Sector Lockdown
Make any combination of 64KB sectors permanently read-only
128-byte One-Time Programmable (OTP) Security Register
Flexible programming
Byte/Page Program (1 to 256 bytes)
Fast Program and Erase times
1.0ms typical Page Program (256 bytes) time
50ms typical 4KB Block Erase time
250ms typical 32KB Block Erase time
400ms typical 64KB Block Erase time
Program and Erase Suspend/Resume
Automatic checking and reporting of erase/program failures
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low power dissipation
5mA Active Read current (typical at 20MHz)
5μA Deep Power-Down current (typical)
Endurance: 100,000 Program/Erase cycles
Data retention: 20 years
Complies with full industrial temperature range
Industry standard green (Pb/Halide-free/RoHS-compliant) package options
8-lead SOIC (0.150" and 0.208" wide)
8-pad Ultra Thin UDFN (5 x 6 x 0.6mm)
™
operation
) of 5ns maximum
V
8671C–DFLASH–11/2012
1. Description
The AT25DQ161 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer
based applications in which program code is shadowed from Flash memory into embedded or external RAM for
execution. The flexible erase architecture of the AT25DQ161, with its erase granularity as small as 4KB, makes it ideal
for data storage as well, eliminating the need for additional data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT25DQ161 have been optimized to meet the needs of today's
code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space
can be used much more efficiently. Because certain code modules and data storage segments must reside by
themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and
large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows
additional code routines and data storage segments to be added while still maintaining the same overall device density.
The AT25DQ161 also offers a sophisticated method for protecting individual sectors against erroneous or malicious
program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can
unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely
protected. This is useful in applications where the program code is patched, updated on a subroutine or module basis, or
in applications where data storage segments need to be modified without running the risk of errant modifications to the
program code segments. In addition to individual sector protection capabilities, the AT25DQ161 incorporates Global
Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at
once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one
prior to initial programming.
To take code and data protection to the next level, the AT25DQ161 incorporates a sector lockdown mechanism that
allows any combination of individual 64KB sectors to be locked down and become permanently read-only. This
addresses the need of certain secure applications that require portions of the Flash memory array to be permanently
protected against malicious attempts at altering program code, data modules, security information or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time
Programmable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3V systems, the AT25DQ161 supports read, program, and erase operations with a
supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
2
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is
deasserted, the device will be deselected and normally be placed in standby
mode (not Deep Power-Down mode), and the SO pin will be in a
high-impedance state. When the device is deselected, data will not be accepted
CS
SCK
SI (I/O0)
on the SI pin.
A high-to-low transition on the
low-to-high transition is required to end an operation. When ending an internally
self-timed operation such as a program or erase cycle, the device will not enter
the standby mode until the completion of the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to
control the flow of data to and from the device. Command, address, and input
data present on the SI pin or I/O pins is always latched in on the rising edge of
SCK, while output data on the SO pin or I/O pins is always clocked out on the
falling edge of SCK.
Serial Input (I/O0): The SI pin is used to shift data into the device. The SI pin is
used for all data input including command and address sequences. Data on the
SI pin is always latched in on the rising edge of SCK.
With the Dual-Input and Quad-Input Byte/Page Program commands, the SI pin
is used as an input pin (I/O
(on I/O
) or four bits (on I/O
1-0
) in conjunction with other pins to allow two bits
0
3-0
SCK. With the Dual-Output and Quad-Output Read Array commands, the SI pin
becomes an output pin (I/O
(on I/O
) or four bits (on I/O
1-0
) and, along with other pins, allows two bits
0
3-0
of SCK. To maintain consistency with SPI nomenclature, the SI (I/O
referenced as SI throughout the document with exception to sections dealing
with the Dual-Input and Quad-Input Byte/Page Program commands as well as
the Dual-Output and Quad-Output Read Array commands in which it will be
referenced as I/O
.
0
Data present on the SI pin will be ignored whenever the device is deselected
CS is deasserted).
(
CS pin is required to start an operation, and a
) of data to be clocked in on every rising edge of
) of data to be clocked out on every falling edge
) pin will be
0
Asserted
State
Low Input
— Input
— Input/Output
Type
SO (I/O1)
Serial Output (I/O1): The SO pin is used to shift data out from the device. Data
on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input and Quad-Input Byte/Page Program commands, the SO pin
becomes an input pin (I/O
or four bits (on I/O
3-0
) and, along with other pins, allows two bits (on I/O
1
1-0
) of data to be clocked in on every rising edge of SCK. With
the Dual-Output and Quad-Output Read Array commands, the SO pin is used
as an output pin (I/O
or four bits (on I/O
maintain consistency with SPI nomenclature, the SO (I/O
) in conjunction with other pins to allow two bits (on I/O
1
) of data to be clocked out on every falling edge of SCK. To
3-0
) pin will be
1
1-0
referenced as SO throughout the document with exception to sections dealing
with the Dual-Input and Quad-Input Byte/Page Program commands as well as
the Dual-Output and Quad-Output Read Array commands in which it will be
referenced as I/O
.
1
The SO pin will be in a high-impedance state whenever the device is deselected
CS is deasserted).
(
AT25DQ161 [DATASHEET]
)
)
— Input/Output
3
8671C–DFLASH–11/2012
Table 2-1. Pin Descriptions (Continued)
Symbol Name and Function
Write Protect (I/O2): The WP# pin controls the hardware locking feature of the
device. See “Protection Commands and Features” on page 24 for more details
on protection features and the
With the Quad-Input Byte/Page Program command, the
WP (I/O2)
input pin (I/O
be clocked in on every rising edge of SCK. With the Quad-Output Read Array
command, the
) and, along with other pins, allows four bits (on I/O
2
WP pin becomes an output pin (I/O2) and, when used with other
pins, allows four bits (on I/O
SCK. The QE bit in the Configuration Register must be set in order for the
pin to be used as an I/O data pin.
WP pin must be driven at all times or pulled-high using an external pull-up
The
resistor.
Hold (I/O3): The HOLD pin is used to temporarily pause serial communication
without deselecting or resetting the device. While the
transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin
will be in a high-impedance state.
The
CS pin must be asserted, and the SCK pin must be in the low state in order
for a Hold condition to start. A Hold condition pauses serial communication only
and does not have an affect on internally self-timed operations such as a
program or erase cycle. See “Hold” on page 53 for additional details on the Hold
HOLD (I/O3)
operation.
With the Quad-Input Byte/Page Program command, the
input pin (I/O
) and, along with other pins, allows four bits (on I/O
3
be clocked in on every rising edge of SCK. With the Quad-Output Read Array
command, the
HOLD pin becomes an output pin (I/O3) and, when used with
other pins, allows four bits (on I/O
edge of SCK. The QE bit in the Configuration Register must be set in order for
the
HOLD pin to be used as an I/O data pin.
HOLD pin must be driven at all times or pulled-high using an external pull-
The
up resistor.
WP pin.
WP pin becomes an
) of data to
3-0
) of data to be clocked out on every falling edge of
3-0
HOLD pin is asserted,
HOLD pin becomes an
) of data to
3-0
) of data to be clocked out on every falling
3-0
WP
Asserted
State
Low Input
Low Input
Type
Device Power Supply: The VCC pin is used to supply the source voltage to the
V
CC
device.
Operations at invalid V
be attempted.
GND
Ground: The ground reference for the power supply. GND should be
connected to the system ground.
Figure 2-1. 8-SOIC
(Top View)
1
CS
SO (I/O )
WP (I/O )
GND
2
1
3
2
4
8
7
6
5
V
CC
HOLD (I/O )
SCK
SI (I/O )
0
voltages may produce spurious results and should not
CC
Figure 2-2. 8-UDFN
(Top View)
1
CS
GND
2
1
3
2
4
3
WP (I/O )
SO (I/O )
8
V
CC
7
HOLD (I/O )
6
SCK
5
SI (I/O )
3
0
AT25DQ161 [DATASHEET]
— Power
— Power
4
8671C–DFLASH–11/2012
3. Block Diagram
Figure 3-1. Block Diagram
CS
SCK
SI (I/O0)
SO (I/O1)
WP (I/O2)
HOLD (I/O3)
Note: I/O
Control and
Protection Logic
Interface
Control
and
Logic
Address Latch
pin naming convention is used for Dual-I/O and Quad-I/O commands
3-0
Y-Decoder
X-Decoder
I/O Buffers
and Latches
SRAM
Data Buffer
Y-Gating
Flash
Memory
Array
AT25DQ161 [DATASHEET]
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5
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DQ161 can be erased in four levels of granularity
including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each
sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for
both code and data storage applications, allowing both code and data segments to reside in their own isolated regions.
The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each
physical sector.
Figure 4-1. Memory Architecture Diagram
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
256 bytes
AT25DQ161 [DATASHEET]
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6
5. Device Operation
The AT25DQ161 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the
SPI Master. The SPI Master communicates with the AT25DQ161 via the SPI bus which is comprised of four signal lines:
Chip Select (
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DQ161
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
SI
SO
MSB LSB
5.1 Dual-I/O and Quad-I/O Operation
The AT25DQ161 features a Dual-Input Program mode and a Dual-Output Read mode that allows two bits of data to be
clocked into or out of the device every clock cycle to improve throughputs. To accomplish this, both the SI and SO pins
are utilized as inputs/outputs for the transfer of data bytes. With the Dual-Input Byte/Page Program command, the SO
pin becomes an input along with the SI pin. Alternatively, with the Dual-Output Read Array command, the SI pin
becomes an output along with the SO pin. For both Dual-I/O commands, the SO pin will be referred to as I/O
SI pin will be referred to as I/O
.
0
The device also supports a Quad-Input Program mode and a Quad-Output Read mode in which the
become data pins for even higher throughputs. For the Quad-Input Byte/Page Program command and for the
Quad-Output Read Array command, the
, WP becomes I/O2, SO becomes I/O1, and SI becomes I/O0. The QE bit in the Configuration Register must be set in
I/O
3
HOLD, WP, SO, and SI pins are referred to as I/O
order for both Quad-I/O commands to be enabled and for the
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the
Opcodes not supported by the AT25DQ161 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (
then reasserted). In addition, if the
device, then no operation will be performed, and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DQ161 memory array is 1FFFFFh, address bits A23-A21 are always ignored by
the device.
CS pin is deasserted before complete opcode and address information is sent to the
MSB LSB
WP and HOLD pins
where HOLD becomes
3-0
HOLD and WP pins to be converted to I/O data pins.
CS pin being deasserted and
and the
1
CS pin.
AT25DQ161 [DATASHEET]
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7
Table 6-1. Command Listing
Clock
Command Opcode
Read Commands
1Bh 0001 1011 Up to 100MHz 3 2 1+
Read Array
Dual-Output Read Array 3Bh 0011 1011 Up to 85MHz 3 1 1+
Quad-Output Read Array 6Bh 0110 1011 Up to 85MHz 3 1 1+
Program and Erase Commands
Block Erase (4KB) 20h 0010 0000 Up to 100MHz 3 0 0
Block Erase (32KB) 52h 0101 0010 Up to 100MHz 3 0 0
Block Erase (64KB) D8h 1101 1000 Up to 100MHz 3 0 0
Chip Erase
Byte/Page Program (1 to 256 bytes) 02h 0000 0010 Up to 100MHz 3 0 1+
Dual-Input Byte/Page Program (1 to 256 bytes) A2h 1010 0010 Up to 100MHz 3 0 1+
Quad-Input Byte/Page Program (1 to 256 bytes) 32h 0011 0010 Up to 100MHz 3 0 1+
Program/Erase Suspend B0h 1011 0000 Up to 100MHz 0 0 0
Program/Erase Resume D0h 1101 0000 Up to 100MHz 0 0 0
Protection Commands
Write Enable 06h 0000 0110 Up to 100MHz 0 0 0
Write Disable 04h 0000 0100 Up to 100MHz 0 0 0
Protect Sector 36h 0011 0110 Up to 100MHz 3 0 0
Unprotect Sector 39h 0011 1001 Up to 100MHz 3 0 0
Global Protect/Unprotect Use Write Status Register Byte 1 Command
Read Sector Protection Registers 3Ch 0011 1100 Up to 100MHz 3 0 1+
Security Commands
Sector Lockdown 33h 0011 0011 Up to 100MHz 3 0 1
Freeze Sector Lockdown State 34h 0011 0100 Up to 100MHz 3 0 1
Read Sector Lockdown Registers 35h 0011 0101 Up to 100MHz 3 0 1+
Program OTP Security Register 9Bh 1001 1011 Up to 100MHz 3 0 1+
Read OTP Security Register 77h 0111 0111 Up to 100MHz 3 2 1+
Status and Configuration Register Commands
Read Status Register 05h 0000 0101 Up to 100MHz 0 0 1+
Write Status Register Byte 1 01h 0000 0001 Up to 100MHz 0 0 1
Write Status Register Byte 2 31h 0011 0001 Up to 100MHz 0 0 1
Read Configuration Register 3Fh 0011 1111 Up to 100MHz 0 0 1+
Write Configuration Register 3Eh 0011 1110 Up to 100MHz 0 0 1
Miscellaneous Commands
Reset F0h 1111 0000 Up to 100MHz 0 0 1
Read Manufacturer and Device ID 9Fh 1001 1111 Up to 85MHz 0 0 1 to 5
Deep Power-Down B9h 1011 1001 Up to 100MHz 0 0 0
Resume from Deep Power-Down ABh 1010 1011 Up to 100MHz 0 0 0
0Bh 0000 1011 Up to 85MHz 3 1 1+
03h 0000 0011 Up to 40MHz 3 0 1+
60h 0110 0000 Up to 100MHz 0 0 0
C7h 1100 0111 Up to 100MHz 0 0 0
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
AT25DQ161 [DATASHEET]
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8
7. Read Commands
7.1 Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address has been specified. The device incorporates an internal
address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by f
to the maximum specified by f
any clock frequency up to the maximum specified by f
should be reserved to systems employing the RapidS protocol.
f
CLK
To perform the Read Array operation, the
must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the memory array. Following the three address bytes,
additional dummy bytes may need to be clocked into the device depending on which opcode is used for the Read Array
operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the device after the three address
bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a byte
first. When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading back at the
beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
Deasserting the
be deasserted at any time and does not require that a full byte of data be read.
CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
, and the 03h opcode can be used for lower frequency read operations up
CLK
. The 1Bh opcode allows the highest read performance possible and can be used at
RDLF
; however, use of the 1Bh opcode at clock frequencies above
MAX
CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or 03h)
AT25DQ161 [DATASHEET]
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9
Figure 7-1. Read Array – 1Bh Opcode
CS
2310
675410119812 394243414037 3833 36353431 3229 30 44 47 484645 50 5149 52 55 565453
SCK
Opcode
SI
SO
00011011
MSB MSB
High-impedance
AAAA AAAAA
Figure 7-2. Read Array – 0Bh Opcode
CS
2310
675410119812 394243414037 3833 36353431 3229 30 44 47 484645
SCK
Opcode
SI
SO
00001011
MSB MSB
High-impedance
Address Bits A23-A0 Don't Care
Don't Care
XXXXXXXX
MSB
XXXXXXXX
MSB
Address Bits A23-A0 Don't Care
AAAA AAAAA
XXXXXXXX
MSB
Data Byte 1
DDDDDDDDDD
MSB MSB
Data Byte 1
DDDDDDDDDD
MSB MSB
Figure 7-3. Read Array – 03h Opcode
CS
2310
675410119812 373833 36353431 3229 30 39 40
SCK
Opcode
SI
SO
00000011
MSB MSB
High-impedance
Address Bits A23-A0
AAAA AAAAA
Data Byte 1
DDDDDDDDDD
MSB MSB
AT25DQ161 [DATASHEET]
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10
7.2 Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by f
perform the Dual-Output Read Array operation, the
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting
address location of the first byte to read within the memory array. Following the three address bytes, a single dummy
byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the I/O1 and I/O0 pins. The data is always output with the MSB of a byte first, and the MSB is always
output on the I/O
same data byte will be output on the I/O
on the I/O
1
cycles. When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading back at the
beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
Deasserting the
can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-4. Dual-Output Read Array
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O1 pin while bit 6 of the
1
and I/O0 pins, respectively. The sequence continues with each byte of data being output after every four clock
CS pin will terminate the read operation and put the I/O
. To
RDDO
CS pin must first be asserted and the opcode of 3Bh must be clocked
pin. During the next clock cycle, bits 5 and 4 of the first data byte will be output
0
pins into a high-impedance state. The CS pin
1-0
CS
SCK
SI (I/O0)
SO (I/O1)
2310
Opcode
00111011
MSB MSB
High-impedance
675410119812 394243414037 3833 36353431 3229 30 44 47 484645
Address Bits A23-A0 Don't Care
AAAA AAAAA
XXXXXXXX
MSB
Output
Data Byte 1
D
D
D
6
4
D
D
D
7
5
MSB MSB MSB
2
3
D
0
D
1
Output
Data Byte 2
D
D
6
D
D
7
D
D
4
2
D
5
3
D
D
6
4
0
D
D
D
7
5
1
AT25DQ161 [DATASHEET]
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11
7.3 Quad-Output Read Array
The Quad-Output Read Array command is similar to the Dual-Output Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting
address has been specified. Unlike the Dual-Output Read Array command, however, the Quad-Output Read Array
command allows four bits of data to be clocked out of the device on every clock cycle rather than two.
The Quad-Output Read Array command can be used at any clock frequency up to the maximum specified by f
perform the Quad-Output Read Array operation, the
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, a single
dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on the I/O
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O
data byte will be output on the I/O
first data byte will be output on the I/O
data being output after every two clock cycles. When the last byte (1FFFFFh) of the memory array has been read, the
device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping
around from the end of the array to the beginning of the array.
Deasserting the
can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-5. Quad-Output Read Array
pins. The data is always output with the MSB of a byte first, and the MSB is always output on the I/O3
3-0
CS pin will terminate the read operation and put the I/O
. To
RDQO
CS pin must first be asserted and the opcode of 6Bh must be
pin while bits 6, 5, and 4 of the same
3
, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the
2
, I/O2, I/O1, and I/O0 pins, respectively. The sequence continues with each byte of
3
pins into a high-impedance state. The CS pin
3-0
CS
SCK
I/O
(SI)
I/O
(SO)
I/O
(WP)
I/O
(HOLD)
2310
Opcode
0
1
2
3
01101011
MSB MSB
High-impedance
High-impedance
High-impedance
675410119812 394243414037 3833 36353431 3229 30 44 47 484645
Byte 1
Byte 2
Address Bits A23-A0 Don't Care
AAAA AAAAA
XXXXXXXX
MSB
Out
D
D
4
0
D
D
5
1
D6D
2
D7D
3
MSB MSBMSB MSBMSB
Out
D
4
D
5
D6D
D7D
Byte 3
Out
D
D
D
0
4
D
D
D
1
5
D6D
2
D7D
3
Byte 4
Byte 5
Out
Out
D
D
D
0
4
D
1
5
D6D
2
D7D
3
D
0
4
0
D
D
D
1
5
1
D6D
2
2
D7D
3
3
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
12
8. Program and Erase Commands
8.1 Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed
into previously erased memory locations. An erased memory location is one that has all eight bits set to the Logical 1
state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must
have been previously issued to the device (see “Write Enable” on page 24) to set the Write Enable Latch (WEL) bit of the
Status Register to a Logical 1 state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three
address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have
been clocked in, data can then be clocked into the device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not
all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any
data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same
page.
Example: If the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of
data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h
through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more
than 256 bytes of data is sent to the device, then only the last 256 bytes sent will be latched into the internal
buffer.
When the
CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not
be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and
should take place in a time of t
The three address bytes and at least one complete byte of data must be clocked into the device before the
deasserted, and the
CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device
or tBP if only programming a single byte.
PP
CS pin is
will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by
A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector” on page 26) or
locked down (see “Sector Lockdown” on page 32), then the Byte/Page Program command will not be executed, and the
device will return to the idle state once the
CS pin has been deasserted. The WEL bit in the Status Register will be reset
back to the Logical 0 state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of
data being sent, the
CS pin being deasserted on uneven byte boundaries, or because the memory location to be
programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the t
or tPP time to determine if the
BP
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
13
Figure 8-1. Byte Program
CS
2310
SCK
Opcode
SI
SO
00000010
MSB MSB
High-impedance
Figure 8-2. Page Program
CS
2310
SCK
Opcode
SI
SO
00000010
MSB MSB
High-impedance
675410119812 3937 3833 36353431 3229 30
Address Bits A23-A0 Data In
AAAA AAAAA
6754983937 3833 36353431 3229 30
Address Bits A23-A0 Data In Byte 1
AA AAAA
DDDDDDDD
MSB
DDDDDDDD
MSB
Data In Byte N
DDDDDDDD
MSB
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
14
8.2 Dual-Input Byte/Page Program
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used
to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. Unlike
the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command allows two bits of
data to be clocked into the device on every clock cycle rather than just one.
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device (see “Write Enable” on page 24) to set the Write Enable Latch (WEL) bit of the Status
Register to a Logical 1 state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must be clocked
into the device followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the device two bits at a time
on both the I/O
The data is always input with the MSB of a byte first, and the MSB is always input on the I/O
cycle, bit 7 of the first data byte would be input on the I/O
pin. During the next clock cycle, bits 5 and 4 of the first data byte would be input on the I/O
The sequence would continue with each byte of data being input after every four clock cycles. Like the standard
Byte/Page Program command, all data clocked into the device is stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not
all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any
data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same
page.
Example: If the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
and I/O0 pins.
1
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of
data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h
through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more
than 256 bytes of data is sent to the device, then only the last 256 bytes sent will be latched into the internal
buffer.
pin. During the first clock
1
pin while bit 6 of the same data byte would be input on the I/O0
1
and I/O0 pins, respectively.
1
When the
CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not
be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and
should take place in a time of t
The three address bytes and at least one complete byte of data must be clocked into the device before the
deasserted, and the
CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device
or tBP if only programming a single byte.
PP
CS pin is
will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by
A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector” on page 26) or
locked down (see “Sector Lockdown” on page 32), then the Byte/Page Program command will not be executed, and the
device will return to the idle state once the
CS pin has been deasserted. The WEL bit in the Status Register will be reset
back to the Logical 0 state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of
data being sent, the
CS pin being deasserted on uneven byte boundaries, or because the memory location to be
programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the t
or tPP time to determine if the
BP
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
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Figure 8-3. Dual-Input Byte Program
CS
2310
SCK
Opcode
SI (I/O0)
SO (I/O1)
10100010
MSB MSB
High-impedance
Figure 8-4. Dual-Input Page Program
CS
2310
SCK
Opcode
SI (I/O0)
SO (I/O1)
10100010
MSB MSB
High-impedance
675410119812 33353431 3229 30
Address Bits A23-a0
AAAA AAAAA
675410119812 3937 3833 36353431 3229 30
Address Bits A23-A0
AAAA AAAAA
Input
Data Byte
D
D
D
4
2
D
D
5
3
Input
Data Byte 1
D
D
4
2
D
D
5
3
D
0
D
1
D
D
0
D
D
1
6
D
7
MSB
D
6
D
7
MSB MSB
Input
Data Byte 2
D
D
6
4
D
D
7
5
Input
Data Byte N
D
2
D
3
D
D
D
0
1
D
MSB
6
7
D
4
2
0
D
D
D
5
3
1
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
16
8.3 Quad-Input Byte/Page Program
The Quad-Input Byte/Page Program command is similar to the Dual-Input Byte/Page Program command and can be
used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations.
Unlike the Dual-Input Byte/Page Program command, however, the Quad-Input Byte/Page Program command allows four
bits of data to be clocked into the device on every clock cycle rather than two.
Before the Quad-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device (See “Write Enable” on page 24) to set the Write Enable Latch (WEL) bit of the Status
Register to a Logical 1 state. To perform a Quad-Input Byte/Page Program command, an opcode of 32h must be
clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the device four bits at a
time on the I/O
The data is always input with the MSB of a byte first, and the MSB is always input on the I/O
cycle, bit 7 of the first data byte would be input on the I/O
on the I/O
2
input on the I/O
after every two clock cycles. Like the standard Byte/Page Program and Dual-Input Byte/Page Program commands, all
data clocked into the device is stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on a 256-byte page boundary (A7-A0 are not all 0), then
special circumstances regarding which memory locations to be programmed will apply. In this situation, any data that is
sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page.
Example: If the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
pins.
3-0
, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte would be
, I/O2, I/O1, and I/O0 pins, respectively. The sequence would continue with each byte of data being input
3
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of
data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h
through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more
than 256 bytes of data is sent to the device, then only the last 256 bytes sent will be latched into the internal
buffer.
pin. During the first clock
3
pin while bits 6, 5, and 4 of the same data byte would be input
3
When the
CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will
not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed
and should take place in a time of t
The three address bytes and at least one complete byte of data must be clocked into the device before the
deasserted, and the
CS pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will
or tBP if only programming a single byte.
PP
CS pin is
abort the operation and no data will be programmed into the memory array. In addition, if the address specified by
A23-A0 points to a memory location within a sector that is in the protected state (See “Protect Sector” on page 26) or
locked down (See “Sector Lockdown” on page 32), then the Quad-Input Byte/Page Program command will not be
executed, and the device will return to the idle state once the
CS pin has been deasserted. The WEL bit in the Status
Register will be reset back to the Logical 0 state if the program cycle aborts due to an incomplete address being sent, an
incomplete byte of data being sent, the
CS pin being deasserted on uneven byte boundaries, or because the memory
location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the t
or tPP time to determine if the
BP
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
17
Figure 8-5. Quad-Input Byte Program
CS
2310
675410119812 3331 3229 30
SCK
Opcode
I/O
(SI)
I/O
0
1
00110010
MSB MSB
High-impedance
(SO)
I/O
2
High-impedance
(WP)
I/O
3
High-impedance
(HOLD)
Figure 8-6. Quad-Input Page Program
CS
Address Bits A23-a0
AAAA AAAAA
D
D
D6D
D7D
MSB
Byte
4
5
In
D
0
D
1
2
3
SCK
I/O
(SI)
I/O
(SO)
I/O
(WP)
I/O
(HOLD)
2310
Opcode
0
1
2
3
00110010
MSB MSB
High-impedance
High-impedance
High-impedance
675410119812 3937 3833 36353431 3229 30
Address Bits A23-A0
AAAA AAAAA
Byte 1InByte 2InByte 3InByte 4
D
D
D
D
D
D
4
0
D
D
D
5
1
D6D
D6D
2
D7D
D7D
3
MSB MSB MSBMSB
4
0
D
5
1
2
3
4
D
5
D6D
D7D
D
0
D
D
1
D6D
2
D7D
3
In
D
4
0
D
5
1
2
3
Byte n
D
D
D6D
D7D
MSB
In
D
4
0
D
5
1
2
3
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
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8.4 Block Erase
A block of 4, 32, or 64KB can be erased (all bits set to the Logical 1 state) in a single operation by using one of three
different opcodes for the Block Erase command. An opcode of 20h is used for a 4KB erase, an opcode of 52h is used for
a 32KB erase, and an opcode of D8h is used for a 64KB erase. Before a Block Erase command can be started, the Write
Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a Logical 1
state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the
4, 32, or 64KB block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When
CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally
the
self-timed and should take place in a time of t
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the
device. Therefore, for a 4KB erase, address bits A11-A0 will be ignored by the device and their values can be either a
Logical 1 or 0. For a 32KB erase, address bits A14-A0 will be ignored, and for a 64KB erase, address
bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must
be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no
erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked down
state, then the Block Erase command will not be executed, and the device will return to the idle state once the
been deasserted.
The WEL bit in the Status Register will be reset back to the Logical 0 state if the erase cycle aborts due to an incomplete
address being sent, the
region to be erased is protected or locked down.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error occurs, it will be indicated by the EPE bit in the Status Register.
.
BLKE
CS pin has
CS pin being deasserted on uneven byte boundaries, or because a memory location within the
time to
BLKE
Figure 8-7. Block Erase
CS
SCK
SI
SO
CCCCCCCC
MSB MSB
High-impedance
2310
Opcode
675410119812 3129 3027 2826
Address Bits A23-A0
AAAA AAAAA A A A
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
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8.5 Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase
command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit
of the Status Register to a Logical 1 state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality
when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes
(60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to
be clocked into the device, and any data clocked in after the opcode will be ignored. When the
device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a
time of t
The complete opcode must be clocked into the device before the
deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any
sector of the memory array is in the protected or locked down state, then the Chip Erase command will not be executed,
and the device will return to the idle state once the
be reset back to the Logical 0 state if the
or locked down state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error occurs, it will be indicated by the EPE bit in the Status Register.
CHPE
.
CS pin is deasserted, the
CS pin is deasserted, and the CS pin must be
CS pin has been deasserted. The WEL bit in the Status Register will
CS pin is deasserted on uneven byte boundaries or if a sector is in the protected
time to
CHPE
Figure 8-8. Chip Erase
CS
SCK
SI
SO
CCCCCCCC
MSB
High-impedance
2310
Opcode
6754
AT25DQ161 [DATASHEET]
8671C–DFLASH–11/2012
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