Rainbow Electronics AT25DF081A User Manual

Features

• Single 2.7V - 3.6V Supply

• Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3
– Supports RapidS
– Supports Dual-Input Program and Dual-Output Read

• Very High Operating Frequencies

– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (t

• Flexible, Optimized Erase Architecture for Code + Data Storage Applications

– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase

• Individual Sector Protection with Global Protect/Unprotect Feature

– 16 Sectors of 64-Kbytes Each

• Hardware Controlled Locking of Protected Sectors via WP Pin

• Sector Lockdown

– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only

• 128-Byte Programmable OTP Security Register

• Flexible Programming

– Byte/Page Program (1- to 256-Bytes)

• Fast Program and Erase Times

– 1.0ms Typical Page Program (256 Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time

• Automatic Checking and Reporting of Erase/Program Failures

• Software Controlled Reset

• JEDEC Standard Manufacturer and Device ID Read Methodology

• Low Power Dissipation

– 5mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)

• Endurance: 100,000 Program/Erase Cycles

• Data Retention: 20 Years

• Complies with Full Industrial Temperature Range

• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (150-mil and 208-mil wide)
– 8-pad Ultra Thin DFN (5x6x0.6mm)

™

Operation

) of 5ns Maximum

V

8-Mbit

2.7V Minimum
Serial Peripheral
Interface Serial
Flash Memory

AT25DF081A

8715C–SFLSH–11/2012

1. Description

The Adesto®AT25DF081A is a serial interface Flash memory device designed for use in a wide variety of high-vol­ume consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the AT25DF081A, with its erase granularity as small
as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM
devices.

The physical sectoring and the erase block sizes of the AT25DF081A have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same
overall device density.

The AT25DF081A also offers a sophisticated method for protecting individual sectors against erroneous or mali­cious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system
can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array
securely protected. This is useful in applications where program code is patched or updated on a subroutine or
module basis, or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DF081A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors
do not have to be unprotected one-by-one prior to initial programming.

To take code and data protection to the next level, the AT25DF081A incorporates a sector lockdown mechanism
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be per­manently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time Pro­grammable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.

Specifically designed for use in 3-volt systems, the AT25DF081A supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.

2

AT25DF081A

8715C–SFLSH–11/2012

2. Pin Descriptions and Pinouts

Table 2-1. Pin Descriptions

Symbol Name and Function

CS

SCK

SI (SIO)

CHIP SELECT: Asserting the
the device will be deselected and normally be placed in standby mode (not Deep Power­Down mode), and the SO pin will be in a high-impedance state. When the device is
deselected, data will not be accepted on the SI pin.

A high-to-low transition on the
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.

SERIAL INPUT (SERIAL INPUT/OUTPUT): The SI pin is used to shift data into the device.
The SI pin is used for all data input including command and address sequences. Data on the
SI pin is always latched in on the rising edge of SCK.

With the Dual-Output Read Array command, the SI pin becomes an output pin (SIO) to allow
two bits of data (on the SO and SIO pins) to be clocked out on every falling edge of SCK. To
maintain consistency with SPI nomenclature, the SIO pin will be referenced as SI throughout
the document with exception to sections dealing with the Dual-Output Read Array command
in which it will be referenced as SIO.

Data present on the SI pin will be ignored whenever the device is deselected (
deasserted).

CS pin selects the device. When the CS pin is deasserted,

CS pin is required to start an operation, and a low-to-high

AT25DF081A

Asserted

State Type

Low Input

- Input

- Input/Output

CS is

SO (SOI)

WP

HOLD

SERIAL OUTPUT (SERIAL OUTPUT/INPUT): The SO pin is used to shift data out from the
device. Data on the SO pin is always clocked out on the falling edge of SCK.

With the Dual-Input Byte/Page Program command, the SO pin becomes an input pin (SOI) to
allow two bits of data (on the SOI and SI pins) to be clocked in on every rising edge of SCK.
To maintain consistency with SPI nomenclature, the SOI pin will be referenced as SO
throughout the document with exception to sections dealing with the Dual-Input Byte/Page
Program command in which it will be referenced as SOI.

The SO pin will be in a high-impedance state whenever the device is deselected (
deasserted).

WRITE PROTECT: The
refer to “Protection Commands and Features” on page 17 for more details on protection
features and the

The

WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the
to V

whenever possible.

CC

HOLD: The
deselecting or resetting the device. While the
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.

The

CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to

“Hold” on page 41 for additional details on the Hold operation.

The

HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the
whenever possible.

WP pin.

HOLD pin is used to temporarily pause serial communication without

WP pin controls the hardware locking feature of the device. Please

WP pin also be externally connected

HOLD pin is asserted, transitions on the SCK

HOLD pin also be externally connected to V

CS is

CC

- Output/Input

Low Input

Low Input

8715C–SFLSH–11/2012

3

Table 2-1. Pin Descriptions (Continued)

Symbol Name and Function

DEVICE POWER SUPPLY: The VCCpin is used to supply the source voltage to the device.

V

CC

Operations at invalid V
attempted.

voltages may produce spurious results and should not be

CC

Asserted

State Type

-Power

GND

GROUND: The ground reference for the power supply. GND should be connected to the
system ground.

Figure 2-1. 8-SOIC (Top View) Figure 2-2. 8-UDFN (Top View)

CS

SO (SOI)

WP

GND

1

2

3

4

8

VCC

7

HOLD

6

SCK

5

SI (SIO)

SO (SOI)

CS

WP

GND

1

2

3

4

3. Block Diagram

Figure 3-1. Block Diagram

CONTROL AND

CS

PROTECTION LOGIC

-Power

8

VCC

7

HOLD

6

SCK

5

SI (SIO)

I/O BUFFERS

AND LATCHES

SRAM

SCK

SI (SIO)

SO (SOI)

INTERFACE

CONTROL

AND

LOGIC

Y-DECODER

DATA BUFFER

Y-GATING

FLASH

WP

HOLD

4

AT25DF081A

ADDRESS LATCH

X-DECODER

MEMORY

ARRAY

8715C–SFLSH–11/2012

4. Memory Array

r

To provide the greatest flexibility, the memory array of the AT25DF081A can be erased in four levels of granularity
including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which
each sector can be individually protected from program and erase operations. The size of the physical sectors is
optimized for both code and data storage applications, allowing both code and data segments to reside in their own
isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.

Figure 4-1. Memory Architecture Diagram

AT25DF081A

Block Erase Detail Page Program Detail

Internal Sectoring fo

Sector Protection Block Erase Block Erase Block Erase Page Program

Function (D8h Command) (52h Command) (20h Command) (02h Command)

64KB

(Sector 15)

64KB

(Sector 14)

• •

•

64KB

(Sector 0)

64KB 32KB 4KB 1-256 Byte

Range

0FFFFFh – 0FF000h 256 Bytes 0FFFFFh – 0FFF00h

0FEFFFh – 0FE000h 256 Bytes 0FFEFFh – 0FFE00h
0FDFFFh – 0FD000h 256 Bytes 0FFDFFh – 0FFD00h
0FCFFFh – 0FC000h 256 Bytes 0FFCFFh – 0FFC00h
0FBFFFh – 0FB000h 256 Bytes 0FFBFFh – 0FFB00h
0FAFFFh – 0FA000h 256 Bytes 0FFAFFh – 0FFA00h

0F9FFFh – 0F9000h 256 Bytes 0FF9FFh – 0FF900h

0F8FFFh – 0F8000h 256 Bytes 0FF8FFh – 0FF800h

0F7FFFh – 0F7000h 256 Bytes 0FF7FFh – 0FF700h

0F6FFFh – 0F6000h 256 Bytes 0FF6FFh – 0FF600h

0F5FFFh – 0F5000h 256 Bytes 0FF5FFh – 0FF500h

0F4FFFh – 0F4000h 256 Bytes 0FF4FFh – 0FF400h

0F3FFFh – 0F3000h 256 Bytes 0FF3FFh – 0FF300h

0F2FFFh – 0F2000h 256 Bytes 0FF2FFh – 0FF200h

0F1FFFh – 0F1000h 256 Bytes 0FF1FFh – 0FF100h

0F0FFFh – 0F0000h 256 Bytes 0FF0FFh – 0FF000h
0EFFFFh – 0EF000h 256 Bytes 0FEFFFh – 0FEF00h
0EEFFFh – 0EE000h 256 Bytes 0FEEFFh – 0FEE00h
0EDFFFh – 0ED000h 256 Bytes 0FEDFFh – 0FED00h
0ECFFFh – 0EC000h 256 Bytes 0FECFFh – 0FEC00h
0EBFFFh – 0EB000h 256 Bytes 0FEBFFh – 0FEB00h
0EAFFFh – 0EA000h 256 Bytes 0FEAFFh – 0FEA00h

0E9FFFh – 0E9000h 256 Bytes 0FE9FFh – 0FE900h

0E8FFFh – 0E8000h 256 Bytes 0FE8FFh – 0FE800h

0E7FFFh – 0E7000h

0E6FFFh – 0E6000h

0E5FFFh – 0E5000h

0E4FFFh – 0E4000h 256 Bytes 0017FFh – 001700h

0E3FFFh – 0E3000h 256 Bytes 0016FFh – 001600h

0E2FFFh – 0E2000h 256 Bytes 0015FFh – 001500h

0E1FFFh – 0E1000h 256 Bytes 0014FFh – 001400h

0E0FFFh – 0E0000h 256 Bytes 0013FFh – 001300h

00FFFFh – 00F000h 256 Bytes 000FFFh – 000F00h

00EFFFh – 00E000h 256 Bytes 000EFFh – 000E00h
00DFFFh – 00D000h 256 Bytes 000DFFh – 000D00h
00CFFFh – 00C000h 256 Bytes 000CFFh – 000C00h

00BFFFh – 00B000h 256 Bytes 000BFFh – 000B00h

00AFFFh – 00A000h 256 Bytes 000AFFh – 000A00h

009FFFh – 009000h 256 Bytes 0009FFh – 000900h
008FFFh – 008000h 256 Bytes 0008FFh – 000800h
007FFFh – 007000h 256 Bytes 0007FFh – 000700h
006FFFh – 006000h 256 Bytes 0006FFh – 000600h
005FFFh – 005000h 256 Bytes 0005FFh – 000500h
004FFFh – 004000h 256 Bytes 0004FFh – 000400h
003FFFh – 003000h 256 Bytes 0003FFh – 000300h
002FFFh – 002000h 256 Bytes 0002FFh – 000200h
001FFFh – 001000h 256 Bytes 0001FFh – 000100h
000FFFh – 000000h 256 Bytes 0000FFh – 000000h

•

• •

256 Bytes 0012FFh – 001200h
256 Bytes 0011FFh – 001100h
256 Bytes 0010FFh – 001000h

64KB

64KB

64KB

4KB
4KB
4KB

32KB

32KB

32KB

32KB

• • •

32KB

32KB

• •

•

4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB

4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB

•

• •

Page AddressBlock Address

Range

8715C–SFLSH–11/2012

5

5. Device Operation

The AT25DF081A is controlled by a set of instructions that are sent from a host controller, commonly referred to as
the SPI Master. The SPI Master communicates with the AT25DF081A via the SPI bus which is comprised of four
signal lines: Chip Select (

The AT25DF081A features a dual-input program mode in which the SO pin becomes an input. Similarly, the device
also features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page Pro­gram command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual­Output Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect
to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The
AT25DF081A supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes
0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and
not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and
always output on the falling edge of SCK.

Figure 5-1. SPI Mode 0 and 3

CS

SCK

CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

SI

SO

MSB LSB

6. Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruc­tion dependent information such as address and data bytes would then be clocked out by the host controller. All
opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by
deasserting the CS pin.

Opcodes not supported by the AT25DF081A will be ignored by the device and no operation will be started. The
device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being
deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address
information is sent to the device, then no operation will be performed and the device will simply return to the idle
state and wait for the next operation.

Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DF081A memory array is 0FFFFFh, address bits A23-A20 are always
ignored by the device.

MSB

LSB

6

AT25DF081A

8715C–SFLSH–11/2012

Table 6-1. Command Listing

AT25DF081A

Clock

Command Opcode

Read Commands

1Bh 0001 1011 Up to 100MHz 3 2 1+

Read Array

Dual-Output Read Array 3Bh 0011 1011 Up to 85MHz 3 1 1+

Program and Erase Commands

Block Erase (4 KBytes) 20h 0010 0000 Up to 100MHz 3 0 0

Block Erase (32 KBytes) 52h 0101 0010 Up to 100MHz 3 0 0

Block Erase (64 KBytes) D8h 1101 1000 Up to 100MHz 3 0 0

Chip Erase

Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 100MHz 3 0 1+

Dual-Input Byte/Page Program (1 to 256 Bytes) A2h 1010 0010 Up to 100MHz 3 0 1+

Protection Commands

Write Enable 06h 0000 0110 Up to 100MHz 0 0 0

Write Disable 04h 0000 0100 Up to 100MHz 0 0 0

0Bh 0000 1011 Up to 85MHz 3 1 1+

03h 0000 0011 Up to 50MHz 3 0 1+

60h 0110 0000 Up to 100MHz 0 0 0

C7h 1100 0111 Up to 100MHz 0 0 0

Frequency

Address

Bytes

Dummy

Bytes

Data

Bytes

Protect Sector 36h 0011 0110 Up to 100MHz 3 0 0

Unprotect Sector 39h 0011 1001 Up to 100MHz 3 0 0

Global Protect/Unprotect Use Write Status Register Byte 1 Command

Read Sector Protection Registers 3Ch 0011 1100 Up to 100MHz 3 0 1+

Security Commands

Sector Lockdown 33h 0011 0011 Up to 100MHz 3 0 1

Freeze Sector Lockdown State 34h 0011 0100 Up to 100MHz 3 0 1

Read Sector Lockdown Registers 35h 0011 0101 Up to 100MHz 3 0 1+

Program OTP Security Register 9Bh 1001 1011 Up to 100MHz 3 0 1+

Read OTP Security Register 77h 0111 0111 Up to 100MHz 3 2 1+

Status Register Commands

Read Status Register 05h 0000 0101 Up to 100MHz 0 0 1+

Write Status Register Byte 1 01h 0000 0001 Up to 100MHz 0 0 1

Write Status Register Byte 2 31h 0011 0001 Up to 100MHz 0 0 1

Miscellaneous Commands

Reset F0h 1111 0000 Up to 100MHz 0 0 1

Read Manufacturer and Device ID 9Fh 1001 1111 Up to 85MHz 0 0 1 to 4

Deep Power-Down B9h 1011 1001 Up to 100MHz 0 0 0

Resume from Deep Power-Down ABh 1010 1011 Up to 100MHz 0 0 0

8715C–SFLSH–11/2012

7

7. Read Commands

7.1 Read Array

The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address has been specified. The device incorporates an internal
address counter that automatically increments on every clock cycle.

Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends
on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at
any clock frequency up to the maximum specified by f
read operations up to the maximum specified by f
sible and can be used at any clock frequency up to the maximum specified by f
opcode at clock frequencies above f

To perform the Read Array operation, the
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the starting address location of the first byte to read within the memory array. Following the
three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode
is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after
the address bytes.

After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a
byte first. When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading back
at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array
to the beginning of the array.

, and the 03h opcode can be used for lower frequency

CLK

. The 1Bh opcode allows the highest read performance pos-

RDLF

; however, use of the 1Bh

MAX

should be reserved to systems employing the RapidS protocol.

CLK

CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 7-1. Read Array – 1Bh Opcode

CS

SCK

SI

SO

2310

OPCODE

00011011

MSB MSB

HIGH-IMPEDANCE

675410119812 394243414037 3833 36353431 3229 30 44 47 484645 50 5149 52 55 565453

ADDRESS BITS A23-A0 DON'T CARE

AAAA AAAA A

DON'T CARE

XXXXXXXX

MSB

XXXXXXXX

MSB

DATA BYTE 1

DDDDDDDDDD

MSB MSB

8

AT25DF081A

8715C–SFLSH–11/2012

Figure 7-2. Read Array – 0Bh Opcode

CS

AT25DF081A

2310

675410119812 394243414037 3833 36353431 3229 30 44 47 484645

SCK

OPCODE

SI

SO

00001011

MSB MSB

HIGH-IMPEDANCE

AAAA AAAA A

Figure 7-3. Read Array – 03h Opcode

CS

2310

675410119812 373833 36353431 3229 30 39 40

SCK

OPCODE

SI

SO

00000011

MSB MSB

HIGH-IMPEDANCE

AAAA AAAA A

ADDRESS BITS A23-A0 DON'T CARE

XXXXXXXX

MSB

DATA BYTE 1

DDDDDDDDDD

MSB MSB

ADDRESS BITS A23-A0

DATA BYTE 1

DDDDDDDDDD

MSB MSB

8715C–SFLSH–11/2012

9

7.2 Dual-Output Read Array

The Dual-Output Read Array command is similar to the standard Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial
starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read
Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.

The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by f

RDDO

To perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the memory array. Following the three address
bytes, a single dummy byte must also be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data
being output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is
always output on the SO pin. During the first clock cycle, bit seven of the first data byte will be output on the SO pin
while bit six of the same data byte will be output on the SIO pin. During the next clock cycle, bits five and four of the
first data byte will be output on the SO and SIO pins, respectively. The sequence continues with each byte of data
being output after every four clock cycles. When the last byte (0FFFFFh) of the memory array has been read, the
device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrap­ping around from the end of the array to the beginning of the array.

Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 7-4. Dual-Output Read Array

CS

2310

675410119812 394243414037 3833 36353431 3229 30 44 47 484645

SCK

OPCODE

ADDRESS BITS A23-A0 DON'T CARE

OUTPUT

DATA BYTE 1

OUTPUT

DATA BYTE 2

.

10

SIO

SO

00111011

MSB MSB

HIGH-IMPEDANCE

AT25DF081A

AAAA AAAAA

XXXXXXXX

MSB

D

D

D

D

D

D

D

6

4

2

0

6

D

D

D

D

7

5

MSB MSB MSB

D

3

1

7

D

4

2

0

D

D

D

5

3

1

8715C–SFLSH–11/2012

D

D

6

4

D

D

7

5

8. Program and Erase Commands

8.1 Byte/Page Program

The Byte/Page Program command allows anywhere from a single byte of data to 256-bytes of data to be pro­grammed into previously erased memory locations. An erased memory location is one that has all eight bits set to
the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable
command must have been previously issued to the device (see “Write Enable” on page 17) to set the Write Enable
Latch (WEL) bit of the Status Register to a logical “1” state.

To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the
three address bytes denoting the first byte location of the memory array to begin programming at. After the address
bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situa­tion, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addi­tion, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched into the
internal buffer.

AT25DF081A

When the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within the
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is inter­nally self-timed and should take place in a time of tPPor tBPif only programming a single byte.

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”

on page 19) or locked down (see “Sector Lockdown” on page 25), then the Byte/Page Program command will not

be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBPor tPPtime to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to pro­gram properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the

8715C–SFLSH–11/2012

11

Figure 8-1. Byte Program

CS

2310

SCK

OPCODE

SI

SO

00000010

MSB MSB

HIGH-IMPEDANCE

Figure 8-2. Page Program

CS

2310

SCK

OPCODE

SI

SO

00000010

MSB MSB

HIGH-IMPEDANCE

675410119812 3937 3833 36353431 3229 30

ADDRESS BITS A23-A0 DATA IN

AAAA AAAA A

6754983937 3833 36353431 3229 30

ADDRESS BITS A23-A0 DATA IN BYTE 1

AA AAAA

DDDDDDDD

MSB

DDDDDDDD

MSB

DATA IN BYTE n

DDDDDDDD

MSB

12

AT25DF081A

8715C–SFLSH–11/2012

8.2 Dual-Input Byte/Page Program

The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be
used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory loca­tions. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command
allows two bits of data to be clocked into the device on every clock cycle rather than just one.

Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device (see “Write Enable” on page 17) to set the Write Enable Latch (WEL) bit of the Sta­tus Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h must
be clocked into the device followed by the three address bytes denoting the first byte location of the memory array
to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device
two bits at a time on both the SOI and SI pins.

The data is always input with the MSB of a byte first, and the MSB is always input on the SOI pin. During the first
clock cycle, bit seven of the first data byte would be input on the SOI pin while bit six of the same data byte would
be input on the SI pin. During the next clock cycle, bits five and four of the first data byte would be input on the SOI
and SI pins, respectively. The sequence would continue with each byte of data being input after every four clock
cycles. Like the standard Byte/Page Program command, all data clocked into the device is stored in an internal
buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situa­tion, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addi­tion, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched into the
internal buffer.

AT25DF081A

When the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within the
page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is inter­nally self-timed and should take place in a time of tPPor tBPif only programming a single byte.

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”

on page 19) or locked down (see “Sector Lockdown” on page 25), then the Byte/Page Program command will not

be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBPor tPPtime to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to pro­gram properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the

8715C–SFLSH–11/2012

13

Figure 8-3. Dual-Input Byte Program

CS

2310

675410119812 33353431 3229 30

SCK

OPCODE

SI

SOI

10100010

MSB MSB

HIGH-IMPEDANCE

AAAA AAAA A

Figure 8-4. Dual-Input Page Program

CS

2310

675410119812 3937 3833 36353431 3229 30

SCK

OPCODE

SI

SOI

10100010

MSB MSB

HIGH-IMPEDANCE

AAAA AAAA A

ADDRESS BITS A23-A0

ADDRESS BITS A23-A0

INPUT

DATA BYTE

D

D

D

4

D

5

INPUT

D

4

D

5

D

2

0

D

D

3

1

D

D

D

2

0

D

D

D

3

1

6

D

7

MSB

DATA BYTE 1

D

6

D

7

MSB MSB

INPUT

DATA BYTE 2

D

D

6

4

2

D

D

7

5

3

INPUT

DATA BYTE n

D

0

D

1

D

D

MSB

D

D

6

7

D

4

2

0

D

D

D

5

3

1

14

AT25DF081A

8715C–SFLSH–11/2012

8.3 Block Erase

A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one
of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode
of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase
command can be started, the Write Enable command must have been previously issued to the device to set the
WEL bit of the Status Register to a logical “1” state.

AT25DF081A

To perform a Block Erase, the

CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must
be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address
within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device
will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the
block is internally self-timed and should take place in a time of t

BLKE

.

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded
by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values
can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a 64-Kbyte
erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded
by the device, the complete three address bytes must still be clocked into the device before the

CS pin is deas­serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the
device will abort the operation and no erase operation will be performed.

If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked
down state, then the Block Erase command will not be executed, and the device will return to the idle state once
the CS pin has been deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an
incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory
location within the region to be erased is protected or locked down.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
t

time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL

BLKE

bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase prop­erly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.

Figure 8-5. Block Erase

CS

SCK

SI

SO

8715C–SFLSH–11/2012

2310

OPCODE

CCCCCCCC

MSB MSB

HIGH-IMPEDANCE

675410119812 3129 3027 2826

ADDRESS BITS A23-A0

AAAA AAAA A A A A

15

8.4 Chip Erase

The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip
Erase command can be started, the Write Enable command must have been previously issued to the device to set
the WEL bit of the Status Register to a logical “1” state.

Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functional­ity when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two
opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address
bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS
pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed
and should take place in a time of t

The complete opcode must be clocked into the device before the
deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if
any sector of the memory array is in the protected or locked down state, then the Chip Erase command will not be
executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Sta­tus Register will be reset back to the logical “0” state if the
sector is in the protected or locked down state.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
t

time to determine if the device has finished erasing. At some point before the erase cycle completes, the

CHPE

WEL bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase prop­erly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.

CHPE

.

CS pin is deasserted, and the CS pin must be

CS pin is deasserted on uneven byte boundaries or if a

Figure 8-6. Chip Erase

CS

2310

SCK

OPCODE

SI

SO

CCCCCCCC

MSB

HIGH-IMPEDANCE

6754

16

AT25DF081A

8715C–SFLSH–11/2012