Rainbow Electronics AT25DF041A User Manual

Features

• Single 2.3V - 3.6V or 2.7V - 3.6V Supply

• Serial Peripheral Interface (SPI) Compatible

– Supports SPI Modes 0 and 3

• 70 MHz Maximum Clock Frequency

• Flexible, Uniform Erase Architecture

– 4-Kbyte Blocks – 32-Kbyte Blocks – 64-Kbyte Blocks – Full Chip Erase

• Individual Sector Protection with Global Protect/Unprotect Feature

– One 16-Kbyte Top Sector – Two 8-Kbyte Sectors – One 32-Kbyte Sector – Seven 64-Kbyte Sectors

• Hardware Controlled Locking of Protected Sectors via WP pin

• Flexible Programming Options

– Byte/Page Program (1 to 256 Bytes) – Sequential Program Mode Capability

• Fast Program and Erase Times

– 1.2 ms Typical Page Program (256 Bytes) Time – 50 ms Typical 4-Kbyte Block Erase Time – 250 ms Typical 32-Kbyte Block Erase Time – 400 ms Typical 64-Kbyte Block Erase Time

• Automatic Checking and Reporting of Erase/Program Failures

• JEDEC Standard Manufacturer and Device ID Read Methodology

• Low Power Dissipation

– 5 mA Active Read Current (Typical) – 15 µA Deep Power-down Current (Typical)

• Endurance: 100,000 Program/Erase Cycles

• Data Retention: 20 Years

• Complies with Full Industrial Temperature Range

• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options

– 8-lead SOIC (150-mil and 208-mil Wide) – 8-pad Ultra Thin DFN (5x6x0.6mm)

4-megabit

2.3-volt or

2.7-volt Minimum SPI Serial Flash Memory

AT25DF041A

1. Description

The AT25DF041A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF041A, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.

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The physical sectoring and the erase block sizes of the AT25DF041A have been optimized to meet the needs of today’s code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density.

The AT25DF041A also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF041A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming.

Specifically designed for use in 2.5-volt or 3-volt systems, the AT25DF041A supports read, program, and erase operations with a supply voltage range of 2.3V to 3.6V or 2.7V to 3.6V. No separate voltage is required for programming and erasing.

AT25DF041A

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2. Pin Descriptions and Pinouts

Table 2-1. Pin Descriptions

Symbol Name and Function

SCK

HOLD

GND

CHIP SELECT: Asserting the device will be deselected and normally be placed in standby mode (not Deep Power-down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin.

A high-to-low transition on the is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation.

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK.

SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK.

WRITE PROTECT: The section “Protection Commands and Features” on page 15 for more details on protection features and the

The

WP pin.

WP pin is internally pulled-high and may be left floating if hardware-controlled protection will not be used. However, it is recommended that the whenever possible.

HOLD: The

HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the SI pin will be ignored, and the SO pin will be in a high-impedance state.

The

CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to section “Hold”

on page 30 for additional details on the Hold operation.

The

HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the possible.

DEVICE POWER SUPPLY: The VCCpin is used to supply the source voltage to the device. Operations at invalid V

GROUND: The ground reference for the power supply. GND should be connected to the system ground.

CS pin selects the device. When the CS pin is deasserted, the

CS pin is required to start an operation, and a low-to-high transition

WP pin controls the hardware locking feature of the device. Please refer to

HOLD pin is asserted, transitions on the SCK pin and data on the

HOLD pin also be externally connected to VCCwhenever

voltages may produce spurious results and should not be attempted.

WP pin also be externally connected to V

AT25DF041A

Asserted

State Type

Low Input

Input

Output

Low Input

Power

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Figure 2-1. 8-SOIC Top View Figure 2-2. 8-UDFN Top View

CS SO

GND

1 2 3 4

VCC

HOLD

SCK

CS SO

GND

VCC HOLD SCK SI

3. Block Diagram

SCK

INTERFACE

CONTROL

4. Memory Array

CONTROL AND

PROTECTION LOGIC

AND

LOGIC

ADDRESS LATCH

To provide the greatest flexibility, the memory array of the AT25DF041A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program and erase operations. The sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the breakdown of each physical sector.

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

AT25DF041A

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Figure 4-1. Memory Architecture Diagram

64KB

(Sector 0)

32KB

• • •

64KB

32KB

• • •

64KB

32KB

• • •

64KB

(Sector 6)

64KB

16KB

(Sector 10)

8KB

(Sector 9)

8KB

(Sector 8)

32KB

(Sector 7)

Block Erase Detail Page Program Detail

AT25DF041A

Internal Sectoring fo

Sector Protection Block Erase Block Erase Block Erase Page Program

Function (D8h Command) (52h Command) (20h Command) (02h Command)

64KB 32KB 4KB 1-256 Byte

4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB

4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB

07FFFFh – 07F000h 07EFFFh – 07E000h 07DFFFh – 07D000h 07CFFFh – 07C000h 07BFFFh – 07B000h 07AFFFh – 07A000h 079FFFh – 079000h 078FFFh – 078000h 077FFFh – 077000h 076FFFh – 076000h 075FFFh – 075000h 074FFFh – 074000h 073FFFh – 073000h 072FFFh – 072000h 071FFFh – 071000h 070FFFh – 070000h 06FFFFh – 06F000h 06EFFFh – 06E000h 06DFFFh – 06D000h 06CFFFh – 06C000h 06BFFFh – 06B000h 06AFFFh – 06A000h 069FFFh – 069000h 068FFFh – 068000h 067FFFh – 067000h 066FFFh – 066000h 065FFFh – 065000h 064FFFh – 064000h 063FFFh – 063000h 062FFFh – 062000h 061FFFh – 061000h 060FFFh – 060000h

00FFFFh – 00F000h 00EFFFh – 00E000h 00DFFFh – 00D000h 00CFFFh – 00C000h 00BFFFh – 00B000h 00AFFFh – 00A000h 009FFFh – 009000h 008FFFh – 008000h 007FFFh – 007000h 006FFFh – 006000h 005FFFh – 005000h 004FFFh – 004000h 003FFFh – 003000h 002FFFh – 002000h 001FFFh – 001000h 000FFFh – 000000h

256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes

Page AddressBlock Address

RangeRange

07FFFFh – 07FF00h 07FEFFh – 07FE00h 07FDFFh – 07FD00h 07FCFFh – 07FC00h 07FBFFh – 07FB00h 07FAFFh – 07FA00h 07F9FFh – 07F900h 07F8FFh – 07F800h 07F7FFh – 07F700h 07F6FFh – 07F600h 07F5FFh – 07F500h 07F4FFh – 07F400h 07F3FFh – 07F300h 07F2FFh – 07F200h 07F1FFh – 07F100h 07F0FFh – 07F000h 07EFFFh – 07EF00h 07EEFFh – 07EE00h 07EDFFh – 07ED00h 07ECFFh – 07EC00h 07EBFFh – 07EB00h 07EAFFh – 07EA00h 07E9FFh – 07E900h 07E8FFh – 07E800h

0017FFh – 001700h 0016FFh – 001600h 0015FFh – 001500h 0014FFh – 001400h 0013FFh – 001300h 0012FFh – 001200h 0011FFh – 001100h 0010FFh – 001000h 000FFFh – 000F00h 000EFFh – 000E00h 000DFFh – 000D00h 000CFFh – 000C00h 000BFFh – 000B00h 000AFFh – 000A00h 0009FFh – 000900h 0008FFh – 000800h 0007FFh – 000700h 0006FFh – 000600h 0005FFh – 000500h 0004FFh – 000400h 0003FFh – 000300h 0002FFh – 000200h 0001FFh – 000100h 0000FFh – 000000h

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5. Device Operation

The AT25DF041A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF041A via the SPI bus which is comprised of four signal lines: Chip Select ( Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF041A supports the two most common modes, SPI modes 0 and 3. The only difference between SPI modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK.

Figure 5-1. SPI Mode 0 and 3

SCK

CS), Serial Clock (SCK), Serial

MSB LSB

6. Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the SPI Master must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT25DF041A will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CSpinis deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation.

Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23 - A0. Since the upper address limit of the AT25DF041A memory array is 07FFFFh, address bits A23 - A19 are always ignored by the device.

MSB

LSB

AT25DF041A

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AT25DF041A

Table 6-1. Command Listing

Command Opcode Address Bytes Dummy Bytes Data Bytes

Read Commands

Read Array 0Bh 0000 1011 3 1 1+

Read Array (Low Frequency) 03h 0000 0011 3 0 1+

Program and Erase Commands

Block Erase (4 Kbytes) 20h 0010 0000 3 0 0

Block Erase (32 Kbytes) 52h 0101 0010 3 0 0

Block Erase (64 Kbytes) D8h 1101 1000 3 0 0

Chip Erase

Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 3 0 1+

Sequential Program Mode

Protection Commands

60h 0110 0000 0 0 0

C7h 1100 0111 0 0 0

ADh 1010 1101 3, 0

AFh 1010 1111 3, 0

(1)

Write Enable 06h 0000 0110 0 0 0

Write Disable 04h 0000 0100 0 0 0

Protect Sector 36h 0011 0110 3 0 0

Unprotect Sector 39h 0011 1001 3 0 0

Global Protect/Unprotect Use Write Status Register command

Read Sector Protection Registers 3Ch 0011 1100 3 0 1+

Status Register Commands

Read Status Register 05h 0000 0101 0 0 1+

Write Status Register 01h 0000 0001 0 0 1

Miscellaneous Commands

Read Manufacturer and Device ID 9Fh 1001 1111 0 0 1 to 4

Deep Power-down B9h 1011 1001 0 0 0

Resume from Deep Power-down ABh 1010 1011 0 0 0

Note: 1. Three address bytes are only required for the first operation to designate the address to start programming at. Afterwards,

the internal address counter automatically increments, so subsequent Sequential Program Mode operations only require clocking in of the opcode and the data byte until the Sequential Program Mode has been exited.

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7. Read Commands

7.1 Read Array

The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the SCK signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle.

Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode depends on the maximum SCK frequency that will be used to read data from the device. The 0Bh opcode can be used at any SCK frequency up to the maximum specified by f opcode can be used for lower frequency read operations up to the maximum specified by f

To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. If the 0Bh opcode is used, then one don't care byte must also be clocked in after the three address bytes.

After the three address bytes (and the one don't care byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in serial data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (07FFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.

.The03h

SCK

RDLF

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 7-1. Read Array – 0Bh Opcode

SCK

2310

OPCODE

00001011

MSB MSB

HIGH-IMPEDANCE

Figure 7-2. Read Array – 03h Opcode

SCK

00000011

MSB MSB

HIGH-IMPEDANCE

675410119812 394243414037 3833 36353431 3229 30 44 47 484645

ADDRESS BITS A23-A0 DON'T CARE

AAAA AAAA A

2310

OPCODE

675410119812 373833 36353431 3229 30 39 40

ADDRESS BITS A23-A0

AAAA AAAA A

XXXXXXXX

MSB

DATA BYTE 1

MSB MSB

DATA BYTE 1

DDDDDDDDDD

MSB MSB

DDDDDDDDDD

AT25DF041A

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8. Program and Erase Commands

8.1 Byte/Page Program

The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see “Write Enable” on page 15 command description) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state.

To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer.

If the starting memory address denoted by A23 - A0 does not fall on an even 256-byte page boundary (A7 - A0 are not all 0’s), then special circumstances regarding which memory locations will be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23 - A0 is 0000FEh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will be unaffected and will not change. In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer.

AT25DF041A

When the gram it into the appropriate memory array locations based on the starting address specified by A23 - A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be altered. The programming of the data bytes is internally self-timed and should take place in a time of tPP.

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23 - A0 points to a memory location within a sector that is in the protected state (see section “Protect Sector” on

page 16), then the Byte/Page Program command will not be executed, and the device will return

to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBPor tPPtime to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

CS pin is deasserted, the device will take the data stored in the internal buffer and pro-

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The Byte/Page Program mode is the default programming mode after the device powers-up or resumes from a device reset.

Figure 8-1. Byte Program

SCK

Figure 8-2. Page Program

SCK

00000010

MSB MSB

HIGH-IMPEDANCE

2310

OPCODE

00000010

MSB MSB

HIGH-IMPEDANCE

2310

OPCODE

6754983937 3833 36353431 3229 30

ADDRESS BITS A23-A0 DATA IN BYTE 1

AA AAAA

675410119812 3937 3833 36353431 3229 30

ADDRESS BITS A23-A0 DATA IN

AAAA AAAA A

DDDDDDDD

MSB

DDDDDDDD

MSB

DATA IN BYTE n

DDDDDDDD

MSB

8.2 Sequential Program Mode

The Sequential Program Mode improves throughput over the Byte/Page Program command when the Byte/Page Program command is used to program single bytes only into consecutive address locations. For example, some systems may be designed to program only a single byte of information at a time and cannot utilize a buffered Page Program operation due to design restrictions. In such a case, the system would normally have to perform multiple Byte Program operations in order to program data into sequential memory locations. This approach can add considerable system overhead and SPI bus traffic.

The Sequential Programming Mode helps reduce system overhead and bus traffic by incorporating an internal address counter that keeps track of the byte location to program, thereby eliminating the need to supply an address sequence to the device for every byte to program. When using the Sequential Program mode, all address locations to be programmed must be in the erased state. Before the Sequential Program mode can first be entered, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To start the Sequential Program Mode, the CS pin must first be asserted, and either an opcode of ADh or AFh must be clocked into the device. For the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. After the address bytes have been clocked in, the byte of data to be programmed can be sent to the

AT25DF041A

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AT25DF041A

device. Deasserting the CS pin will start the internally self-timed program operation, and the byte of data will be programmed into the memory location specified by A23 - A0.

After the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the CS pin, clocking in the ADh or AFh opcode, and then clocking in the next byte of data. When the the next sequential memory location. The process would be repeated for any additional bytes. There is no need to reissue the Write Enable command once the Sequential Program Mode has been entered.

When the last desired byte has been programmed into the memory array, the Sequential Program Mode operation can be terminated by reasserting the Write Disable command to the device to reset the WEL bit in the Status Register back to the logical “0” state.

If more than one byte of data is ever clocked in during each program cycle, then only the last byte of data sent on the SI pin will be stored in the internal latches. The programming of each byte is internally self-timed and should take place in a time of tBP. For each program cycle, a complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the byte of data will not be programmed into the memory array, and the WEL bit in the Status Register will be reset back to the logical “0” state.

CS pin is deasserted, the second byte of data will be programmed into

CS pin and sending the

If the address initially specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Sequential Program Mode command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will also be reset back to the logical “0” state.

There is no address wrapping when using the Sequential Program Mode. Therefore, when the last byte (07FFFFh) of the memory array has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register back to the logical “0” state. In addition, the Sequential Program mode will not automatically skip over protected sectors; therefore, once the highest unprotected memory location in a programming sequence has been programmed, the device will automatically exit the Sequential Program mode and reset the WEL bit in the Status Register. For example, if Sector 1 was protected and Sector 0 was currently being programmed, once the last byte of Sector 0 was programmed, the Sequential Program mode would automatically end. To continue programming with Sector 2, the Sequential Program mode would have to be restarted by supplying the ADh or AFh opcode, the three address bytes, and the first byte of Sector 2 to program.

While the device is programming a byte, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled at the end of each program cycle rather than waiting the tBPtime to determine if the byte has finished programming before starting the next Sequential Program mode cycle.

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Figure 8-3. Sequential Program Mode – Status Register Polling

Seqeuntial Program Mode

Command

Opcode

Note: Each transition shown for SI represents one byte (8 bits)

A23-16 A15-8 A7-0 05hData

First Address to Program

HIGH-IMPEDANCE

Status Register Read

Command

STATUS REGISTER

Seqeuntial Program Mode

Command

Opcode

DATA

Seqeuntial Program Mode

Data 05h 04h

STATUS REGISTER

DATA

Figure 8-4. Sequential Program Mode – Waiting Maximum Byte Program Time

Seqeuntial Program Mode

Command

Opcode

Note: Each transition shown for SI represents one byte (8 bits)

A23-16 A15-8 A7-0 Data

First Address to Program

HIGH-IMPEDANCE

Seqeuntial Program Mode

Command

Opcode

Data 04h

Seqeuntial Program Mode

Command

Opcode

Data 05h

Data

Write Disable

Command

STATUS REGISTER

Write Disable

Command

DATA

8.3 Block Erase

A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally selftimed and should take place in a time of t

BLKE

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed.

AT25DF041A

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AT25DF041A

If the address specified by A23 - A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 18 through 15) at one time. Therefore, in order to erase a larger block that may span more than one sector, all of the sectors in the span must be in the unprotected state. If one of the physical sectors within the span is in the protected state, then the device will ignore the Block Erase command and will return to the idle state once the CS pin is deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected.

While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.

CS pin has been deasserted. In addition, with the larger Block Erase

time to determine if the device has finished erasing. At

BLKE

Figure 8-5. Block Erase

SCK

CCCCCCCC

MSB MSB

HIGH-IMPEDANCE

2310

OPCODE

675410119812 3129 3027 2826

ADDRESS BITS A23-A0

AAAA AAAA A A A A

3668E–DFLASH–11/2012

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