Rainbow Electronics AT25640A User Manual

Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)

– Data Sheet Describes Mode 0 Operation

• Medium-voltage and Standard-voltage Operation

– 5.0 (V
– 2.7 (V

• 5.0 MHz Clock Rate (5V)

• 32-byte Page Mode

• Block Write Protection

– Protect 1/4, 1/2, or Entire Array

• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software

Data Protection

• Self-timed Write Cycle (2 ms [5V] typical)

• High Reliability

– Endurance: One Million Write Cycles
– Data Retention: 100 Years

• 8-lead PDIP and 8-lead JEDEC SOIC Packages

= 4.5V to 5.5V)

CC

= 2.7V to 5.5V)

CC

SPI Serial
Automotive
EEPROMs
8K (1024 x 8)

Description

The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial
electrically-erasable programmable read-only memory (EEPROM) organized as
1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many
automotive applications where low-power and low-voltage operation are essential.
The AT25080A/160A/320A/640A is available in space saving 8-lead PDIP and 8-lead
JEDEC SOIC packages.

The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS
accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely self­timed, and no separate erase cycle is required before write.

Block write protection is enabled by programming the status register with one of four blocks
of write protection. Separate program enable and program disable instructions are provided
for additional data protection. Hardware data protection is provided via the WP
against inadvertent write attempts to the status register. The HOLD
pend any serial communication without resetting the serial sequence.

Table 1. Pin Configuration

Pin Name Function

CS

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

Chip Select

CS
SO

WP

GND

pin may be used to sus-

8-lead PDIP

1
2

3

4

pin to protect

8

7
6
5

) and

VCC
HOLD

SCK
SI

16K (2048 x 8)
32K (4096 x 8)
64K (8192 x 8)

AT25080A
AT25160A
AT25320A
AT25640A

GND Ground

VCC Power Supply

WP

HOLD

NC No Connect

DC Don’t Connect

Write Protect

Suspends Serial Input

CS
SO

WP

GND

8-lead SOIC

1
2

3

4

VCC

8

HOLD

7

SCK

6

SI

5

3401C–SEEPR–8/04

1

Absolute Maximum Ratings*

Operating Temperature......................................−40°C to +125°C

Storage Temperature .........................................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground........................................ −1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

2

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

Tabl e 2 . Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Symbol Test Conditions Max Units Conditions

C

OUT

C

IN

Output Capacitance (SO) 8 pF V

Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV

OUT

IN

= 0V

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Tabl e 3 . DC Characteristics

(1)

Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

Supply Voltage 4.5 5.5 V

CC2

I

CC1

I

CC2

I

CC3

Standby Current VCC = 2.7V, CS = V

I

SB1

I

SB2

I

Input Leakage VIN = 0V to V

IL

I

OL

(1)

V

IL

(1)

V

IH

V

Output Low-voltage

OL1

V

OH1

Note: 1. VIL min and VIH max are reference only and are not tested.

Supply Voltage 2.7 5.5 V

Supply Current VCC = 5.0V at 5 MHz, SO = Open, Read 6.0 mA

Supply Current VCC = 5.0V at 1 MHz 3.0 mA

Supply Current VCC = 5.0V at 5 MHz, SO = Open,

7.0 mA

Read, Write

0.2 10.0

2.0 13.0

Standby Current VCC = 5.0V, CS = V

CC

Output Leakage V

= 0V to VCC −3.0 3.0 µA

IN

CC

CC

−3.0 µA

Input Low-voltage −0.6 VCC x 0.3 V

Input High-voltage VCC x 0.7 VCC + 0.5 V

= 3.0 mA 0.4 V

I

Output High-voltage IOH = −1.6 mA VCC − 0.8 V

2.7V ≤ V

≤ 5.5V

CC

OL

2. Worst case measured at 125°C

(2)

(2)

µA

µA

3401C–SEEPR–8/04

3

Tabl e 4 . AC Characteristics

Applicable over recommended operating range from T

= −40°C to +125°C, VCC = As Specified,

A

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

f

SCK

t

RI

t

FI

t

WH

t

WL

t

CS

t

CSS

t

CS Hold Time 4.5–5.5

CSH

t

Data In Setup Time 4.5–5.5

SU

SCK Clock Frequency 4.5–5.5

2.7–5.5

Input Rise Time 4.5–5.5

2.7–5.5

Input Fall Time 4.5–5.5

2.7–5.5

SCK High Time 4.5–5.5

2.7–5.5

SCK Low Time 4.5–5.5

2.7–5.5

CS High Time 4.5–5.5

2.7–5.5

CS Setup Time 4.5–5.5

2.7–5.5

2.7–5.5

2.7–5.5

0
0

80

133

80

133

150
250

150
250

150
250

50
50

5.0

3.0

2
2

2
2

ns

MHz

µs

µs

ns

ns

ns

ns

ns

t

H

t

Hold Setup Time 4.5–5.5

HD

t

CD

t

V

t

HO

t

LZ

t

HZ

t

DIS

t

WC

Endurance

Data In Hold Time 4.5–5.5

Hold Hold Time 4.5–5.5

Output Valid 4.5 - 5.5

Output Hold Time 4.5–5.5

Hold to Output Low Z 4.5–5.5

Hold to Output High Z 4.5–5.5

Output Disable Time 4.5–5.5

Write Cycle Time 4.5–5.5

(1)

5.0V, 25°C, Page Mode 1M Write Cycles

Note: 1. This parameter is characterized and is not 100% tested.

2.7–5.5

2.7–5.5

2.7 - 5.5

2.7–5.5

2.7–5.5

2.7–5.5

2.7–5.5

2.7–5.5

2.7–5.5

50
50

100
100

150
200

0
0

0
0

0
0

80

133

100
100

100
100

150
250

5
5

ns

ns

ns

ns

ns

ns

ns

ms

4

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

Serial Interface Description

MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the

AT25080A/160A/320A/640A always operates as a slave.
TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated

for data transmission (SO) and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS

received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the

AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance
state until the falling edge of CS
communication.

CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS
the device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.

HOLD: The HOLD
AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway,
HOLD

can be used to pause the serial communication with the master device without resetting
the serial sequence. To pause, the HOLD
To resume serial communication, the HOLD
may still toggle during HOLD
high impedance state.

pin is used in conjunction with the CS pin to select the

). Inputs to the SI pin will be ignored while the SO pin is in the

is detected again. This will reinitialize the serial

pin must be brought low while the SCK pin is low.

pin is brought high while the SCK pin is low (SCK

going low, the first byte will be

pin is low. When

WRITE PROTECT: The write protect pin (WP
held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta­tus register are inhibited. WP
register. If the internal write cycle has already been initiated, WP
on any write operation to the status register. The WP
bit in the status register is "0". This will allow the user to install the AT25080A/
160A/320A/640A in a system with the WP
status register. All WP

pin functions are enabled when the WPEN bit is set to “1”.

going low while CS is still low will interrupt a write to the status

) will allow normal read/write operations when

going low will have no effect

pin function is blocked when the WPEN

pin tied to ground and still be able to write to the

3401C–SEEPR–8/04

5

Figure 2. SPI Serial Interface

AT25080A/160A/320A/640A

6

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

Functional Description

The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.

The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions
and their operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.

Tabl e 5 . Instruction Set for the AT25080A/160A/320A/640A

Instruction Name Instruction Format Operation

WREN 0000 X110 Set Write Enable Latch

WRDI 0000 X100 Reset Write Enable Latch

RDSR 0000 X101 Read Status Register

WRSR 0000 X001 Write Status Register

READ 0000 X011 Read Data from Memory Array

WRITE 0000 X010 Write Data to Memory Array

WRITE ENABLE (WREN): The device will power-up in the write disable state when V

CC

is
applied. All programming instructions must therefore be preceded by a Write Enable
instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the sta­tus of the WP

pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be deter­mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction.

Tabl e 6 . Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Tabl e 7 . Read Status Register Bit Definition

Bit Definition

Bit 0 (RDY

Bit 1 (WEN) Bit 1= 0 indicates the device is not write-enabled. Bit 1 = 1 indicates the device is

Bit 2 (BP0) See Table 8 on page 8.

Bit 3 (BP1) See Table 8 on page 8.

Bits 4–6 are “0”s when device is not in an internal write cycle.

Bit 7 (WPEN) See Table 9 on page 8.

Bits 0–7 are “1”s during an internal write cycle.

) Bit 0 = 0 (RDY) indicates the device is ready. Bit 0 = 1 indicates the write cycle is in

progress.

write-enabled.

3401C–SEEPR–8/04

7

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of

four levels of protection. The AT25080A/160A/320A/640A is divided into four array segments.
One-quarter, one-half, or all of the memory segments can be protected. Any of the data within
any selected segment will therefore be read-only. The block write protection levels and corre­sponding status register control bits are shown in Table 8.

The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, t

, RDSR).

WC

Tabl e 8 . Block Write Protect Bits

Status

Register Bits Array Addresses Protected

Level

0 0 0 None None None None

1(1/4)

2(1/2)

3(All)

The WRSR instruction also allows the user to enable or disable the write protect (WP

BP1 BP0 AT25080A AT25160A AT25320A AT25640A

01

10

11

0300

−03FF

0200

−03FF

0000

−03FF

0600

−07FF

0400

−07FF

0000

−07FF

0C00

−0FFF

0800

−0FFF

0000

−0FFF

1800

−1FFF

1000

−1FFF

0000

−1FFF

) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP
either the WP

pin is low and the WPEN bit is “1”. Hardware write protection is disabled when

pin is high or the WPEN bit is “0”. When the device is hardware write-protected,
writes to the status register, including the block protect bits and the WPEN bit, and the block­protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory that are not block-protected.

NOTE: When the WPEN bit is hardware write-protected, it cannot be changed back to “0” as
long as the WP

pin is held low.

Tabl e 9 . WPEN Operation

WPEN WP WEN

Protected

Blocks

Unprotected

Blocks

Status

Register

0 X 0 Protected Protected Protected

0 X 1 Protected Writable Writable

1 Low 0 Protected Protected Protected

1 Low 1 Protected Writable Protected

X High 0 Protected Protected Protected

X High 1 Protected Writable Writable

8

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the serial output

(SO) pin requires the following sequence. After the CS
READ op-code is transmitted via the SI line followed by the byte address to be read (A15–A0;
see Table 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued
since the byte address is automatically incremented and data will continue to be shifted out.
When the highest address is reached, the address counter will roll over to the lowest address,
allowing the entire memory to be read in one continuous read cycle.

WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two sep­arate instructions must be executed. First, the device
instruction. Then a write (WRITE) instruction may be executed. Also, the address of the mem­ory location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands will
be ignored except the RDSR instruction.

line is pulled low to select a device, the

must be write-enabled

via the WREN

A write instruction requires the following sequence. After the CS

line is pulled low to select the
device, the WRITE op-code is trans‘mitted via the SI line followed by the byte address (A15–
A0) and the data (D7–D0) to be programmed (see Table 10). Programming will start after the
CS

pin is brought high. The low-to-high transition of the CS pin must occur during the SCK

low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register

(RDSR) instruction. If Bit 0 = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.

The AT25080A/160A/320A/640A is capable of a 32-byte page write operation. After each byte
of data is received, the five low-order address bits are internally incremented by one; the high­order bits of the address will remain constant. If more than 32 bytes of data are transmitted,
the address counter will roll over and the previously written data will be overwritten. The
AT25080A/160A/320A/640A is automatically returned to the write disable state at the comple­tion of a write cycle.

NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction
and will return to the standby state when CS

is brought high. A new CS falling edge is required

to reinitiate the serial communication.

Tabl e 1 0. Address Key

Address AT25080A AT25160A AT25320A AT25640A

A

N

Don’t

Care Bits

A

9–A0

A

15–A10

A

10–A0

A

15–A11

A

11–A0

A

15–A12

A

12–A0

A

15–A13

3401C–SEEPR–8/04

9

Timing Diagrams

Figure 3. Synchronous Data Timing (for Mode 0)

V

IH

CS

V

IL

t

CSS

V

SO

IH

V

IL

t

SU

V

IH

SI

V

IL

V

OH

HI-Z

V

OL

VAL ID IN

SCK

Figure 4. WREN Timing

t

CS

t

CSH

t

WH

t

H

t

WL

t

V

t

HO

t

DIS

HI-Z

Figure 5. WRDI Timing

10

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

Figure 6. RDSR Timing

CS

AT25080A/160A/320A/640A

SCK

SI

SO

HIGH IMPEDANCE

Figure 7. WRSR Timing

CS

00112233445566778 910111213 14 15

SCK

01234567891011121314

INSTRUCTION

DATA OUT

76543210

MSB

15

SO

SI

DATA IN

INSTRUCTION

HIGH IMPEDANCE

3401C–SEEPR–8/04

11

Figure 8. READ Timing

CS

0

SCK

SI

INSTRUCTION

1

2

3

445566778910

11 20 21 22 23 24 25 26 27 28 29 30

31

BYTE ADDRESS

15 14 13

...

2

3

0

1

SO

HIGH IMPEDANCE

Figure 9. WRITE Timing

CS

0

SCK

SI

SO

Figure 10. HOLD

HIGH IMPEDANCE

INSTRUCTION

Timing

DATA OUT

0

1

2

3

MSB

1

2

3

445566778 910

11 20 21 22 23 24 25 26 27 28 29 30 31

BYTE ADDRESS DATA IN

15 14 13

...

2

3

0

1

2

3

0

1

CS

SCK

HOLD

SO

12

t

CD

t

HD

t

HZ

AT25080A/160A/320A/640A

t

CD

t

HD

t

LZ

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

AT25080A Ordering Information

Ordering Code Package Operation Range

AT25080A-10PA-5.0C
AT25080AN-10SA-5.0C

AT25080A-10PA-2.7C
AT25080AN-10SA-2.7C

8P3
8S1

8P3
8S1

Automotive

(−40°C to 125°C)

Automotive

(−40°C to 125°C)

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

−5.0 Standard Device (4.5V to 5.5V)

−2.7 Low Voltage (2.7V to 5.5V)

3401C–SEEPR–8/04

13

AT25160A Ordering Information

Ordering Code Package Operation Range

AT25160A-10PA-5.0C
AT25160AN-10SA-5.0C

AT25160A-10PA-2.7C
AT25160AN-10SA-2.7C

8P3
8S1

8P3
8S1

Automotive

(−40°C to 125°C)

Automotive

(−40°C to 125°C)

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

−5.0 Standard Device (4.5V to 5.5V)

−2.7 Low Voltage (2.7V to 5.5V)

14

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

AT25320A Ordering Information

Ordering Code Package Operation Range

AT25320A-10PA-5.0C
AT25320AN-10SA-5.0C

AT25320A-10PA-2.7C
AT25320AN-10SA-2.7C

8P3
8S1

8P3
8S1

Automotive

(−40°C to 125°C)

Automotive

(−40°C to 125°C)

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

−5.0 Standard Device (4.5V to 5.5V)

−2.7 Low Voltage (2.7V to 5.5V)

3401C–SEEPR–8/04

15

AT25640A Ordering Information

Ordering Code Package Operation Range

AT25640A-10PA-5.0C
AT25640AN-10SA-5.0C

AT25640A-10PA-2.7C
AT25640AN-10SA-2.7C

8P3
8S1

8P3
8S1

Automotive

(−40°C to 125°C)

Automotive

(−40°C to 125°C)

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

Options

−5.0 Standard Device (4.5V to 5.5V)

−2.7 Low Voltage (2.7V to 5.5V)

16

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

Packaging Information

8P3 – PDIP

AT25080A/160A/320A/640A

D1

b3

4 PLCS

Top View

D

e

Side View

1

E

E1

N

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

b

b2

A2 A

SYMBOL

A
A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014
D 0.355 0.365 0.400 3

L

D1 0.005
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2

MIN

NOM

–

MAX

–

0.210 2

–

–

3

NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicu

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

3401C–SEEPR–8/04

8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

lar to datum.

DRAWING NO.

8P3

01/09/02

REV.

B

17

8S1 – JEDEC SOIC

C

1

E

N

∅

E1

L

Top View

End View

e

D

Side View

B

A

SYMBOL

A1

A 1.35 – 1.75

A1 0.10 – 0.25

b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0° – 8°

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

18

Note:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906

R

TITLE

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)

AT25080A/160A/320A/640A

DRAWING NO.

8S1 B

3401C–SEEPR–8/04

10/7/03

REV.

Atmel Corporation Atmel Operations

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

Regional Headquarters

Europe

Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: [phone]
Fax: [phone]

Asia

Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: [phone]
Fax: [phone]

Japan

9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: [phone]
Fax: [phone]

Memory

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

Microcontrollers

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: [phone]
Fax: [phone]

ASIC/ASSP/Smart Cards

Zone Industrielle
13106 Rousset Cedex, France
Tel: [phone]
Fax: [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: [phone]
Fax: [phone]

Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: [phone]
Fax: [phone]

RF/Automotive

Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: [phone]
Fax: [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: [phone]
Fax: [phone]

Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom

Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: [phone]
Fax: [phone]

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
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