Rainbow Electronics AT25640A User Manual

Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)

– Data Sheet Describes Mode 0 Operation

• Medium-voltage and Standard-voltage Operation

– 5.0 (V – 2.7 (V

• 5.0 MHz Clock Rate (5V)

• 32-byte Page Mode

• Block Write Protection

– Protect 1/4, 1/2, or Entire Array

• Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software

Data Protection

• Self-timed Write Cycle (2 ms [5V] typical)

• High Reliability

– Endurance: One Million Write Cycles – Data Retention: 100 Years

• 8-lead PDIP and 8-lead JEDEC SOIC Packages

= 4.5V to 5.5V)

= 2.7V to 5.5V)

SPI Serial Automotive EEPROMs 8K (1024 x 8)

Description

The AT25080A/160A/320A/640A provides 8192/16384/32768/65536 bits of serial electrically-erasable programmable read-only memory (EEPROM) organized as 1024/2048/4096/8192 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT25080A/160A/320A/640A is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages.

The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS accessed via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely selftimed, and no separate erase cycle is required before write.

Block write protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP against inadvertent write attempts to the status register. The HOLD pend any serial communication without resetting the serial sequence.

Table 1. Pin Configuration

Pin Name Function

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

Chip Select

CS SO

GND

pin may be used to sus-

8-lead PDIP

1 2

pin to protect

7 6 5

) and

VCC HOLD

SCK SI

16K (2048 x 8) 32K (4096 x 8) 64K (8192 x 8)

AT25080A AT25160A AT25320A AT25640A

GND Ground

VCC Power Supply

HOLD

NC No Connect

DC Don’t Connect

Write Protect

Suspends Serial Input

CS SO

GND

8-lead SOIC

1 2

VCC

HOLD

SCK

3401C–SEEPR–8/04

Absolute Maximum Ratings*

Operating Temperature......................................−40°C to +125°C

Storage Temperature .........................................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground........................................ −1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

Tabl e 2 . Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Symbol Test Conditions Max Units Conditions

OUT

Output Capacitance (SO) 8 pF V

Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV

OUT

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

Tabl e 3 . DC Characteristics

(1)

Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V

Symbol Parameter Test Condition Min Typ Max Units

CC1

Supply Voltage 4.5 5.5 V

CC2

CC1

CC2

CC3

Standby Current VCC = 2.7V, CS = V

SB1

SB2

Input Leakage VIN = 0V to V

(1)

Output Low-voltage

OL1

OH1

Note: 1. VIL min and VIH max are reference only and are not tested.

Supply Voltage 2.7 5.5 V

Supply Current VCC = 5.0V at 5 MHz, SO = Open, Read 6.0 mA

Supply Current VCC = 5.0V at 1 MHz 3.0 mA

Supply Current VCC = 5.0V at 5 MHz, SO = Open,

7.0 mA

Read, Write

0.2 10.0

2.0 13.0

Standby Current VCC = 5.0V, CS = V

Output Leakage V

= 0V to VCC −3.0 3.0 µA

−3.0 µA

Input Low-voltage −0.6 VCC x 0.3 V

Input High-voltage VCC x 0.7 VCC + 0.5 V

= 3.0 mA 0.4 V

Output High-voltage IOH = −1.6 mA VCC − 0.8 V

2.7V ≤ V

≤ 5.5V

2. Worst case measured at 125°C

(2)

µA

3401C–SEEPR–8/04

Tabl e 4 . AC Characteristics

Applicable over recommended operating range from T

= −40°C to +125°C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

SCK

CSS

CS Hold Time 4.5–5.5

CSH

Data In Setup Time 4.5–5.5

SCK Clock Frequency 4.5–5.5

2.7–5.5

Input Rise Time 4.5–5.5

2.7–5.5

Input Fall Time 4.5–5.5

2.7–5.5

SCK High Time 4.5–5.5

2.7–5.5

SCK Low Time 4.5–5.5

2.7–5.5

CS High Time 4.5–5.5

2.7–5.5

CS Setup Time 4.5–5.5

2.7–5.5

0 0

133

150 250

50 50

5.0

3.0

2 2

MHz

µs

Hold Setup Time 4.5–5.5

DIS

Endurance

Data In Hold Time 4.5–5.5

Hold Hold Time 4.5–5.5

Output Valid 4.5 - 5.5

Output Hold Time 4.5–5.5

Hold to Output Low Z 4.5–5.5

Hold to Output High Z 4.5–5.5

Output Disable Time 4.5–5.5

Write Cycle Time 4.5–5.5

(1)

5.0V, 25°C, Page Mode 1M Write Cycles

Note: 1. This parameter is characterized and is not 100% tested.

2.7–5.5

2.7 - 5.5

2.7–5.5

50 50

100 100

150 200

0 0

133

100 100

150 250

5 5

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

AT25080A/160A/320A/640A

Serial Interface Description

MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the

AT25080A/160A/320A/640A always operates as a slave. TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated

for data transmission (SO) and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS

received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the

AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS communication.

CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.

HOLD: The HOLD AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway, HOLD

can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD To resume serial communication, the HOLD may still toggle during HOLD high impedance state.

pin is used in conjunction with the CS pin to select the

). Inputs to the SI pin will be ignored while the SO pin is in the

is detected again. This will reinitialize the serial

pin must be brought low while the SCK pin is low.

pin is brought high while the SCK pin is low (SCK

going low, the first byte will be

pin is low. When

WRITE PROTECT: The write protect pin (WP held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP register. If the internal write cycle has already been initiated, WP on any write operation to the status register. The WP bit in the status register is "0". This will allow the user to install the AT25080A/ 160A/320A/640A in a system with the WP status register. All WP

pin functions are enabled when the WPEN bit is set to “1”.

going low while CS is still low will interrupt a write to the status

) will allow normal read/write operations when

going low will have no effect

pin function is blocked when the WPEN

pin tied to ground and still be able to write to the

3401C–SEEPR–8/04

Figure 2. SPI Serial Interface

AT25080A/160A/320A/640A

3401C–SEEPR–8/04

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