Rainbow Electronics AT25256A User Manual

Features

• Serial Peripheral Interf ace (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)

• Medium-v olt age and Standard-voltage Operation

– 5.0 (V
– 2.7 (V

• 3 MHz Clock Rate (5V)

• 64-byte Page Mode and Byte Write Operation

• Block Write Pr otection

– Protect 1/4, 1/2, or Entire Array

• Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

• Self-timed Write Cycle (5 ms Typica l)

• High-reliability

– Endurance: 100,000 Write Cycles
– Data Retention: >200 Years

• 8-lead PDIP, 8- lead JEDEC SOIC and 8-lead EIAJ SOIC Packages

= 4.5V to 5.5V)

CC

= 2.7V to 5.5V)

CC

SPI Serial
Automotive
EEPROMs

128K (16,384 x 8)

Description

The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro­grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commerc ial applications
where low-power and low-vol tage operation are essential. The devices are available in
space saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC (AT25256A)
packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V
(2.7V to 5.5V) versions.

Pin Configurations

CS
SO

WP

GND

CS
SO

WP

GND

8-lead PDIP

1

8

2

7

3

6

4

5

8-lead SOIC

1
2
3
4

8
7
6
5

VCC
HOLD
SCK
SI

VCC
HOLD
SCK
SI

Pin Name Function

CS
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP
HOLD
NC No Connect
DC Don't Connect

Chip Se lec t

Write Protect
Suspends Serial Input

256K (32,768 x 8)

AT25128A
AT25256A

Preliminary

Rev. 3404A–SEEPR–10/03

1

The AT25128A/256A is enabled through the Ch ip Sele ct pin (CS) an d accessed via a 3-wire interface consisting of Seria l
Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with top ¼ , top ½ or entire array of write protec­tion. Separate program enable and program disable instructions are provided for additional data protection. Hardware data
protection is provided via the WP

pin to protect against inadvertent write attempts to the status register. The HOLD pin may

be used to suspend any serial communication without resetting the serial sequence.

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature............................ ......... -65°C to +150°C

Voltage on Any Pin

with Resp e c t to Gr o und . .. ... ....... .. ... ....... ... .. .......-1.0V to +7.0 V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

*NOTICE: Str esses beyond th ose listed under “Absolute Max i-

mum Ratings” ma y cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi­tions beyond those indicated in the operational sec­tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.

Block Diagram

16384/32768 x 8

2

AT25128A/256A [Preliminary]

3404A–SEEPR–10/03

AT25128A/256A [Preliminary]

Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).

Symbol T est Conditions Max Units Conditions

C

OUT

C

IN

Output Capacitance (SO) 8 pF V
Input Capacit ance (CS, SCK, SI, WP, HOLD)6pFV

OUT

IN

= 0V

= 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.5V

Symbol Paramet er Test Condition Min Typ Max Units

V

CC1

V

CC2

I

CC1

I

CC2

I

SB1

I

SB2

I

IL

I

OL

(1)

V

IL

(1)

V

IH

V

OL1

V

OH1

Note: 1. V

Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read 2.0 3.0 mA

= 5.0V at 2 MHz,

V

Supply Current

CC

SO = Open, Read, Write
Standby Current VCC = 2.7V, CS = V
Standby Current VCC = 5.0V, CS = V
Input Leakage VIN = 0V to V

CC

CC

CC

-3.0 3.0 µA

3.0 5.0 mA

0.2 2.0 µA

2.0 5.0 µA

Output Leakage VIN = 0V to VCC -3.0 3.0 µA
Input Low-voltage -1.0 VCC x 0.3 V
Input High-v oltage VCC x 0.7 VCC + 0.5 V
Outp u t Lo w -voltag e
Output High-voltage IOH = -1.6 mA VCC - 0.8 V

4.5 ≤ V

and VIH max are reference only and are not tested.

IL

≤ 5.5V

CC

I

= 3.0 mA 0.4 V

OL

3404A–SEEPR–10/03

3

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Voltage Min Max Units

f

SCK

t

RI

t

FI

t

WH

t

WL

t

CS

t

CSS

t

CSH

t

SU

t

H

t

HD

SCK Clock Frequency

Input Rise Time

Input Fall Time

SCK High Time

SCK Low Time

CS High Time

CS Setup Time

CS Hold Time

Data In Setup Time

Data In Hold Time

Hold Setup Time

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

0
0

150
200

150
200

250
250

100
250

150
250

30
50

50
50

100
100

3.0

2.1
2

2
2

2

MHz

µs

µs

ns

ns

ns

ns

ns

ns

ns

ns

t

CD

t

V

t

HO

t

LZ

t

HZ

t

DIS

t

WC

Endurance

Hold Hold Time

Output Valid

Output Hold Time

Hold to Output Low Z

Hold to Output High Z

Output Disable Time

Write Cycle Time

(1)

5.0V, 25°C, Page Mode 100K Write Cycles

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

4.5 - 5.5

2.7 - 5.5

200
300

0
0

0
0

0
0

Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.

4

AT25128A/256A [Preliminary]

150
200

100
200

100
200

200
250

5

10

ns

ns

ns

ns

ns

ns

ms

3404A–SEEPR–10/03

AT25128A/256A [Preliminary]

Serial Interface Description

MASTER: The device that generates the serial clock.
SLAVE: Be cause the Se rial Clock pi n (SCK) is alw ays an i nput, the AT2 5128A /256A

always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for

data transmission (SO) and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After th e device is selected with CS

be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an inv alid op-co de is rec eived, no data will be shifte d into the

AT251 28A /256 A, and th e ser ial out put pin ( SO) wi ll rem ain in a high im peda nce sta te
until the falling edge of CS
communication.

CHIP SELECT: The AT25128A/256A is selected when the CS
device is not selecte d, data wil l not be accepted via the S I pin, and the serial output pi n
(SO) will remain in a high impedance state.

HOLD: The HOLD
AT25128A/ 256A. Whe n the device is selected an d a serial seque nce is underway ,
HOLD

can be used to pause the serial communication with the master device without
resett ing th e s erial sequ en ce. To pa use, th e HOLD
SCK pin is low. To resume serial communication, the HOLD
SCK pin is low (SCK ma y still toggle duri ng HOLD
while the SO pin is in the high impedance state.

pin is used in conjunction with the CS pin to s elect th e

is detecte d again. This will rein itialize the seri al

pin mu st be brou gh t low whil e the

). Inputs to the SI pin will be i gnored

going low, the first byte will

pin is low. When the

pin is brought high while the

WRITE PROTECT: The write pro tect pin (WP
when he ld hi gh. Wh en the W P
tions to the status register are inhibited. WP
write to the status register. If the internal write cycle has already been initiated, WP
going lo w will ha ve n o effe ct on any wri te o perat ion to the status r egis ter . The WP pi n
funct ion is b loc ke d w hen th e WP EN bi t in the st atu s reg is ter is “ 0” . Thi s wi ll all ow th e
user to install the AT25128A/256A in a system with the WP
able to write to the status register. All WP
is set to “1”.

pin is brought low and WPEN bit is “1”, all write opera-

) will allo w no rmal read /wr ite o perat io ns

going low while CS is still low will interrupt a

pin tied to ground and still be

pin functions are enabled when the WPEN bit

3404A–SEEPR–10/03

5

SPI Serial Interface

AT25128A/256A

Functional Description

6

AT25128A/256A [Preliminary]

The AT25128A/256A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.

The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS

Table 1. Instruction Set for the AT25128A/256A

Instruction Name Instruction Format Operation

WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Registe r
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array

transition..

3404A–SEEPR–10/03