• Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Sof tware Data Protection
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Enduranc e: One Million Write Cycles
– Data Retention: 100 Years
• 8-pin PDIP and 8-lead JEDEC SOIC Package
= 4.5V to 5.5V)
CC
= 2.7V to 5.5V)
CC
SPI Serial
Automotive
EEPROMs
1K (128 x 8)
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many automotive applications where lowpower and low vo ltage opera tio n are e sse nti al. Th e AT25010/020/0 40 is avail able in
space saving 8-pin PDIP and 8-lead JEDEC SOIC packages.
The A T25010/020/040 is enabled through the Chip Select pin (CS
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial C lock (SC K). All programm ing cy cle s are c omp letely self-tim ed, and no sep arate ERASE cycle is required before WRITE.
BLOCK WRIT E protectio n is enabled by programmi ng the statu s registe r with on e of
four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection i s provided
via the WP
used to suspend any serial communication without resetting the serial sequence.
pin to protect against inadvertent write attempts. The HOLD pin may be
) and accessed via a
Pin Configurations
CS
SO
WP
8-pin PDIP
1
2
3
4
8
VCC
7
HOLD
6
SCK
5
SI
Pin NameFunction
CS
SCKSerial Data Clock
SISerial Data Input
SOSerial Data Output
Chip Select
GND
2K (256 x 8)
4K (512 x 8)
AT25010
AT25020
AT25040
SPI, 1K Serial
2
E
PROM
GNDGround
VCCPower Supply
WP
HOLD
Write Protect
Suspends Serial Input
CS
SO
WP
GND
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Rev. 3259C–SEEPR–06/03
1
Absolute Maximum Ratings*
Operatin g Temperature....... .. ........................ -55°C to + 1 25° C
Storage Temperature.................................... -65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ....................................-1.0V to + 7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratin gs” may cause permanent damage to the devi ce . This is a stres s rati ng only and
functional operation of the de vice at these or any
other conditions beyond those indicated in the
operational sections of this specif ication is not
implied. Expos ure to absolute maximum rat ing
conditions for ext ended periods may affect
device reliability.
2
AT25010/020/040
3259C–SEEPR–06/03
AT25010/020/040
Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Note:1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TA = -40°C to +125°C, VCC = +2.7V to +5.5V.
SymbolParameterTe st Condi ti onMinMaxUnits
V
CC1
V
CC2
I
CC1
I
CC2
I
SB1
I
SB2
I
IL
I
OL
(2)
V
IL
(2)
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Notes: 1. This parameter is preliminary and Atmel may change the specifications upon further characterization.
Supply Voltage2.75.5V
Supply Voltage4.55.5V
Supply CurrentVCC = 5.0V at 1 MHz, SO = Open, Read3.0mA
= 5.0V at 2 MHz, SO = Open,
V
Supply Current
CC
Read, Write
Standby CurrentVCC = 2.7VCS = V
Standby CurrentVCC = 5.0VCS = V
CC
CC
6.0mA
5µA
10µA
Input LeakageVIN = 0V to VCC -0.63.0µA
Output LeakageVIN = 0V to VCC -0.63.0µA
Input Low Voltage-0.6V
x 0.3V
CC
Input High VoltageVCC x 0.7VCC + 0.5V
Outp u t Lo w Voltag e
Output High VoltageIOH = -1.0 mAVCC - 0.8V
4.5V ≤ V
≤ 5.5V
CC
Outp u t Lo w Voltag e
Output High VoltageIOH = -100 µAVCC - 0.2V
2.7V ≤ V
2. V
min and VIH max are reference onl y and are not tested.
IL
≤ 5.5V
CC
= 2.0 mA0.4V
I
OL
I
= 0.15 mA0.2V
OL
3259C–SEEPR–06/03
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
SymbolParameterVoltageMinMaxUnits
f
SCK
t
RI
t
FI
t
WH
t
WL
t
CS
t
CSS
t
CSH
t
SU
t
H
t
HD
t
CD
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
CS Setup Time
CS Hold0 Time
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
0
0
133
200
133
200
250
250
250
250
250
250
50
50
50
100
100
100
200
200
3.0
2.1
2
2
2
2
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
V
t
HO
t
LZ
t
HZ
t
DIS
t
WC
Endurance
Output Valid
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Write Cycle Time
(1)
5.0V, 25°C, Page M o de1MWri t e Cycl es
Note:1. This parameter is characterized and is not 100% tested.
4
AT25010/020/040
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
0
0
0
0
0
0
133
200
100
100
100
100
250
500
5
10
ns
ns
ns
ns
ns
ms
3259C–SEEPR–06/03
AT25010/020/040
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clo ck pin (SC K) is always an inp ut, the AT25 010/0 20/040
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS
received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010/020/ 040, and the seria l output pin (SO) will remain i n a high impedance state
until the falling edge of CS
communication.
CHIP SELECT: The AT25010/020/040 is selected when the CS
device is not selecte d, data wil l not be accepted via the S I pin, and the serial output pi n
(SO) will remain in a high impedance state.
HOLD: The HOLD
AT25010/020/040. When the device is selected and a serial sequence is underway,
HOLD
can be used to paus e the serial communication with the master device without
resett ing th e s erial sequ en ce. To pa use, th e HOLD
SCK pin is low. To resume serial communication, the HOLD
SCK pin is low (SCK ma y still toggle duri ng HOLD
while the SO pin is in the high impedance state.
pin is used in conjunction with the CS pin to s elect th e
is detecte d again. This will rein itialize the seri al
going l o w , th e f ir s t byte will be
pin is low. When the
pin mu st be brou gh t low whil e the
pin is brought high while the
). Inputs to the SI pin will be i gnored
WRITE PROTECT: The write pro tect pin (WP
when held high. When the WP
going low while CS is still low will interrupt a write to the AT25010/020/040. If the
WP
internal write cycle has already been initiated, WP
write operation.
pin is brought low, all write operations are inhibited.
) will allo w no rmal read /wr ite o perat io ns
going low will have no effe ct on any
3259C–SEEPR–06/03
5
SPI Serial Interface
6
AT25010/020/040
3259C–SEEPR–06/03
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