Rainbow Electronics AT24C64 User Manual
Features
• Low-Voltage and Standard-Voltage Operation
–2.7(V
–1.8(V
• Low-Power Devices (I
• Internally Organized 4096 x 8, 8192 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
• Write Protect Pin for Hardware Data Protection
• 32-Byte Page Write Mode (Partial Page Writes Allowed)
• Self-Timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,
and 8-pin TSSOP Packages
=2.7Vto5.5V)
CC
=1.8Vto5.5V)
CC
=2 µA at 5.5V) Available
SB
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.
Pin Configurations
A0
A1
A2
8-Pin TSSOP
1
2
3
4
8
VCC
7
WP
6
SCL
5
SDA
Pin Name Function
A0 - A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
GND
AT24C32
AT24C64
2-Wire, 32K
Serial E
2
PROM
A0
A1
A2
GND
8-Pin PDIP
1
2
3
4
8-Pin SOIC
1
8
VCC
7
WP
6
SCL
5
SDA
A0
A1
A2
GND
2
3
4
VCC
8
WP
7
SCL
6
SDA
5
Rev. 0336I–SEEPR–07/02
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°Cto+125°C
Storage Temperature ..................................... -65°Cto+150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current ........................................................ 5.0 mA
Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
2
AT24C32/64
0336I–SEEPR–07/02
AT24C32/64
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to V
(8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to
GND.
, all write operations to the upper quandrant
CC
Memory Organization AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.
2,A1
,andA
0
0336I–SEEPR–07/02
3
Pin Capacitance
(1)
Applicable over recommended operating range from TA=25°C,f=1.0MHz,VCC= +1.8V.
Symbol Test Condition Max Units Conditions
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
I/O
=0V
Input Capacitance (A0,A1,A2,SCL) 6 pF VIN=0V
Note: 1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI=-40°Cto+85°C, VCC= +1.8V to +5.5V, TAC=0°Cto+70°C,
V
= +1.8V to +5.5V (unless otherwise noted).
CC
Symbol Parameter Test Condition Min Typ Max Units
V
V
V
V
I
I
I
I
I
I
CC1
CC2
CC3
CC4
CC1
CC2
SB1
SB2
SB3
SB4
Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC= 5.0V READ at 100 kHz 0.4 1.0 mA
Supply Current VCC= 5.0V WRITE at 100 kHz 2.0 3.0 mA
V
Standby Current
(1.8V option)
Standby Current
(2.5V option)
Standby Current
(2.7V option)
Standby Current
(5V option)
=1.8V
CC
=5.5V 2.0
V
CC
V
=2.5V
CC
V
=5.5V 2.0
CC
V
=2.7V
CC
V
=5.5V 2.0
CC
V
= 4.5 - 5.5V VIN=VCCor V
CC
V
IN=VCC
V
IN=VCC
V
IN=VCC
or V
or V
or V
SS
SS
SS
SS
20 35 µA
0.1 µA
0.5 µA
0.5 µA
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note: 1. V
4
AT24C32/64
Input Leakage
Current
Output Leakage
Current
Input Low Level
Input High Level
(1)
(1)
V
IN=VCC
V
OUT=VCC
or V
or V
SS
SS
0.10 3.0 µA
0.05 3.0 µA
-0.6 VCCx0.3 V
VCCx0.7 VCC+0.5 V
Output Low Level VCC=3.0V IOL=2.1mA 0.4 V
Output Low Level VCC=1.8V IOL=0.15mA 0.2 V
min and VIHmax are reference only and are not tested.
IL
0336I–SEEPR–07/02
AT24C32/64
AC Characteristics
Applicable over recommended operating range from TA=-40°Cto+85°C, VCC= +1.8V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
1.8-volt 2.7-, 2.5-volt 5.0-volt
Symbol Parameter
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 100 100 400 kHz
Clock Pulse Width Low 4.7 4.7 1.2 µs
Clock Pulse Width High 4.0 4.0 0.6 µs
Noise Suppression Time
(1)
Clock Low to Data Out Valid 0.1 4.5 0.1 4.5 0.1 0.9 µs
Time the bus must be free
before a new transmission can start
(1)
Start Hold Time 4.0 4.0 0.6 µs
Start Set-up Time 4.7 4.7 0.6 µs
Data In Hold Time 0 0 0 µs
Data In Set-up Time 200 200 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 4.7 4.7 0.6 µs
Data Out Hold Time 100 100 50 ns
WriteCycleTime 20 10 10 ms
(1)
5.0V, 25°C, Page Mode 1M 1M 1M
Note: 1. This parameter is characterized and is not 100% tested.
UnitsMin Max Min Max Min Max
100 100 50 ns
4.7 4.7 1.2 µs
1.0 1.0 0.3 µs
300 300 300 ns
Write
Cycles
0336I–SEEPR–07/02
5
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
AT24C32/64
0336I–SEEPR–07/02
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