The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.
Pin Configurations
A0
A1
A2
8-Pin TSSOP
1
2
3
4
8
VCC
7
WP
6
SCL
5
SDA
Pin NameFunction
A0 - A2Address Inputs
SDASerial Data
SCLSerial Clock Input
WPWrite Protect
GND
AT24C32
AT24C64
2-Wire, 32K
Serial E
2
PROM
A0
A1
A2
GND
8-Pin PDIP
1
2
3
4
8-Pin SOIC
1
8
VCC
7
WP
6
SCL
5
SDA
A0
A1
A2
GND
2
3
4
VCC
8
WP
7
SCL
6
SDA
5
Rev. 0336I–SEEPR–07/02
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°Cto+125°C
Storage Temperature ..................................... -65°Cto+150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current ........................................................ 5.0 mA
Block Diagram
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
2
AT24C32/64
0336I–SEEPR–07/02
AT24C32/64
Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to V
(8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to
GND.
, all write operations to the upper quandrant
CC
Memory Organization AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.
2,A1
,andA
0
0336I–SEEPR–07/02
3
Pin Capacitance
(1)
Applicable over recommended operating range from TA=25°C,f=1.0MHz,VCC= +1.8V.
SymbolTest ConditionMaxUnitsConditions
C
I/O
C
IN
Input/Output Capacitance (SDA)8pFV
I/O
=0V
Input Capacitance (A0,A1,A2,SCL)6pFVIN=0V
Note:1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI=-40°Cto+85°C, VCC= +1.8V to +5.5V, TAC=0°Cto+70°C,
V
= +1.8V to +5.5V (unless otherwise noted).
CC
SymbolParameterTest ConditionMinTypMaxUnits
V
V
V
V
I
I
I
I
I
I
CC1
CC2
CC3
CC4
CC1
CC2
SB1
SB2
SB3
SB4
Supply Voltage1.85.5V
Supply Voltage2.55.5V
Supply Voltage2.75.5V
Supply Voltage4.55.5V
Supply CurrentVCC= 5.0VREAD at 100 kHz0.41.0mA
Supply CurrentVCC= 5.0VWRITE at 100 kHz2.03.0mA
V
Standby Current
(1.8V option)
Standby Current
(2.5V option)
Standby Current
(2.7V option)
Standby Current
(5V option)
=1.8V
CC
=5.5V2.0
V
CC
V
=2.5V
CC
V
=5.5V2.0
CC
V
=2.7V
CC
V
=5.5V2.0
CC
V
= 4.5 - 5.5VVIN=VCCor V
CC
V
IN=VCC
V
IN=VCC
V
IN=VCC
or V
or V
or V
SS
SS
SS
SS
2035µA
0.1µA
0.5µA
0.5µA
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:1. V
4
AT24C32/64
Input Leakage
Current
Output Leakage
Current
Input Low Level
Input High Level
(1)
(1)
V
IN=VCC
V
OUT=VCC
or V
or V
SS
SS
0.103.0µA
0.053.0µA
-0.6VCCx0.3V
VCCx0.7VCC+0.5V
Output Low LevelVCC=3.0VIOL=2.1mA0.4V
Output Low LevelVCC=1.8VIOL=0.15mA0.2V
min and VIHmax are reference only and are not tested.
IL
0336I–SEEPR–07/02
AT24C32/64
AC Characteristics
Applicable over recommended operating range from TA=-40°Cto+85°C, VCC= +1.8V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
1.8-volt2.7-, 2.5-volt5.0-volt
SymbolParameter
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL100100400kHz
Clock Pulse Width Low4.74.71.2µs
Clock Pulse Width High4.04.00.6µs
Noise Suppression Time
(1)
Clock Low to Data Out Valid0.14.50.14.50.10.9µs
Time the bus must be free
before a new transmission can start
(1)
Start Hold Time4.04.00.6µs
Start Set-up Time4.74.70.6µs
Data In Hold Time000µs
Data In Set-up Time200200100ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time4.74.70.6µs
Data Out Hold Time10010050ns
WriteCycleTime201010ms
(1)
5.0V, 25°C, Page Mode1M1M1M
Note:1. This parameter is characterized and is not 100% tested.
UnitsMinMaxMinMaxMinMax
10010050ns
4.74.71.2µs
1.01.00.3µs
300300300ns
Write
Cycles
0336I–SEEPR–07/02
5
Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6
AT24C32/64
0336I–SEEPR–07/02
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
AT24C32/64
(1)
t
WR
Note:1. The write cycle time tWRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
0336I–SEEPR–07/02
7
Data Validity
Start and Stop Definition
Output Acknowledge
8
AT24C32/64
0336I–SEEPR–07/02
AT24C32/64
Device AddressingThe 32K/64K EEPROM requires an 8-bit device address word following a start condition
toenablethechipforareadorwriteoperation(refertoFigure1).Thedeviceaddress
word consists of a mandatory one, zero sequence for the first four most significant bits
as shown. This is common to all 2-wire EEPROM devices.
The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight
devices on the same bus. These bits must compare to their corresponding hardwired
input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them
to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to standby state.
NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. A low-V
resets the device to prevent data corruption in a noisy environment.
DATA SECURITY: The AT24C32/64 has a hardware data protection scheme that allows
the user to write protect the upper quadrant (8/16K bits) of memory when the WP pin is
at V
.
CC
detector (5-volt option)
CC
Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the
device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to Figure 2).
PAG E WR I TE : The 32K/64K EEPROM is capable of 32-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 31
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to Figure 3).
The data word address lower 5 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 32 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
,tothe
WR
0336I–SEEPR–07/02
9
Read
Operations
Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page, to the first byte of the first
page. The address “roll over” during write is from the last byte of the current page to the first
byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 6).
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
A10.050.33
b0.350.515
C0.180.255
D5.135.38
E5.135.412, 3
H7.628.38
L0.510.89
e 1.27 BSC4
MIN
NOM
MAX
NOTE
5/2/02
2325 Orchard Parkway
R
San Jose, CA 95131
0336I–SEEPR–07/02
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
B
17
8A2 – TSSOP
Pin 1 indicator
this corner
123
N
Top View
b
e
D
Side View
A2
E1
E
L1
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
D2.903.003.102, 5
E6.40 BSC
E14.304.404.503, 5
A––1.20
A20.801.001.05
b0.19–0.304
e0.65 BSC
L0.450.600.75
L11.00 REF
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
18
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
2325 Orchard Parkway
R
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
AT24C32/64
0336I–SEEPR–07/02
5/30/02
REV.
B
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Corporate Headquarters
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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
AT ME L®is the registered trademark of Atmel Corporation.
Other terms and product names may be the trademark of others.
Printed on recycled paper.
0336I–SEEPR–07/02xM
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