Rainbow Electronics AT24C512 User Manual

Features

• Low-voltage and Standard-voltage Operation

–2.7(V
–1.8(V

=2.7Vto5.5V)

CC

=1.8Vto3.6V)

CC

• Internally Organized 65,536 x 8

• 2-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

• Write Protect Pin for Hardware and Software Data Protection

• 128-byte Page Write Mode (Partial Page Writes Allowed)

• Self-timed Write Cycle (5 ms Typical)

• High Reliability

– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead LAP and 8-ball dBGA

Packages

TM

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s
cascadable feature allows up to 4 devices to share a common 2-wire bus. The device
is optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The devices are available in space-saving
8-pin PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP) and 8­ball dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 3.6V) versions.

2-wire Serial
EEPROM

512K (65,536 x 8)

AT24C512

Pin Configurations

Pin Name Function

A0 - A1 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-lead TSSOP

8

VCC

7

WP

6

SCL

5

SDA

VCC

8

WP

7

SCL

6

SDA

5

NC

GND

A0
A1

NC

GND

1

A0

2

A1

3
4

8-lead SOIC

1
2
3
4

8-lead PDIP

8

A0
A1

NC

GND

1
2
3
4

VCC

7

WP

6

SCL

5

SDA

8-lead Leadless Array

VCC

WP

SCL

SDA

8
7
6
5

A0

1

A1

2

NC

3

GND

4

Bottom View

8-ball dBGA

VCC

WP
SCL
SDA

8

7

6

5

A0

2

A1

3

NC

4

GND

1

Bottom View

Rev. 1116H–SEEPR–08/02

1

Absolute Maximum Ratings*

Operating Temperature .................................. -55°Cto+125°C

Storage Temperature ..................................... -65°Cto+150°C

Voltage on Any Pin

with Respect to Ground .....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current ........................................................ 5.0 mA

Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

2

AT24C512

1116H–SEEPR–08/02

AT24C512

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.

DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with AT24C128/256.
When the pins are hardwired, as many as four 512K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Address­ing section). When the pins are not hardwired, the default A1 and A0 are zero.

WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to V
ited. If left unconnected, WP is internally pulled down to GND. Switching WP to V
to a write operation creates a software write protect function.

Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of

128-bytes each. Random word addressing requires a 16-bit data word address.

, all write operations to the memory are inhib-

CC

CC

prior

1116H–SEEPR–08/02

3

Pin Capacitance

(1)

Applicable over recommended operating range from TA=25°C, f = 1.0 MHz, VCC=+1.8V.

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

I/O

=0V

Input Capacitance (A0,A1,SCL) 6 pF VIN=0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics

Applicable over recommended operating range from: TAI=-40°Cto+85°C, VCC= +1.8V to +5.5V, TAC=0°Cto+70°C,
V

= +1.8V to +5.5V (unless otherwise noted).

CC

Symbol Parameter Test Condition Min Typ Max Units

V

V

V

I

I

I

I

I

CC1

CC2

CC3

CC1

CC2

SB1

SB2

SB3

Supply Voltage 1.8 3.6 V

Supply Voltage 2.7 5.5 V

Supply Voltage 4.5 5.5 V

Supply Current VCC= 5.0V READ at 400 kHz 1.0 2.0 mA

Supply Current VCC= 5.0V WRITE at 400 kHz 2.0 3.0 mA

V

Standby Current
(1.8V option)

Standby Current
(2.7V option)

Standby Current
(5.0V option)

=1.8V

CC

V

=3.6V 3.0

CC

V

=2.7V

CC

V

=5.5V 6.0

CC

V

=4.5-5.5V VIN=VCCor V

CC

V

IN=VCC

V

IN=VCC

or V

or V

SS

SS

SS

1.0 µA

2.0 µA

6.0 µA

I

LI

I

LO

V

IL

V

IH

V

OL2

V

OL1

Note: 1. V

Input Leakage Current VIN=VCCor V

Output Leakage
Current

Input Low Level

Input High Level

(1)

(1)

V

OUT=VCC

or V

SS

SS

-0.6 VCCx0.3 V

VCCx0.7 VCC+0.5 V

0.10 3.0 µA

0.05 3.0 µA

Output Low Level VCC=3.0V IOL=2.1mA 0.4 V

Output Low Level VCC=1.8V IOL=0.15mA 0.2 V

min and VIHmax are reference only and are not tested.

IL

4

AT24C512

1116H–SEEPR–08/02

AT24C512

AC Characteristics

Applicable over recommended operating range from TA=-40°Cto+85°C, VCC= +1.8V to +5.5V, CL= 100 pF (unless oth­erwise noted). Test conditions are listed in Note 2.

1.8-volt 2.7-volt 5.0-volt

Symbol Parameter

f

SCL

t

LOW

t

HIGH

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 100 400 1000 kHz

Clock Pulse Width Low 4.7 1.3 0.4 µs

Clock Pulse Width High 4.0 1.0 0.4 µs

Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a new
transmission can start

(1)

Start Hold Time 4.0 0.6 0.25 µs

Start Set-up Time 4.7 0.6 0.25 µs

Data In Hold Time 0 0 0 µs

Data In Set-up Time 200 100 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

Stop Set-up Time 4.7 0.6 0.25 µs

Data Out Hold Time 100 50 50 ns

WriteCycleTime 20 10 10 ms

(1)

5.0V, 25°C, Page Mode 100K 100K 100K Write Cycles

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
R

(connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)

L

Input pulse voltages: 0.3V

CC

to 0.7V

CC

Input rise and fall times: ≤50 ns
Input and output timing reference voltages: 0.5V

CC

UnitsMin Max Min Max Min Max

4.7 1.3 0.5 µs

1.0 0.3 0.3 µs

300 300 100 ns

1116H–SEEPR–08/02

5

Device Operation CLOCK and DATA TRANSITIONS: TheSDApinisnormallypulledhighwithanexter-

nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.

STANDBY MODE: The AT24C512 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2­wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

6

AT24C512

1116H–SEEPR–08/02

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

AT24C512

(1)

Note: 1. The write cycle time tWRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

1116H–SEEPR–08/02

7

Data Validity

Start and Stop Definition

Output Acknowledge

8

AT24C512

1116H–SEEPR–08/02

AT24C512

Device Addressing The 512K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (refer to Figure 1). The device address word
consists of a mandatory one, zero sequence for the first five most significant bits as
shown. This is common to all 2-wire EEPROM devices.

The 512K uses the two device address bits A1, A0 to allow as many as four devices on
the same bus. These bits must compare to their corresponding hardwired input pins.
The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low
condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read opera­tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to a standby state.

DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows
the user to write protect the whole memory when the WP pin is at V

Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device,
such as a microcontroller, then must terminate the write sequence with a stop condition.
At this time the EEPROM enters an internally-timed write cycle, t
memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (refer to Figure 2).

.

CC

, to the nonvolatile

WR

PAG E W R IT E : The 512K EEPROM is capable of 128-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 127
more data words. The EEPROM will respond with a zero after each data word received.
The microcontroller must terminate the page write sequence with a stop condition (refer
to Figure 3).

The data word address lower 7 bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the
memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more
than 128 data words are transmitted to the EEPROM, the data word address will “roll
over” and previous data will be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send­ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.

1116H–SEEPR–08/02

9

Read Operations Read operations are initiated the same way as write operations with the exception that

the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page, to the first
byte of the first page.

Oncethedeviceaddresswiththeread/writeselectbitsettooneisclockedinand
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 4).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 5).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen­tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi­tion (refer to Figure 6).

Figure 1. Device Address

10

AT24C512

1116H–SEEPR–08/02

Figure 2. Byte Write

Figure 3. Page Write

AT24C512

Figure 4. Current Address Read

1116H–SEEPR–08/02

11

Figure 5. Random Read

Figure 6. Sequential Read

12

AT24C512

1116H–SEEPR–08/02

AT24C512

Ordering Information

Ordering Code Package Operation Range

AT24C512C1-10CI-2.7

AT24C512-10PI-2.7
AT24C512N-10SI-2.7
AT24C512-10TI-2.7
AT24C512-10UI-2.7

AT24C512C1-10CI-1.8
AT24C512-10PI-1.8
AT24C512N-10SI-1.8
AT24C512-10TI-1.8
AT24C512-10UI-1.8

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.

8CN1

8P3
8S1
8A2
8U2

8CN1
8P3
8S1
8A2
8U2

Industrial

(-40°Cto85°C)

Industrial

(-40°Cto85°C)

Package Type

8CN1 8-lead, 0.300" Wide, Leadless Array Package (LAP)

8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)

8S1 8-lead, 0.150 Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8U2 8-ball, die Ball Grid Array Package (dBGA)

Options

-2.7 Low-voltage (2.7V to 5.5V)

-1.8 Low-voltage (1.8V to 3.6V)

1116H–SEEPR–08/02

13

Packaging Information

8CN1 – LAP

Marked Pin1 Indentifier

E

D

A

A1

Top View

0.10 mm
TYP

8

e

7

6

5

e1

Bottom View

Note: 1. Metal Pad Dimensions.

L1

Side View

Pin1 Corner

1

COMMON DIMENSIONS

2

SYMBOL

3

b

4

L

A 0.94 1.04 1.14

A1 0.30 0.34 0.38

b 0.36 0.41 0.46 1

D 7.90 8.00 8.10

E 4.90 5.00 5.10

e 1.27 BSC

e1 0.60 REF

L 0.62 0.67 0.72 1

L1 0.92 0.97 1.02 1

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

14

2325 Orchard Parkway

R

San Jose, CA 95131

AT24C512

TITLE

8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,

Leadless Array Package (LAP)

DRAWING NO.

8CN1

1116H–SEEPR–08/02

11/13/01

REV.

A

8P3 – PDIP

AT24C512

D1

b3

4 PLCS

Top View

D

e

Side View

1

E

E1

N

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

b

b2

A2 A

SYMBOL

A 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

L

D1 0.005 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

1116H–SEEPR–08/02

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

DRAWING NO.

8P3

01/09/02

REV.

B

15

8S1 – JEDEC SOIC

Top View

1

2

3

H

N

A2

L

e

D

Side View

E

End View

B

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 1.75

B – – 0.51

C

C – – 0.25

D – – 5.00

E – – 4.00

e 1.27 BSC

H – – 6.20

L – – 1.27

MIN

NOM

MAX

NOTE

16

Note:

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)

AT24C512

DRAWING NO.

8S1 A

1116H–SEEPR–08/02

10/10/01

REV.

8A2 – TSSOP

Pin 1 indicator

this corner

AT24C512

123

N

Top View

b

e

D

Side View

A2

E1

E

L1

L

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A ––1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

1116H–SEEPR–08/02

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

2325 Orchard Parkway

R

San Jose, CA 95131

TITLE

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

DRAWING NO.

8A2

5/30/02

REV.

B

17

8U2 – dBGA

ZM80.0

YXZM51.0

D

E

Pin 1 Mark
this corner

Top View

-Z-

8

1

2

7

3

6

Øb

d

4

5

D1

E1

Bottom View

e

A2

Side View

Notes: 1. These drawings are for general information only. No JEDEC Drawing to refer to for additional information.

2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum Z.

#

#

#

#

A

A1

SYMBOL

D 5.10

D1 1.43 TYP

E 3.25

E1 1.25 TYP

e 0.75 TYP

d 0.75 TYP

A 0.90 REF

A1 0.49 0.52 0.55

A2 0.35 0.38 0.41

Ø

b 0.47 0.50 0.53

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

NOM

TITLE

1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906

R

8U2, 8-ball 0.75 pitch, Die Ball Grid Array
Package (dBGA) AT24C512 (AT19870)

MAX

NOTE

02/04/02

DRAWING NO.

8U2

REV.

A

18

AT24C512

1116H–SEEPR–08/02

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© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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Other terms and product names may be the trademarks of others.

Printed on recycled paper.

1116H–SEEPR–08/02 xM