Rainbow Electronics AT24C16A User Manual

Features

• Write Protect Pin for Hardware Data Protection

– Utilizes Different Array Protection Compared to the AT24C02/04/08/16

• Low-voltage and Standard-voltage Operation

– 2.7 (V – 1.8 (V

• Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)

• 2-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bi-directional Data Transfer Protocol

• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate for AT24C02A, 04A and 08A

• 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V and 5V) Clock Rate for AT24C16A

• 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes

• Partial Page Writes are Allowed

• Self-timed Write Cycle (10 ms max)

• High Reliability

– Endurance: One Million Write Cycles – Data Retention: 100 Years

• Automotive Grade and Extended Temperature Devices Available

• 8-lead JEDEC SOIC, 8-pin PDIP, and 8-lead TSSOP Packages

= 2.7V to 5.5V)

= 1.8V to 5.5V)

2-wire Serial EEPROM

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

Description

The AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C02A/04A/08A/16A is available in space saving 8-pin PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP (AT24C02A/04A) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

Pin Configurations

A0 A1 A2

GND

A0 A1 A2

GND

8-pin PDIP

1 2 3 4

8 7 6 5

8-lead SOIC

1 2 3 4

VCC WP SCL SDA

VCC

SCL

SDA

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No-connect

16K (2048 x 8)

AT24C02A AT24C04A AT24C08A AT24C16A

8-lead TSSOP

GND

VCC

SCL

SDA

Rev. 0976D–12/01

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Pin Description

AT24C02A/04A/08A/16A

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that must be hard wired for the AT24C02A. As many as eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).

The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no-connect.

0976D–12/01

AT24C02A/04A/08A/16A

The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are noconnects.

The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no-connects.

WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to

, the write protection feature is enabled and operates as shown in the following

table.

WP Pin Status

At V

At GND Normal Read/Write Operations

24C02A 24C04A 24C08A 24C16A

Upper Half

(1K) Array

Part of the Array Protected

Upper Half

(2K) Array

Full (8K)

Array

Full (16K)

Array

Memory Organization AT24C02A, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,

the 2K requires an 8-bit data word address for random word addressing.

AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16 bytes each. Random word addressing requires a 9-bit data word address.

AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16 bytes each. Random word addressing requires a 10-bit data word address.

AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of 16 bytes each. Random word addressing requires an 11-bit data word address.

Pin Capacitance

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.

Symbol Test Condition Max Units Conditions

I/O

Note: 1. This parameter is characterized and is not 100% tested.

Input/Output Capacitance (SDA) 8 pF V

Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

I/O

= 0V

0976D–12/01

DC Characteristics

Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

= +1.8V to +5.5V (unless otherwise noted).

Symbol Parameter Test Condition Min Typ Max Units

CC1

CC2

CC3

CC4

SB1

Supply Voltage 1.8 5.5 V

Supply Voltage 2.5 5.5 V

Supply Voltage 2.7 5.5 V

Supply Voltage 4.5 5.5 V

Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA

Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA

Standby Current VCC =

1.8V

= VCC or V

0.6 3.0 µA

SB2

SB3

SB4

OL2

OL1

Standby Current VCC =

2.5V

Standby Current VCC =

2.7V

Standby Current VCC =

5.0V

Input Leakage Current VIN = VCC or V

Output Leakage Current V

Input Low Level

Input High Level

(1)

Output Low Level VCC =

3.0V

Output Low Level VCC =

1.8V

= VCC or V

= V

OUT

= 2.1 mA 0.4 V

= 0.15 mA 0.2 V

or V

Note: 1. VIL min and VIH max are reference only and are not tested.

1.4 4.0 µA

1.6 4.0 µA

8.0 18.0 µA

0.10 3.0 µA

0.05 3.0 µA

-0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

AT24C02A/04A/08A/16A

0976D–12/01

AT24C02A/04A/08A/16A

AC Characteristics

Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter

SCL

LOW

HIGH

BUF

HD.STA

SU.STA

HD.DAT

SU.DAT

SU.STO

Endurance

Clock Frequency, SCL 100 100 400 400 kHz

Clock Pulse Width Low 4.7 4.7 1.3 1.2 µs

Clock Pulse Width High 4.0 4.0 0.6 0.6 µs

Noise Suppression Time

Clock Low to Data Out Valid 0.1 4.5 0.1 4.5 0.2 0.9 0.1 0.9 µs

Time the bus must be free before a new transmission can start

Start Hold Time 4.0 4.0 0.6 0.6 µs

Start Set-up Time 4.7 4.7 0.6 0.6 µs

Data In Hold Time 0 0 0 0 µs

Data In Set-up Time 200 200 100 100 ns

Inputs Rise Time

Inputs Fall Time

Stop Set-up Time 4.7 4.7 0.6 0.6 µs

Data Out Hold Time 100 100 100 50 ns

Write Cycle Time 10 10 10 10 ms

(2)

5.0V, 25°C, Page Mode 1M 1M 1M 1M

AT24C02A/

04A/08A/16A

1.8V

AT2402A/04A/

08A

2.5V, 2.7V

AT24C16A

2.5V

AT24C02A/

04A/08A/16A

5.0V

UnitsMin Max Min Max Min Max Min Max

(1)

(2)

4.74.71.31.2 µs

100 100 100 50 ns

1.0 1.0 0.3 0.3 µs

300 300 300 300 ns

Write

Cycles

Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).

2. This parameter is characterized and is not 100% tested.

0976D–12/01

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8 bit words received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C02A/04A/08A/16A features a low power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.

The EEPROM sends a zero to acknowledge that it has

AT24C02A/04A/08A/16A

0976D–12/01

+ 14 hidden pages