Rainbow Electronics AT24C1024B User Manual

Features

• Low-voltage Operation

–1.8V (VCC = 1.8V to 3.6V)
–2.5V (V

• Internally Organized 131,072 x 8

• Two-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 400 kHz (1.8V) and 1 MHz (5V, 2.5V) Clock Rate

• Write Protect Pin for Hardware and Software Data Protection

• 256-byte Page Write Mode (Partial Page Writes Allowed)

• Random and Sequential Read Modes

• Self-timed Write Cycle (5 ms Typical)

• High Reliability

– Endurance: 1,000,000 Write Cycles/Page
– Data Retention: 40 Years

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead Ultra Thin

Small Array (SAP), and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Tape and Reel and Bumped Die

= 2.5V to 5.5V)

CC

Two-wire Serial
EEPROM

1M (131,072 x 8)

AT24C1024B

Description

The AT24C1024B provides 1,048,576 bits of serial electrically erasable and program­mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.

Table 1. Pin Configurations

Pin Name Function

A1 Address Input

A2 Address Input

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-lead SOIC

1

NC

A1
A2

GND

VCC

WP

SCL

SDA

2
3
4

8-lead dBGA2

8

7

6

5

8
7
6
5

1

NC

2

A1

3

A2

4

GND

VCC
WP
SCL
SDA

8-lead PDIP

NC

A1
A2

GND

1
2
3
4

8
7
6
5

8-lead TSSOP

NC

A1
A2

GND

1

2

3

4

8

7

6

5

8-lead Ultra-Thin SAP

8

1

VCC

WP

SCL

SDA

7

6

5

NC

2

A1

3

A2

4

GND

Bottom View

VCC
WP
SCL
SDA

VCC
WP
SCL
SDA

with Two Device
Address Inputs

Preliminary

Rev. 5194D–SEEPR–5/07

Bottom View

1

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

2

2

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

AT24C1024B [Preliminary]

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-

drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.

DEVICE/ADDRESSES (A1/A2): The A1, A2 pin is a device address input that can be hard­wired or left not connected for hardware compatibility with other AT24Cxx devices. When the
A1, A2 pins are hardwired, as many as four 1024K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
A1/A2 pins are left floating, the A1/A2 pin will be internally pulled down to GND if the capaci­tive coupling to the circuit board V
connecting the A1/A2 pin to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal
write operations. When WP is connected high to V
inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the
capacitive coupling to the circuit board V
mends connecting the pin to GND. Switching WP to V
software write-protect function.

plane is <3 pF. If coupling is >3 pF, Atmel recommends

CC

, all write operations to the memory are

CC

plane is <3 pF. If coupling is >3 pF, Atmel recom-

CC

prior to a write operation creates a

CC

Memory Organization

AT24C1024B, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of

256 bytes each. Random word addressing requires a 17-bit data word address.

5194D–SEEPR–5/07

3

Table 2. Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A1, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics
Applicable over recommended operating range from: T

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

CC2

I

CC

I

CC

I

SB1

I

SB2

I

LI

I

LO

V

IL

V

IH

V

OL1

V

OL2

Note: 1. VIL min and VIH max are reference only and are not tested.

Supply Voltage 1.8 3.6 V

Supply Voltage 2.5 5.5 V

Supply Current VCC = 5.0V READ at 400 kHz 2.0 mA

Supply Current VCC = 5.0V WRITE at 400 kHz 3.0 mA

VCC = 1.8V VIN = VCC or V

Standby Current

= 3.6V 3.0 µA

V

CC

V

= 2.5V VIN = VCC or V

Standby Current

Input Leakage Current VIN = V

Output Leakage

CC

V

= 5.5V 6.0 µA

CC

CC or VSS

V

= V

OUT

CC or VSS

Current

Input Low Level

Input High Level

(1)

(1)

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

= –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)

AI

SS

SS

1.0 µA

2.0 µA

0.10 3.0 µA

0.05 3.0 µA

–0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

4

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

Table 4. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T

erwise noted). Test conditions are listed in Note 2.

Symbol Parameter

AT24C1024B [Preliminary]

= −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless oth-

AI

1.8-volt 2.5, 5.0-volt

UnitsMin Max Min Max

f

SCL

t

LOW

t

HIGH

t

i

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 400 1000 kHz

Clock Pulse Width Low 1.3 0.4 µs

Clock Pulse Width High 0.6 0.4 µs

Noise Suppression Time

(1)

100 50 ns

Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a
new transmission can start

(1)

1.3 0.5 µs

Start Hold Time 0.6 0.25 µs

Start Set-up Time 0.6 0.25 µs

Data In Hold Time 0 0 µs

Data In Set-up Time 100 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

0.3 0.3 µs

300 100 ns

Stop Set-up Time 0.6 0.25 µs

Data Out Hold Time 50 50 ns

Write Cycle Time 5 5 ms

(1)

25°C, Page Mode, 3.3V 1,000,000

Write

Cycles

Notes: 1. This parameter is ensured by characterization only.

2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 V

to 0.7 V

CC

CC

Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 V

CC

5194D–SEEPR–5/07

5

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the Stop command will place the EEPROM in a standby power mode (see
Figure 5 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl­edge that it has received each word.

STANDBY MODE: The AT24C1024B features a low-power standby mode which is enabled:
a) upon power-up and b) after the receipt of the stop bit and the completion of any internal
operations.

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.

Start Bit Start Bit Stop Bit

Dummy Clock Cycles

SCL

SDA

123 89

Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O

®

)

6

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

S

S

CL

AT24C1024B [Preliminary]

DA

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

8th BIT

WORDn

ACK

STOP

CONDITION

(1)

t

wr

START

CONDITION

Figure 4. Data Validity

Figure 5. Start and Stop Definition

7

5194D–SEEPR–5/07