Rainbow Electronics AT24C1024B User Manual

Features

• Low-voltage Operation

–1.8V (VCC = 1.8V to 3.6V)
–2.5V (V

• Internally Organized 131,072 x 8

• Two-wire Serial Interface

• Schmitt Triggers, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 400 kHz (1.8V) and 1 MHz (5V, 2.5V) Clock Rate

• Write Protect Pin for Hardware and Software Data Protection

• 256-byte Page Write Mode (Partial Page Writes Allowed)

• Random and Sequential Read Modes

• Self-timed Write Cycle (5 ms Typical)

• High Reliability

– Endurance: 1,000,000 Write Cycles/Page
– Data Retention: 40 Years

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead Ultra Thin

Small Array (SAP), and 8-ball dBGA2 Packages

• Die Sales: Wafer Form, Tape and Reel and Bumped Die

= 2.5V to 5.5V)

CC

Two-wire Serial
EEPROM

1M (131,072 x 8)

AT24C1024B

Description

The AT24C1024B provides 1,048,576 bits of serial electrically erasable and program­mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.

Table 1. Pin Configurations

Pin Name Function

A1 Address Input

A2 Address Input

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

8-lead SOIC

1

NC

A1
A2

GND

VCC

WP

SCL

SDA

2
3
4

8-lead dBGA2

8

7

6

5

8
7
6
5

1

NC

2

A1

3

A2

4

GND

VCC
WP
SCL
SDA

8-lead PDIP

NC

A1
A2

GND

1
2
3
4

8
7
6
5

8-lead TSSOP

NC

A1
A2

GND

1

2

3

4

8

7

6

5

8-lead Ultra-Thin SAP

8

1

VCC

WP

SCL

SDA

7

6

5

NC

2

A1

3

A2

4

GND

Bottom View

VCC
WP
SCL
SDA

VCC
WP
SCL
SDA

with Two Device
Address Inputs

Preliminary

Rev. 5194D–SEEPR–5/07

Bottom View

1

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

2

2

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

AT24C1024B [Preliminary]

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-

drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.

DEVICE/ADDRESSES (A1/A2): The A1, A2 pin is a device address input that can be hard­wired or left not connected for hardware compatibility with other AT24Cxx devices. When the
A1, A2 pins are hardwired, as many as four 1024K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
A1/A2 pins are left floating, the A1/A2 pin will be internally pulled down to GND if the capaci­tive coupling to the circuit board V
connecting the A1/A2 pin to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal
write operations. When WP is connected high to V
inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the
capacitive coupling to the circuit board V
mends connecting the pin to GND. Switching WP to V
software write-protect function.

plane is <3 pF. If coupling is >3 pF, Atmel recommends

CC

, all write operations to the memory are

CC

plane is <3 pF. If coupling is >3 pF, Atmel recom-

CC

prior to a write operation creates a

CC

Memory Organization

AT24C1024B, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of

256 bytes each. Random word addressing requires a 17-bit data word address.

5194D–SEEPR–5/07

3

Table 2. Pin Capacitance

(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

C

I/O

C

IN

Input/Output Capacitance (SDA) 8 pF V

I/O

= 0V

Input Capacitance (A1, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics
Applicable over recommended operating range from: T

Symbol Parameter Test Condition Min Typ Max Units

V

CC1

V

CC2

I

CC

I

CC

I

SB1

I

SB2

I

LI

I

LO

V

IL

V

IH

V

OL1

V

OL2

Note: 1. VIL min and VIH max are reference only and are not tested.

Supply Voltage 1.8 3.6 V

Supply Voltage 2.5 5.5 V

Supply Current VCC = 5.0V READ at 400 kHz 2.0 mA

Supply Current VCC = 5.0V WRITE at 400 kHz 3.0 mA

VCC = 1.8V VIN = VCC or V

Standby Current

= 3.6V 3.0 µA

V

CC

V

= 2.5V VIN = VCC or V

Standby Current

Input Leakage Current VIN = V

Output Leakage

CC

V

= 5.5V 6.0 µA

CC

CC or VSS

V

= V

OUT

CC or VSS

Current

Input Low Level

Input High Level

(1)

(1)

Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

= –40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)

AI

SS

SS

1.0 µA

2.0 µA

0.10 3.0 µA

0.05 3.0 µA

–0.6 VCC x 0.3 V

VCC x 0.7 VCC + 0.5 V

4

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

Table 4. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T

erwise noted). Test conditions are listed in Note 2.

Symbol Parameter

AT24C1024B [Preliminary]

= −40°C to +85°C, VCC = +1.8V to +3.6V, CL = 100 pF (unless oth-

AI

1.8-volt 2.5, 5.0-volt

UnitsMin Max Min Max

f

SCL

t

LOW

t

HIGH

t

i

t

AA

t

BUF

t

HD.STA

t

SU.STA

t

HD.DAT

t

SU.DAT

t

R

t

F

t

SU.STO

t

DH

t

WR

Endurance

Clock Frequency, SCL 400 1000 kHz

Clock Pulse Width Low 1.3 0.4 µs

Clock Pulse Width High 0.6 0.4 µs

Noise Suppression Time

(1)

100 50 ns

Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 µs

Time the bus must be free before a
new transmission can start

(1)

1.3 0.5 µs

Start Hold Time 0.6 0.25 µs

Start Set-up Time 0.6 0.25 µs

Data In Hold Time 0 0 µs

Data In Set-up Time 100 100 ns

Inputs Rise Time

Inputs Fall Time

(1)

(1)

0.3 0.3 µs

300 100 ns

Stop Set-up Time 0.6 0.25 µs

Data Out Hold Time 50 50 ns

Write Cycle Time 5 5 ms

(1)

25°C, Page Mode, 3.3V 1,000,000

Write

Cycles

Notes: 1. This parameter is ensured by characterization only.

2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 V

to 0.7 V

CC

CC

Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 V

CC

5194D–SEEPR–5/07

5

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on
page 7). Data changes during SCL high periods will indicate a start or stop condition as
defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 5 on page 7).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the Stop command will place the EEPROM in a standby power mode (see
Figure 5 on page 7).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl­edge that it has received each word.

STANDBY MODE: The AT24C1024B features a low-power standby mode which is enabled:
a) upon power-up and b) after the receipt of the stop bit and the completion of any internal
operations.

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.

Start Bit Start Bit Stop Bit

Dummy Clock Cycles

SCL

SDA

123 89

Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O

®

)

6

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

S

S

CL

AT24C1024B [Preliminary]

DA

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

8th BIT

WORDn

ACK

STOP

CONDITION

(1)

t

wr

START

CONDITION

Figure 4. Data Validity

Figure 5. Start and Stop Definition

7

5194D–SEEPR–5/07

Figure 6. Output Acknowledge

Device Addressing

Write Operations

The 1024K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 7 on page 11). The device address
word consists of a mandatory one, zero sequence for the first four most significant bits as
shown. This is common to all two-wire EEPROM devices.

The 1024K uses the two device address bit, A1, A2, to allow up to four devices on the same
bus. These A1, A2 bits must compare to the corresponding hardwired input pins. The A1, A2
pin uses an internal proprietary circuit that biases it to a logic low condition if the pin is allowed
to float.

The seventh bit (P
address bit is the most significant bit of the data word address that follows. The eighth bit of
the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.

DATA SECURITY: The AT24C1024B has a hardware data protection scheme that allows the
user to write-protect the entire memory when the WP pin is at V

BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.
The word address field consists of the P
word address followed by the least significant word address (see Figure 8 on page 11)

A write operation requires the P
address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM enters
an internally timed write cycle, T
this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on
page 11).

) of the device address is a memory page address bit. This memory page

0

.

CC

bit of the device address, then the most significant

0

bit and two 8-bit data word addresses following the device

0

, to the nonvolatile memory. All inputs are disabled during

WR

8

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

AT24C1024B [Preliminary]

PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 255 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must ter­minate the page write sequence with a stop condition (see Figure 9 on page 11).

The data word address lower 8 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 256 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “rollover” during write is from the last byte of the current page to the
first byte of the same page.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.

5194D–SEEPR–5/07

9

Read Operations

Read operations are initiated the same way as write operations with the exception that the
read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “rollover”
during read is from the last byte of the last memory page, to the first byte of the first page.

Once the device address with the read/write select bit set to one is clocked in and acknowl­edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi­tion (see Figure 10 on page 11).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol­lowing stop condition (see Figure 11 on page 12).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran­dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con­tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero, but does generate a following stop condition (see Figure 12 on page 12).

10

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

Figure 7. Device Address

Figure 8. Byte Write

AT24C1024B [Preliminary]

A

2

0

Figure 9. Page Write

P

Figure 10. Current Address Read

MOST

SIGNIFICANT

P

0

MOST

SIGNIFICANT

0

LEAST

SIGNIFICANT

LEAST

SIGNIFICANT

5194D–SEEPR–5/07

11

Figure 11. Random Read

Figure 12. Sequential Read

High Byte
ADDRESS

P

0

P

0

High Byte

ADDRESS

Low Byte
ADDRESS

Low Byte

ADDRESS

Data n + 1 Data n + 2 Data n + X

12

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

AT24C1024B [Preliminary]

Ordering Information

Ordering Code Voltage Package Operation Range

AT24C1024B-PU (Bulk form only) 1.8 8P3
AT24C1024B-PU25 (Bulk form only) 2.5 8P3

(1)

AT24C1024BN-SH-B
AT24C1024BN-SH-T
AT24C1024BN-SH25-B
AT24C1024BN-SH25-T
AT24C1024BW-SH-B
AT24C1024BW-SH-T
AT24C1024BW-SH25-B
AT24C1024BW-SH25-T
AT24C1024B-TH-B
AT24C1024B-TH-T
AT24C1024B-TH25-B
AT24C1024B-TH25-T
AT24C1024BY7-YH-T
AT24C1024BY7-YH25-T
AT24C1024BU4-UU-T
AT24C1024B-W-11

(NiPdAu Lead Finish) 1.8 8S1

(2)

(NiPdAu Lead Finish) 1.8 8S1

(1)

(NiPdAu Lead Finish) 2.5 8S1

(2)

(NiPdAu Lead Finish) 2.5 8S1

(1)

(NiPdAu Lead Finish) 1.8 8S2

(2)

(NiPdAu Lead Finish) 1.8 8S2

(1)

(NiPdAu Lead Finish) 2.5 8S2

(2)

(NiPdAu Lead Finish) 2.5 8S2

(1)

(NiPdAu Lead Finish) 1.8 8A2

(2)

(NiPdAu Lead Finish) 1.8 8A2

(1)

(NiPdAu Lead Finish) 2.5 8A2

(2)

(NiPdAu Lead Finish) 2.5 8A2

(2)

(NiPdAu Lead Finish) 1.8 8Y7

(2)

(NiPdAu Lead Finish) 2.5 8Y7

(2)

(NiPdAu Lead Finish) 1.8 8U4-1

(3)

1.8 Die Sale Industrial Temperature

Lead-free/Halogen-free/

Industrial Temperature

(–40°C to 85°C)

(–40°C to 85°C)

Notes: 1. “-B” denotes bulk

2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel.

3. Available in tape and reel and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request.

Please contact Serial Interface Marketing.

Package Type

8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8S2 8-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP)

8U4-1 8-ball, die Ball Grid Array Package (dBGA2)

Options

–1.8 Low-voltage (1.8V to 3.6V)

–2.5 Low-voltage (2.5V to 5.5V)

5194D–SEEPR–5/07

13

Packaging Information

8P3 – PDIP

D1

b3

4 PLCS

Top View

D

e

Side View

1

E

E1

N

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

b

b2

A2 A

SYMBOL

A

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

L

D1 0.005

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

MIN

NOM

–

MAX

–

0.210 2

–

–

3

NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

14

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)

AT24C1024B [Preliminary]

DRAWING NO.

8P3

01/09/02

REV.

B

5194D–SEEPR–5/07

8S1 - JEDEC SOIC

Ø

E

1

N

TOP VIEW

C

E1

A

b

L

A1

e

D

SIDE VIEW

AT24C1024B [Preliminary]

C

1

E

N

Ø

TOP VIEW

e

b

D

SIDE VIEW

A

A1

SYMBOL

A 1.35 – 1.75
A1 0.10 – 0.25

b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27

θ 0˚ – 8˚

END VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

E1

L

NOM

MAX

NOTE

Note:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906

R

5194D–SEEPR–5/07

TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC)

DRAWING NO.

8S1 C

3/17/05

REV.

15

8S2 – EIAJ SOIC

q

1

N

E

TOP VIEW

C

E1

END VIEW

A

b

L

A1

e

D

SIDE VIEW

C

1

E

N

TOP VIEW

e

b

A

A1

D

SIDE VIEW

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

END VIEW

SYMBOL

A 1.70 2.16

A1 0.05 0.25

b 0.35 0.48 5

C 0.15 0.35 5

D 5.13 5.35

E1 5.18 5.40 2, 3

E 7.70 8.26

L 0.51 0.85

q 0° 8°

e 1.27 BSC 4

q

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

E1

L

NOM

MAX

NOTE

4/7/06

16

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)

AT24C1024B [Preliminary]

DRAWING NO.

8S2

5194D–SEEPR–5/07

REV.

D

8A2 - TSSOP

Pin 1 indicator

this corner

AT24C1024B [Preliminary]

123

N

Top View

b

e

D

Side View

A2

E1

E

L1

L

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A

D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5

A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.304
e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

5194D–SEEPR–5/07

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions s
(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Dat

um Plane H.

TITLE

2325 Orchard Parkway

R

San Jose, CA 95131

8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)

hall not exceed 0.25 mm

DRAWING NO.

8A2

5/30/02

REV.

B

17

8U4-1 - dBGA2

A1 BALL PAD CORNER

D

5. b

E

A1

TOP VIEW

A1 BALL PAD CORNER

1

2

A

B

e

C

D

(e1)

SIDE VIEW

A2

A

d

(d1)

BOTTOM VIEW

8 SOLDER BALLS

5. Dimension 'b' is measured at the maximum solder ball diameter.

This drawing is for general information only.

1150 E. Cheyenne Mtn. Blvd.

R

Colorado Springs, CO 80906

TITLE

8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch,
Small Die Ball Grid Array Package (dBGA2)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

A 0.81 0.91 1.00
A

1 0.15 0.20 0.25

A

2 0.40 0.45 0.50

b 0.25 0.30 0.35
D 2.47 BSC
E 4.07 BSC

e 0.75 BSC
e1 0.74 REF

d 0.75 BSC

d1 0.80 REF

DRAWING NO.

PO8U4-1 A

MAX

NOTE

1/5/05

REV.

18

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

8Y7 – SAP

AT24C1024B [Preliminary]

PIN 1 INDEX AREA

D

A

PIN 1 ID

D1

E1

L

E

A1

b

e

e1

A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 0.60
A1 0.00 – 0.05
D 5.80 6.00 6.20
E 4.70 4.90 5.10
D1 3.30 3.40 3.50
E1 3.90 4.00 4.10
b 0.35 0.40 0.45
e 1.27 TYP
e1 3.81 REF
L 0.50 0.60 0.70

MIN

NOM

MAX

NOTE

1150 E. Cheyenne Mtn. Blvd.

R

Colorado Springs, CO 80906

5194D–SEEPR–5/07

TITLE

8Y7, 8-lead (6.00 x 4.90 mm Body) Ultra-Thin SOIC Array

Package (UTSAP) Y7

DRAWING NO.

8Y7

10/13/05

REV.

B

19

Revision History

Doc. No. Date Comments

5194D 5/2007 Changed ‘Advance Information’ to ‘Preliminary’

5194C 4/2007 Reduced Pin Configuration sizes

Changed Maximum Operating Voltage from 6.0 to 6.25
Removed Device Power Up & Power Down Recommendation
Added A2 bit to Device Addressing
Removed LSB from Figure 10 Current Address Read
Removed reference to Waffle Pack
Modified Ordering Code table lines
Global change on Voltage from 3.6 to 5.5, Correct pg 1 drawings to

include address inputs

5194B 2/2007 Correct pg 1 TSSOP drawing

5194A 1/2007 Initial Document Release

20

AT24C1024B [Preliminary]

5194D–SEEPR–5/07

Atmel Corporation Atmel Operations

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

Regional Headquarters

Europe

Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: [phone]
Fax: [phone]

Asia

Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: [phone]
Fax: [phone]

Japan

9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: [phone]
Fax: [phone]

Memory

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

Microcontrollers

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: [phone]
Fax: [phone]

ASIC/ASSP/Smart Cards

Zone Industrielle
13106 Rousset Cedex, France
Tel: [phone]
Fax: [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: [phone]
Fax: [phone]

Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: [phone]
Fax: [phone]

RF/Automotive

Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: [phone]
Fax: [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: [phone]
Fax: [phone]

Biometrics

Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: [phone]
Fax: [phone]

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN­TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.

©2007 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, are registered trademarks or trademarks of Atmel Cor-
poration or its subsidiaries. Other terms and product names may be trademarks of others.

Printed on recycled paper.

5194D–SEEPR–5/07