Rainbow Electronics AT24C01 User Manual
Features
• Low Voltage and Standard Voltage Operation
–2.7(V
–1.8(V
=2.7Vto5.5V)
CC
=1.8Vto5.5V)
CC
• Internally Organized 128 x 8
• 2-Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
• 4-Byte Page Write Mode
• Self-Timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
2-Wire Serial
EEPROM
1K(128x8)
The AT24C01 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C01 is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.
Pin Configurations
Pin Name Function
NC No Connect
SDA Serial Data
SCL Serial Clock Input
TEST Test Input (GND or VCC)
8-lead PDIP
NC
NC
NC
GND
8-lead TSSOP
1
2
3
4
8-lead SOIC
VCC
8
TEST
7
SCL
6
SDA
5
AT24C0 1
NC
NC
NC
GND
8
1
2
3
4
VCC
7
TEST
6
SCL
5
SDA
NC
NC
NC
GND
1
2
3
4
VCC
8
TEST
7
SCL
6
SDA
5
Rev. 0134E–SEEPR–08/02
1
Absolute Maximum Ratings*
Operating Temperature .................................. -55°Cto+125°C
Storage Temperature ..................................... -65°Cto+150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current ........................................................ 5.0 mA
Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
2
AT24C01
0134E–SEEPR–08/02
AT24C01
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization AT24C01, 1K SERIAL EEPROM: Internally organized with 128 pages of 1 byte each.
The 1K requires a 7-bit data word address for random word addressing.
Pin Capacitance
Applicable over recommended operating range from TA=25°C, f = 1.0 MHz, VCC= +1.8V.
Symbol Test Condition Max Units Condition
C
I/O
C
IN
Input/Output Capacitance (SDA) 8 pF V
Input Capacitance (A0, A1, A2, SCL) 6 pF VIN=0V
DC Characteristics
I/O
=0V
Applicable over recommended operating range from: TAI=-40°Cto+85°C, VCC= +1.8V to +5.5V, TAC=0°Cto+70°C,
V
= +1.8V to +5.5V (unless otherwise noted).
CC
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note: 1. VILmin and VIHmax are reference only and are not tested.
Supply Voltage 1.8 5.5 V
Supply Voltage 2.5 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC= 5.0V READ at 100 kHz 0.4 1.0 mA
Supply Current VCC= 5.0V WRITE at 100 kHz 2.0 3.0 mA
Standby Current VCC=1.8V VIN=VCCor V
Standby Current VCC=2.5V VIN=VCCor V
Standby Current VCC=2.7V VIN=VCCor V
Standby Current VCC=5.0V VIN=VCCor V
Input Leakage Current VIN=VCCor V
Output Leakage Current V
Input Low Level
Input High Level
(1)
(1)
OUT=VCC
or V
SS
SS
SS
SS
SS
SS
-0.6 VCC× 0.3 V
VCC× 0.7 VCC+0.5 V
0.6 3.0 µA
1.4 4.0 µA
1.6 4.0 µA
8.0 18.0 µA
0.10 3.0 µA
0.05 3.0 µA
Output Low Level VCC=3.0V IOL=2.1mA 0.4 V
Output Low Level VCC=1.8V IOL=0.15mA 0.2 V
0134E–SEEPR–08/02
3
AC Characteristics
Applicable over recommended operating range from TA=-40°Cto+85°C, VCC= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
2.7-, 2.5-, 1.8-volt 5.0-volt
Symbol Parameter
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
Clock Frequency, SCL 100 400 kHz
Clock Pulse Width Low 4.7 1.2 µs
Clock Pulse Width High 4.0 0.6 µs
Noise Suppression Time
(1)
Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time 4.0 0.6 µs
Start Set-up Time 4.7 0.6 µs
Data In Hold Time 0 0 µs
Data In Set-up Time 200 100 ns
Inputs Rise Time
Inputs Fall Time
(1)
(1)
Stop Set-up Time 4.7 0.6 µs
Data Out Hold Time 100 50 ns
WriteCycleTime 10 10 ms
(1)
5.0V, 25°C, Page Mode 1M 1M
Note: 1. This parameter is characterized and is not 100% tested.
UnitsMin Max Min Max
100 50 ns
4.7 1.2 µs
1.0 0.3 µs
300 300 ns
Write
Cycles
4
AT24C01
0134E–SEEPR–08/02
AT24C01
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition
which terminates all communications. After a read sequence, the stop command will
place the EEPROM in a standby power mode (refer to Start and Stop Definition timing
diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. Any device on the system bus receiving data (when communicating with the EEPROM) must pull the SDA bus low to acknowledge that it has
successfully received each word. This must happen during the ninth clock cycle after
each word received and after all other system devices have freed the SDA bus. The
EEPROM will likewise acknowledge by pulling SDA low after receiving each address or
data word (refer to Acknowledge Response from Receiver timing diagram).
STANDBY MODE: The AT24C01 features a low power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
0134E–SEEPR–08/02
5
Loading...