Rainbow Electronics AT17LV040 User Manual

Features

• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,

2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)

• Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version

• In-System Programmable (ISP) via Two-Wire Bus

• Simple Interface to SRAM FPGAs

•

Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™ Devices, Lucent ORCA

• Cascadable Read-back to S upport Additional Configurations or Higher-density Arrays

• Very Low-power CMOS EEPROM Process

• Programmable Reset Polarity

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• High-reliability

– Endurance: 100,000 Write Cycles – Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for

Commercial Parts (at 70°C)

FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex® FPGAs

FPGA Configuration EEPROM Memory

AT17LV65

Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easyto-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The AT17LV series Configurators uses a si mple se rial -acce ss pro cedure to confi gure on e or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These dev ices also suppor t a write-protection mechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Table 1. AT17LV Series Packages

AT17LV65/

AT17LV128/

Package

8-lead LAP Yes Yes Yes 8-lead PDIP Yes Yes – – 8-lead SOI C Yes 20-lead PLCC Yes Yes Yes – 20-lead SOIC Yes

AT17LV256

(2)

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

(3)

Use 8-lead LAP

(2)

Yes

(1)

Use 8-lead LAP

Yes

(1)

(2)

(3)

–

AT17LV128 AT17LV256 AT17LV512 AT17LV010 AT17LV002 AT17LV040

3.3V and 5V System Support

44-lead PLCC – – Yes Yes 44-lead TQFP – – Yes Yes

Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-

lead SOIC package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead LAP package instead.

2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the AT17LV512/010/002 devices.

3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.

Rev. 2321D–CNFG–10/02

Pin Configuration

8-lead LAP

(WP

(1)

DATA

(1)

) RESET/OE

DATA

CLK

) RESET/OE

DATA

CLK

(1)

) RESET/OE

CLK

2 3

8-lead SOIC

1 2 3 4

8-lead PDIP

1 2 3

20-lead PLCC

VCC

SER_EN

CEO (A2)

GND

8 7 6 5

VCC SER_EN CEO (A2) GND

DATANCVCC

4 5 6 7 8

101112

GND

CLK

(2)

(WP1

(1)

(WP

) RESET/OE

Notes: 1. This pin is only available on AT17LV65/128/256 devices.

) NC

(2)

(WP2

) NC

2. This pin is only available on AT17LV512/010/002 devices.

18 17 16 15 14

NCNCNC

NC SER_EN NC NC (READY CEO (A2)

(2)

)

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

AT17LV65/128/256/512/010/002/040

20-lead SOIC

DATA

CLK

RESET/OE

NC CE NC

GND

Note: 1. This pinout only applies to AT17LV65/128/256 devices.

DATA

CLK

NC NC NC NC

RESET/OE

1 2 3 4 5 6 7 8 9 10

20-lead SOIC

1 2 3 4 5 6 7 8 9 10

(1)

20 19 18 17 16 15 14 13 12 11

(1)

20 19 18 17 16 15 14 13 12 11

VCC NC NC SER_EN NC NC CEO (A2) NC NC NC

VCC NC SER_EN NC NC NC NC CEO NC GND

2321D–CNFG–10/02

Note: 1. This pinout only applies to AT17LV512/010/002 devices.

(WP1

44 PLCC

CLKNCNC

(1)

)

NC NC NC NC NC NC NC NC NC NC NC

65432

7 8 9 10 11 12 13 14 15 16 17

1819202122232425262728

RESET/OE

DATANCVCCNCNC

NCCENC

4443424140

GND

SER_EN

39 38 37 36 35 34 33 32 31 30 29

CEO/A2

NC NC NC NC NC NC NC NC NC NC READY

44 TQFP

(WP1

CLKNCNC

4443424140393837363534

(1)

)

1213141516171819202122

RESET/OE

DATANCVCCNCNC

NCCENC

GND

SER_EN

CEO(A2)

Note: 1. This pin is only available on AT17LV002 devices.

33 32 31 30 29 28 27 26 25 24 23

NC NC NC NC NC NC NC NC NC NC READY

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

Block Diagram

POWER ON

RESET

SER_EN

WP1 WP2

AT17LV65/128/256/512/010/002/040

(2)

READY

Notes: 1. This pin is only available on AT17LV65/128/256 devices.

2. This pin is only available on AT17LV512/010/002 devices.

(1)

Device Description The control signals for the configu ration E EPROM (C E, RESET/OE and CCLK) inter-

face directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller.

The configuration EEPROM RESET/OE DATA output pin and enable the a ddres s counter. W hen RES ET/OE configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV series configurator. If CE is held High after the RESET/OE stated. When OE enabled. When RESET/OE

reset pulse, the counter is disabled and the DATA output pin is tri-

is subsequently driv en Low, the cou nter an d the DATA output pin ar e

is driven High again, the address counter is reset and the

DATA output pin is tri-stated, regardless of the state of CE When the configurator has driven out all of its data and CEO

tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.

This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET

and CE pins control the tri-state buffer on the

is driven High, th e

is driven Low, the device

/OE.

2321D–CNFG–10/02

Pin Description

AT17LV65/

AT17LV128/

AT17LV256

DIP/

LAP/

Name I/O

DA TA

CLKI244243243543543

WP1I––––5––5–––––

RESET/OE

WP2I –7––7–––––

GND 5 10 10 5 10 11 5 10 11 24 18 24 18

CEO

A2 I – –

READYO– – – – 15 – – 15 – 29232923

SER_EN

SOIC20PLCC20SOIC

122121121240240

I36636836819131913

I4 8 8 4 8 10 4 8 1021152115

61414614

I 7 17 17 7 17 18 7 17 18 41 35 41 35

8 2020 8 2020 8 202044384438

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

8 DIP/ LAP20PLCC20SOIC

DIP/

LAP/

SOIC20PLCC20SOIC

614

PLCC44TQFP

27 21 27 21

PLCC44TQFP

DATA Three-state DATA output for configuration. Open-collector bi-dire ctional pin for

programming.

CLK Clock input. Used to increment the inter nal address and bit co unter for reading and

programming.

WP1 WRITE PROTECT (1) . Used to protect p ortions of memory during pr ogramming. Dis-

abled by default due to internal pul l-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010/002 devices.

RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low

level on RESET Low) enables th e da ta ou tput driv er. T he l ogic polar ity o f thi s i nput is pr ogram mable as either RESET/OE active Low. This document describes the pin as RESET

/OE resets both the address and bit counters. A High level (with CE

or RESET/OE. For most applications, RESET should be programmed

/OE.

WP Write protect (WP) input (when CE is Low) d uring progr amming only (SER _EN Low).

When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be written. This pin is only available on AT17LV65/128/256 devices.

WP2 WRITE PROTECT (2) . Used to protect p ortions of memory during pr ogramming. Dis-

abled by default due to internal pul l-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512/010 devices.

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

AT17LV65/128/256/512/010/002/040

CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the

address counter and enables the data output driver. A High level on CE the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN

Low).

disables both

GND Ground pin. A 0.2 µF decoupling capacitor between V

and GND is recommended.

CEO Chip Enable Output (active Low). This output goes Low when the address counter has

reached its maximum value . In a daisy ch ain of A T17LV s eries device s, the CEO one device must be connected to the CE Low as long as CE thereafter, CEO

is Low and OE is High. It will then follow CE until OE goes Low;

will stay High until the entire EEPROM is read again.

input of the next device in the chain. It will stay

pin of

A2 Device selection input, A2. This is used to enable (or select) the device during program-

ming (i.e., when SER_EN

is Low). A2 has an internal pull-down resistor.

READY Open collector reset state indicator. Driven Low during power-up reset, released when

power-up is complete. It is re commende d to use a 4.7 k is used.

W pull-up resistor when this pin

SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,

should be tied to VCC.

SER_EN

3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.

2321D–CNFG–10/02

FPGA Master Serial Mode Summary

The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The progr am is loaded either auto matically upon power-up, or on command, depending on the state of the FPGA mo de pins. In Mas ter mode, the FPGA automatically loads the configuration program from an external memory. The AT17LV Serial Configu ration EEPR OM has been de signed for com patibilit y with the Mast er Serial mode.

This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.

Control of Configuration

Cascading Serial Configuration EEPROMs

Most connections be tween the F PGA devi ce and the AT17LV Se rial EEPROM ar e simple and self-explanatory.

• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.

• The master FPGA CCLK output drives the CLK input of the AT17LV series configurator.

•The CEO configurator in a cascaded chain of EEPROMs.

• SER_EN

•The READY status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.

Note: 1. This pin is not available for the AT17LV65/128/256 devices.

For multiple FP GAs c onf igured as a daisy -chain , o r for F PGAs requ iring l arge r co nfiguration memories, cascaded configurators provide additional memory.

After the last bit from the first configur ator is read, the clock s ignal to the configurator asserts its CEO recognizes the Low level on its CE

After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level.

If the address counters are not to be reset upon completion, then the RESET can be tied to its inactive (High) level.

output of any AT17LV series configurator drives the CE input of the next

must be connected to VCC (except during ISP).

(1)

pin is available as an open-collector indicator of the device’s reset

output Low and disab les its DA TA line dr iver. Th e second configur ator

input and enables its DATA output.

/OE input

AT17LV Series Reset Polarity

The AT17LV series configurator allows the user to program the reset polarity as either RESET/OE algorithms.

or RESET/OE. This feature is supported by industry-standard programmer

Programming Mode The programming mo de i s entered by bringing SER_EN Low. In this mode the chip can

be programmed by the Two-Wire serial bus. T he prog rammin g is d one at V only. Programming super voltages are generated inside the chip.

supply

Standby Mode The A T17LV series c onfigurators enter a low-power sta ndby mode whenever CE is

asserted High. In this mode, the AT17LV65/128/256 c onfigurator consumes les s than 50 µA of current at 3.3V (100 µA for the AT17LV51 2/010 and 200 µA for the AT17LV002/040). Th e ou tput rem ai ns i n a hi gh -impedance state regardles s of the sta te of the OE

AT17LV65/128/256/512/010/002/040

input.

2321D–CNFG–10/02

Absolute Maximum Ratings*

Operating Temperature....................................-40°C to +85°C

Storage Temperature.....................................-65°C to +150°C

Voltage on Any Pin

with Respect to Ground..............................-0.1V to V

Supply Voltage (V

Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C

) .........................................-0.5V to +7.0V

+0.5V

AT17LV65/128/256/512/010/002/040

*NOTICE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the dev ice . This i s a stress r at ing onl y and functional operati on of the de vic e at these or an y other conditions beyond those listed under operating conditions is no t implied . Expos ure to Ab solute Maximum Rating condi tio ns for extended periods of time may affect device reliability.

ESD (R

= 1.5K, C

ZAP

= 100 pF)................................. 2000V

ZAP

Operating Conditions

Symbol Description

Commercial

Industrial

Supply voltage relative to GND

-0°C to +70°C Supply voltage relative to GND

-40°C to +85°C

3.3V 5V UnitsMin Max Min Max

3.0 3.6 4.75 5.25 V

3.0 3.6 4.5 5.5 V

2321D–CNFG–10/02

DC Characteristics

VCC = 3.3V ± 10%

Symbol Description

V V V V V V I I

CCA

CCS

High-level Input Voltage 2.0 V Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 0.4 V High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) 0.4 0.4 0.4 V Supply Current, Active Mode 5 5 5 mA Input or Output Leakage Current (VIN = VCC or GND) -10 10 -10 10 -10 10 µA

Supply Current, Standby Mode

DC Characteristics

AT17LV65/

AT17LV128/

AT17LV256

AT17LV512/

AT17LV010

AT17LV002/

AT17LV040

UnitsMin Max Min Max Min Max

2.0 V

2.4 2.4 2.4 V

Commercial

2.4 2.4 2.4 V

Industrial

Commercial 50 100 150 µA

Industrial 100 100 150 µA

VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial

Symbol Description

V V V V V V I I

CCA

CCS

High-level Input Voltage 2.0 V Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V High-level Output Voltage (IOH = -2.5 mA)

Commercial

Low-level Output Voltage (IOL = +3 mA) 0.32 0.32 0.32 V High-level Output Voltage (IOH = -2 mA)

Industrial

Low-level Output Voltage (IOL = +3 mA) 0.37 0.37 0.37 V Supply Current, Active Mode 10 10 10 mA Input or Output Leakage Current (VIN = VCC or GND) -10 10 -10 10 -10 10 µA

Supply Current, Standby Mode

Commercial 75 200 350 µA

Industrial 150 200 350 µA

AT17LV65/

AT17LV128/

AT17LV256

AT17LV512/

AT17LV010

AT17LV002/

AT17LV040

UnitsMin Max Min Max Min Max

2.0 V

3.7 3.86 3.86 V

3.6 3.76 3.76 V

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

AC Characteristics

RESET/OE

CLK

SCE

AT17LV65/128/256/512/010/002/040

SCE

HOE

HCE

DATA

AC Characteristics when Cascading

RESET/OE

CLK

CDF

DATA

CEO

LAST BIT

OCK

CAC

OCE

OOE

FIRST BIT

2321D–CNFG–10/02

OCE

AC Characteristics

VCC = 3.3V ± 10%

Symbol Description

(1)

CAC

(2)

SCE

HCE

HOE

MAX

Notes: 1. AC test lead = 50 pF.

OE to Data Delay 50 55 50 55 ns CE to Data Delay 60 60 55 60 ns CLK to Data Delay 75 80 55 60 ns Data Hold from CE, OE, or CLK 0000 ns CE or OE to Data Float Delay 55 55 50 50 ns CLK Low Time 25 25 25 25 ns CLK High Time 25 25 25 25 ns CE Setup Time to CLK

(to guarantee proper counting) CE Hold Time from CLK

(to guarantee proper counting) OE High Time (guarantees counter is reset) 25 25 25 25 ns Maximum Clock Frequency 10 10 15 10 MHz

2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.

AT17LV65/128/256 AT17LV512/010/002/040 Commercial Industrial Commercial Industrial MinMaxMinMaxMinMaxMinMax

Units

35 60 30 35 ns

0000 ns

AC Characteristics when Cascading

VCC = 3.3V ± 10%

Symbol Description

(2)

CDF

(1)

OCK

(1)

OCE

(1)

OOE

MAX

Notes: 1. AC test lead = 50 pF.

CLK to Data Float Delay 60 60 50 50 ns CLK to CEO Delay 55 60 50 55 ns CE to CEO Delay 55 60 35 40 ns RESET/OE to CEO Delay 40 45 35 35 ns

Maximum Clock Frequency 8 8 12.5

2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.

AT17LV65/128/256 AT17LV512/010/002/040

Commercial Industrial Commercial Industrial

Min Max Min Max Min Max Min Max

Units

MHz

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

AC Characteristics

VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial

Symbol Description

(1)

CAC

(2)

SCE

HCE

HOE

MAX

Notes: 1. AC test lead = 50 pF.

OE to Data Delay 30 35 30 35 ns CE to Data Delay 45 45 45 45 ns CLK to Data Delay 50 55 50 50 ns Data Hold from CE, OE, or CLK 0 0 0 0 ns CE or OE to Data Fl o a t D e l ay 50 50 50 50 ns CLK Low Time 20 20 20 20 ns CLK High Time 20 20 20 20 ns CE Setup Time to CLK (to guarantee proper

counting) CE Hold Time from CLK (to guarantee proper

counting) OE High Time (guarantees counter is reset) 20 20 20 20 ns Maximum Clock Frequency 12.5 12.5 15 15 MHz

2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.

AT17LV65/128/256/512/010/002/040

AT17LV65/128/256 AT 17LV512/010/002/040 Commercial Industrial Commercial Industrial

MinMaxMinMaxMinMaxMinMax

35 40 20 25 ns

0000 ns

Units

AC Characteristics when Cascading

VCC = 5V ± 5% Commercial; VCC = 5V ± 10% Industrial

Symbol Description

(2)

CDF

OCK

OCE

OOE

MAX

Notes: 1. AC test lead = 50 pF.

CLK to Data Float Delay 50 50 50 50 ns

(1)

CLK to CEO Delay 35 40 35 40 ns

(1)

CE to CEO Delay 35 35 35 35 ns

(1)

RESET/OE to CEO Delay 30 35 30 30 ns Maximum Clock Frequency 10 10 12.5 12.5 MHz

2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels.

AT17LV65/128/256 AT17LV512/010/002/040

Commercial Industrial Commercial Industrial

MinMaxMinMaxMinMaxMinMax

Units

2321D–CNFG–10/02

Thermal Resistance Coefficients

Package Type

[°C/W] 45 45 45 –

8CN4 Leadless Array Package (LAP)

8P3 Plastic Dual Inline Package (PDIP)

8S1

20J

20S2

44A

44J

Plastic Gull Wing Small Outline (SOIC)

Plastic Leaded Chip Carrier (PLCC)

Plastic Gull Wing Small Outline (SOIC)

Thin Plastic Quad Flat Package (TQFP)

Plastic Leaded Chip Carrier (PLCC)

[°C/W]

[°C/W] 37 37 – –

[°C/W]

[°C/W]45–––

[°C/W]

[°C/W] 35 35 35 –

[°C/W]

[°C/W] –

[°C/W]

[°C/W] – – 17 17

[°C/W]

[°C/W] – – 15 15

[°C/W]

(2)

(1)

AT17LV65/

AT17LV128/

AT17LV256

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

115.71 135.71 159.60 –

107 107 – –

150 – – –

90 90 90 –

– – 62 62

– – 50 50

–

Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.

2. Airflow = 0 ft/min.

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

Figure 1. Ordering Code

Voltage Size (Bits) Special Pinouts Package Temperature

3.0V to 5.5V

AT17LV65/128/256/512/010/002/040

AT17LV65A-10PC

C P N J S TQ BJ

= 20S2 = 44A = 44J

65 = 65K A = Altera 8CN4 C = Commercial 128 = 128K Blank = Xilinx/Atmel/ = 8P3 I = Industrial 256 = 256K = 8S1 512 = 512K = 20J 010 = 1M 002 = 2M 040 = 4M

Other

Package Type

8CN4 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

2321D–CNFG–10/02

Orderi ng Information

Memory Size Ordering Code Package Operation Range

64-Kbit

128-Kbit

256-Kbit

512-Kbit

1-Mbit

2-Mbit

4-Mbit

(1)

AT17LV65-10CC AT17LV65-10PC AT17LV65-10NC AT17LV65-10JC AT17LV65-10SC

AT17LV65-10CI AT17LV65-10PI AT17LV65-10NI AT17LV65-10JI AT17LV65-10SI

AT17LV128-10CC AT17LV128-10PC AT17LV128-10NC AT17LV128-10JC AT17LV128-10SC

AT17LV128-10CI AT17LV128-10PI AT17LV128-10NI AT17LV128-10JI AT17LV128-10SI

AT17LV256-10CC AT17LV256-10PC AT17LV256-10NC AT17LV256-10JC AT17LV256-10SC

AT17LV256-10CI AT17LV256-10PI AT17LV256-10NI AT17LV256-10JI AT17LV256-10SI

AT17LV512-10CC AT17LV512-10PC AT17LV512-10JC AT17LV512-10SC

AT17LV512-10CI AT17LV512-10PI AT17LV512-10JI AT17LV512-10SI

AT17LV010-10CC AT17LV010-10PC AT17LV010-10JC AT17LV010-10SC

AT17LV010-10CI AT17LV010-10PI AT17LV010-10JI AT17LV010-10SI

AT17LV002-10CC AT17LV002-10JC AT17LV002-10SC AT17LV002-10TQC AT17LV002-10BJC

AT17LV002-10CI AT17LV002-10JI AT17LV002-10SI AT17LV002-10TQI AT17LV002-10BJI

AT17LV040-10TQC AT17LV040-10BJC

AT17LV040-10TQI AT17LV040-10BJI

Note: 1. For operating voltage of 5V ±10%, please refer to the 5V ±10% AC and DC Characteristics.

8CN4

8P3 8S1

20J

20S2

8CN4

8P3 8S1

20J

20S2

8CN4

8P3 8S1

20J

20S2

8CN4

8P3 8S1

20J

20S2

8CN4

8P3 8S1

20J

20S2

8CN4

8P3 8S1

20J

20S2

8CN4

8P3

20J

20S2

8CN4

8P3

20J

20S2

8CN4

8P3

20J

20S2

8CN4

8P3

20J

20S2

8CN4

20J

20S2

44A

44J

8CN4

20J

20S2

44A

44J

44A

44J

44A

44J

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

Packaging Information

8CN4 – LAP

Marked Pin1 Indentifier

AT17LV65/128/256/512/010/002/040

Top View

0.10 mm TYP

Bottom View

Note: 1. Metal Pad Dimensions.

Side View

Pin1 Corner

COMMON DIMENSIONS

SYMBOL

A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 1 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e 1.27 BSC e1 1.10 REF L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1

(Unit of Measure = mm)

MIN

NOM

MAX

NOTE

2325 Orchard Parkway

San Jose, CA 95131

2321D–CNFG–10/02

TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,

Leadless Array Package (LAP)

DRAWING NO.

8CN4

11/14/01

REV.

8P3 – PDIP

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

A2 A

SYMBOL

A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3

D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2

MIN

NOM

MAX

NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

TITLE

2325 Orchard Parkway

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP)

AT17LV65/128/256/512/010/002/040

DRAWING NO.

8P3

2321D–CNFG–10/02

01/09/02

REV.

8S1 – SOIC

Top View

AT17LV65/128/256/512/010/002/040

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 1.75 B – – 0.51

C – – 0.25 D – – 5.00 E – – 4.00 e 1.27 BSC H – – 6.20 L – – 1.27

MIN

NOM

MAX

NOTE

Note:

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

2325 Orchard Parkway

San Jose, CA 95131

2321D–CNFG–10/02

TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC)

DRAWING NO.

8S1 A

10/10/01

REV.

20J – PLCC

1.14(0.045) X 45˚

0.51(0.020)MAX 45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1 IDENTIFIER

E1 E

1.14(0.045) X 45˚

0.318(0.0125)

0.191(0.0075)

D2/E2

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 Note 2 E 9.779 – 10.033 E1 8.890 – 9.042 Note 2

D2/E2 7.366 – 8.382

B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP

MIN

NOM

MAX

NOTE

2325 Orchard Parkway

San Jose, CA 95131

20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)

AT17LV65/128/256/512/010/002/040

TITLE

DRAWING NO.

20J

2321D–CNFG–10/02

10/04/01

REV.

20S2 – SOIC

AT17LV65/128/256/512/010/002/040

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

Side View

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.

2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006") per side.

3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side.

4. "L" is the length of the terminal for soldering to a substrate.

5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side.

SYMBOL

A 0.0926 0.1043 A1 0.0040 0.0118 b 0.0130 0.0200 4 C 0.0091 0.0125 D 0.4961 0.5118 1 E 0.2914 0.2992 2 H 0.3940 0.4190 L 0.0160 0.050 3 e 0.050 BSC

MIN

NOM

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)

MAX

DRAWING NO.

20S2

NOTE

1/9/02

REV.

2321D–CNFG–10/02

44A – TQFP

PIN 1

PIN 1 IDENTIFIER

E1 E

0˚~7˚

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 Note 2 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP

NOM

MAX

NOTE

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

AT17LV65/128/256/512/010/002/040

TITLE

10/5/2001

DRAWING NO.

44A

2321D–CNFG–10/02

REV.

44J – PLCC

AT17LV65/128/256/512/010/002/040

1.14(0.045) X 45˚

0.51(0.020)MAX 45˚ MAX (3X)

Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

PIN NO. 1 IDENTIFIER

1.14(0.045) X 45˚

E1 E

0.318(0.0125)

0.191(0.0075)

NOM

D2/E2

MAX

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 Note 2 E 17.399 – 17.653 E1 16.510 – 16.662 Note 2

D2/E2 14.986 – 16.002

B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP

MIN

NOTE

2325 Orchard Parkway

San Jose, CA 95131

2321D–CNFG–10/02

TITLE

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

44J

10/04/01

REV.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600

Europe

Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500

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Japan

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Memory

2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314

Microcontrollers

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La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2- 40-18- 19-6 0

ASIC/ASSP/Smart Cards

Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4- 42-53- 60-0 1

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Theresienstrasse 2 Postfach 3535 74025 Heilbro nn, Ge rmany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom

Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4- 76-58- 34-8 0

Atmel Programmable SLI Hotline

(408) 436-4119

Atmel Programmable SLI e-mail

configurator@atmel.com

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

FAQ

Available on web site

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Ter ms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

Atmel® is the registered trademark of Atmel.

™

is the trademark of Altera Corp oration; ORCA™ is the trademark of Lattice Semiconductors;

FLEX SPARTAN the trademarks of Xilinx, Inc.; APEX may be the trademarks of others.

and Virtex® are the registered trademarks of Xilinx, Inc.; XC3000™, XC4000™ and XC5200™ are

™

is the trademark of MIPS Technologies; Other terms and product names

Printed on recycled paper.

2321D–CNFG–10/02

Rainbow Electronics AT17LV040 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Description

Pin Configuration

Block Diagram

Device Description The control signals for the configu ration E EPROM (C E, RESET/OE and CCLK) inter-

Pin Description

DA TA

RESET/OE

READY Open collector reset state indicator. Driven Low during power-up reset, released when

SER_EN

FPGA Master Serial Mode Summary

Control of Configuration

Cascading Serial Configuration EEPROMs

AT17LV Series Reset Polarity

Programming Mode The programming mo de i s entered by bringing SER_EN Low. In this mode the chip can

Standby Mode The A T17LV series c onfigurators enter a low-power sta ndby mode whenever CE is

Absolute Maximum Ratings*

Operating Conditions

DC Characteristics

DC Characteristics

AC Characteristics

AC Characteristics when Cascading

AC Characteristics

AC Characteristics

Orderi ng Information

Packaging Information

8CN4 – LAP

8P3 – PDIP

8S1 – SOIC

20J – PLCC

20S2 – SOIC

44A – TQFP

44J – PLCC