Rainbow Electronics AT17LV040 User Manual

Features

• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,

2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)

• Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version

• In-System Programmable (ISP) via Two-Wire Bus

• Simple Interface to SRAM FPGAs

•

Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™ Devices,
Lucent ORCA

• Cascadable Read-back to S upport Additional Configurations or Higher-density Arrays

• Very Low-power CMOS EEPROM Process

• Programmable Reset Polarity

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and
44-lead TQFP Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• High-reliability

– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for

Commercial Parts (at 70°C)

®

FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex® FPGAs

FPGA
Configuration
EEPROM
Memory

AT17LV65

Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy­to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20­lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The
AT17LV series Configurators uses a si mple se rial -acce ss pro cedure to confi gure on e
or more FPGA devices. The user can select the polarity of the reset function by pro­gramming four EEPROM bytes. These dev ices also suppor t a write-protection
mechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard program­mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Table 1. AT17LV Series Packages

AT17LV65/

AT17LV128/

Package

8-lead LAP Yes Yes Yes
8-lead PDIP Yes Yes – –
8-lead SOI C Yes
20-lead PLCC Yes Yes Yes –
20-lead SOIC Yes

AT17LV256

(2)

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

(3)

Use 8-lead LAP

(2)

Yes

(1)

Use 8-lead LAP

Yes

(1)

(2)

(3)

–

AT17LV128
AT17LV256
AT17LV512
AT17LV010
AT17LV002
AT17LV040

3.3V and 5V
System Support

44-lead PLCC – – Yes Yes
44-lead TQFP – – Yes Yes

Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-

lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi­ble to use an 8-lead LAP package instead.

2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the
AT17LV512/010/002 devices.

3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.

Rev. 2321D–CNFG–10/02

1

Pin Configuration

8-lead LAP

(WP

(WP

(WP

(1)

DATA

(1)

) RESET/OE

DATA

CLK

) RESET/OE

CE

DATA

CLK

(1)

) RESET/OE

1

CLK

2
3

CE

4

8-lead SOIC

1
2
3
4

8-lead PDIP

1
2
3

CE

4

20-lead PLCC

VCC

8

SER_EN

7

CEO (A2)

6

GND

5

8
7
6
5

8
7
6
5

VCC
SER_EN
CEO (A2)
GND

VCC
SER_EN
CEO (A2)
GND

NC

DATANCVCC

3

2

CE

4
5
6
7
8

9

101112

NC

GND

CLK

(2)

(WP1

(1)

(WP

) RESET/OE

Notes: 1. This pin is only available on AT17LV65/128/256 devices.

) NC

(2)

(WP2

) NC

2. This pin is only available on AT17LV512/010/002 devices.

NC

1

20

19

18
17
16
15
14

13

NCNCNC

NC
SER_EN
NC
NC (READY
CEO (A2)

(2)

)

2

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

AT17LV65/128/256/512/010/002/040

20-lead SOIC

NC

DATA

NC

CLK

NC

RESET/OE

NC
CE
NC

GND

Note: 1. This pinout only applies to AT17LV65/128/256 devices.

DATA

NC

CLK

NC
NC
NC
NC

RESET/OE

NC

CE

1
2
3
4
5
6
7
8
9
10

20-lead SOIC

1
2
3
4
5
6
7
8
9
10

(1)

20
19
18
17
16
15
14
13
12
11

(1)

20
19
18
17
16
15
14
13
12
11

VCC
NC
NC
SER_EN
NC
NC
CEO (A2)
NC
NC
NC

VCC
NC
SER_EN
NC
NC
NC
NC
CEO
NC
GND

2321D–CNFG–10/02

Note: 1. This pinout only applies to AT17LV512/010/002 devices.

3

(WP1

44 PLCC

NC

CLKNCNC

(1)

)

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

NC

RESET/OE

DATANCVCCNCNC

NCCENC

1

4443424140

NC

NC

NC

GND

SER_EN

NC

39
38
37
36
35
34
33
32
31
30
29

NC

CEO/A2

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY

44 TQFP

NC

(WP1

CLKNCNC

4443424140393837363534

1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

(1)

7

)

NC

8

NC

9

NC

10

NC

11

NC

1213141516171819202122

NC

RESET/OE

DATANCVCCNCNC

NCCENC

NC

GND

NC

SER_EN

NC

CEO(A2)

NC

NC

Note: 1. This pin is only available on AT17LV002 devices.

33
32
31
30
29
28
27
26
25
24
23

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY

4

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

Block Diagram

POWER ON

RESET

SER_EN

WP1
WP2

AT17LV65/128/256/512/010/002/040

(2)

(2)

(2)

READY

Notes: 1. This pin is only available on AT17LV65/128/256 devices.

2. This pin is only available on AT17LV512/010/002 devices.

(1)

Device Description The control signals for the configu ration E EPROM (C E, RESET/OE and CCLK) inter-

face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.

The configuration EEPROM RESET/OE
DATA output pin and enable the a ddres s counter. W hen RES ET/OE
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV series configurator. If CE is held High after
the RESET/OE
stated. When OE
enabled. When RESET/OE

reset pulse, the counter is disabled and the DATA output pin is tri-

is subsequently driv en Low, the cou nter an d the DATA output pin ar e

is driven High again, the address counter is reset and the

DATA output pin is tri-stated, regardless of the state of CE
When the configurator has driven out all of its data and CEO

tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.

This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET

and CE pins control the tri-state buffer on the

is driven High, th e

.

is driven Low, the device

/OE.

2321D–CNFG–10/02

5

Pin Description

AT17LV65/

AT17LV128/

AT17LV256

8

DIP/

LAP/

Name I/O

DA TA

CLKI244243243543543

WP1I––––5––5–––––

RESET/OE

WP2I –7––7–––––

CE

GND 5 10 10 5 10 11 5 10 11 24 18 24 18

CEO

A2 I – –

READYO– – – – 15 – – 15 – 29232923

SER_EN

V

CC

SOIC20PLCC20SOIC

I/

O

O

122121121240240

I36636836819131913

I4 8 8 4 8 10 4 8 1021152115

61414614

I 7 17 17 7 17 18 7 17 18 41 35 41 35

8 2020 8 2020 8 202044384438

AT17LV512/

AT17LV010 AT17LV002 AT17LV040

8

8
DIP/
LAP20PLCC20SOIC

13

DIP/

LAP/

SOIC20PLCC20SOIC

13

614

44

PLCC44TQFP

27 21 27 21

44

PLCC44TQFP

DATA Three-state DATA output for configuration. Open-collector bi-dire ctional pin for

programming.

CLK Clock input. Used to increment the inter nal address and bit co unter for reading and

programming.

WP1 WRITE PROTECT (1) . Used to protect p ortions of memory during pr ogramming. Dis-

abled by default due to internal pul l-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010/002 devices.

RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low

level on RESET
Low) enables th e da ta ou tput driv er. T he l ogic polar ity o f thi s i nput is pr ogram mable as
either RESET/OE
active Low. This document describes the pin as RESET

/OE resets both the address and bit counters. A High level (with CE

or RESET/OE. For most applications, RESET should be programmed

/OE.

WP Write protect (WP) input (when CE is Low) d uring progr amming only (SER _EN Low).

When WP is Low, the entire memory can be written. When WP is enabled (High), the
lowest block of the memory cannot be written. This pin is only available on
AT17LV65/128/256 devices.

WP2 WRITE PROTECT (2) . Used to protect p ortions of memory during pr ogramming. Dis-

abled by default due to internal pul l-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010 devices.

6

AT17LV65/128/256/512/010/002/040

2321D–CNFG–10/02

AT17LV65/128/256/512/010/002/040

CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the

address counter and enables the data output driver. A High level on CE
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN

Low).

disables both

GND Ground pin. A 0.2 µF decoupling capacitor between V

and GND is recommended.

CC

CEO Chip Enable Output (active Low). This output goes Low when the address counter has

reached its maximum value . In a daisy ch ain of A T17LV s eries device s, the CEO
one device must be connected to the CE
Low as long as CE
thereafter, CEO

is Low and OE is High. It will then follow CE until OE goes Low;

will stay High until the entire EEPROM is read again.

input of the next device in the chain. It will stay

pin of

A2 Device selection input, A2. This is used to enable (or select) the device during program-

ming (i.e., when SER_EN

is Low). A2 has an internal pull-down resistor.

READY Open collector reset state indicator. Driven Low during power-up reset, released when

power-up is complete. It is re commende d to use a 4.7 k
is used.

W pull-up resistor when this pin

SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,

should be tied to VCC.

V

CC

SER_EN

3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) power supply pin.

2321D–CNFG–10/02

7

FPGA Master Serial Mode Summary

The I/O and logic functions of any SRAM-based FPGA are established by a configura­tion program. The progr am is loaded either auto matically upon power-up, or on
command, depending on the state of the FPGA mo de pins. In Mas ter mode, the FPGA
automatically loads the configuration program from an external memory. The AT17LV
Serial Configu ration EEPR OM has been de signed for com patibilit y with the Mast er
Serial mode.

This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as
well as Xilinx applications.

Control of Configuration

Cascading Serial Configuration EEPROMs

Most connections be tween the F PGA devi ce and the AT17LV Se rial EEPROM ar e sim­ple and self-explanatory.

• The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.

• The master FPGA CCLK output drives the CLK input of the AT17LV series
configurator.

•The CEO
configurator in a cascaded chain of EEPROMs.

• SER_EN

•The READY
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.

Note: 1. This pin is not available for the AT17LV65/128/256 devices.

For multiple FP GAs c onf igured as a daisy -chain , o r for F PGAs requ iring l arge r co nfigu­ration memories, cascaded configurators provide additional memory.

After the last bit from the first configur ator is read, the clock s ignal to the configurator
asserts its CEO
recognizes the Low level on its CE

After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.

If the address counters are not to be reset upon completion, then the RESET
can be tied to its inactive (High) level.

output of any AT17LV series configurator drives the CE input of the next

must be connected to VCC (except during ISP).

(1)

pin is available as an open-collector indicator of the device’s reset

output Low and disab les its DA TA line dr iver. Th e second configur ator

input and enables its DATA output.

/OE input

AT17LV Series Reset Polarity

The AT17LV series configurator allows the user to program the reset polarity as either
RESET/OE
algorithms.

or RESET/OE. This feature is supported by industry-standard programmer

Programming Mode The programming mo de i s entered by bringing SER_EN Low. In this mode the chip can

be programmed by the Two-Wire serial bus. T he prog rammin g is d one at V
only. Programming super voltages are generated inside the chip.

supply

CC

Standby Mode The A T17LV series c onfigurators enter a low-power sta ndby mode whenever CE is

asserted High. In this mode, the AT17LV65/128/256 c onfigurator consumes les s than
50 µA of current at 3.3V (100 µA for the AT17LV51 2/010 and 200 µA for the
AT17LV002/040). Th e ou tput rem ai ns i n a hi gh -impedance state regardles s of the sta te
of the OE

8

AT17LV65/128/256/512/010/002/040

input.

2321D–CNFG–10/02