Rainbow Electronics AT17F080 User Manual

Features

• Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store

Configuration Programs for Field Programmable Gate Arrays (FPGAs)

• 3.3V Output Capability

• 5V Tolerant I/O Pins

• In-System Programmable (ISP) via 2-wire Bus

• Simple Interface to SRAM FPGAs

• Compatible with Atmel AT40K and AT94K Devices, Altera FLEX

Lucent ORCA
Motorola MPA1000 FPGAs

• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays

• Low-power CMOS FLASH Process

• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC

Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages

• Emulation of Atmel’s AT24CXXX Serial EEPROMs

• Low-power Standby Mode

• Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System

Reconfiguration

• Fast Serial Download Speeds up to 33 MHz

®

FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex® FPGAs,

®

, APEX™ Devices,

In-System
Programmable
Configuration
PROM

Description

The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
44-lead PLCC and 44-lead TQFP, see Table 1. The AT17F Series Configurator uses a
simple serial-access procedure to configure one or more FPGA devices.

The AT17F Series Configurators can be programmed with industry-standard program­mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.

Table 1. AT17F Series Packages

Package AT17F040 AT17F080

8-lead LAP Yes Yes

20-lead PLCC Yes Yes

44-lead PLCC – Yes

44-lead TQFP – Yes

AT17F040
AT17F080

Advance
Information

Rev. 3039C–CNFG–11/02

1

Pin Configuration

8-lead LAP

RESET/OE

CLK

NC

RESET/OE

PAGESEL1

CE

DATA

1

CLK

2
3

CE

4

20-lead PLCC

NC

3

4
5
6
7
8

9

NC

VCC

8

SER_EN

7

CEO (A2)

6

GND

5

DATANCVCC

2

1

20

101112

NC

GND

PAGESEL0

NC

19

18
17
16
15
14

13

NC

NC
SER_EN
PAGE_EN
READY
CEO (A2)

2

AT17F040/080

3039C–CNFG–11/02

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

44 PLCC

NC

CLKNCNC

6

5

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

DATA

PAGE_EN

VCCNCNC

4

3

2

1

4443424140

SER_EN

NC

39
38
37
36
35
34
33
32
31
30
29

AT17F040/080

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1
2
3
4
5
6
7
8
9
10
11

NC

CE

RESET/OE

PAGESEL0

NC

NC

GND

PAGESEL1

NC

NC

CEO/A2

44 TQFP

NC

CLKNCNC

DATA

PAGE_EN

VCCNCNC

SER_EN

NC

4443424140393837363534

33
32
31
30
29
28
27
26
25
24
23

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY

3039C–CNFG–11/02

1213141516171819202122

NC

CE

NC

NC

GND

NC

NC

CEO(A2)

RESET/OE

PAGESEL0

PAGESEL1

3

Block Diagram

READY

PAGE_EN
PAGESEL0
PAGESEL1

Power-on

Reset

Config. Page

Select

Flash

Memory

Reset

CE/WE/OE

Data

Address

Clock/Oscillator

Logic

Serial Download Logic

2-wire Serial Programming

Control Logic

CLK

CEO(A2)

DATA

CE

RESET/OE

SER_EN

Device Description

The control signals for the configuration memory device (CE, RESET/OE and CLK)
interface directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration device without
requiring an external intelligent controller.

The RESET
enable the address counter. When RESET
resets its address counter and tri-states its DATA pin. The CE
put of the AT17F Series Configurator. If CE
pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subse­quently driven High, the counter and the DATA output pin are enabled. When
RESET
tri-stated, regardless of the state of CE

When the configurator has driven out all of its data and CEO
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.

/OE and CE pins control the tri-state buffer on the DATA output pin and

/OE is driven Low, the configuration device

pin also controls the out-

is held High after the RESET/OE reset

/OE is driven Low again, the address counter is reset and the DATA output pin is

.

is driven Low, the device

4

AT17F040/080

3039C–CNFG–11/02

Pin Description

AT17F040/080

AT17F040 AT17F080

8

Name I/O

DATAI/O1212240

CLK I2424543

PAGE_ENI–16–16139

PAGESEL0 I – 11 – 5 20 14

PAGESEL1 I – 7 – 7 25 19

RESET

/OEI36361913

CE

GND – 5 10 5 10 24 18

CEO

A2 I

READY O – 15 – 15 29 23

SER_EN

V

CC

I48482115

O

I7 17 7 174135

–8 20 8 204438

LAP

6 14 6 14 27 21

20

PLCC

8

LAP

20

PLCC

44

PLCC

44

TQFP

DATA Three-state DATA output for configuration. Open-collector bi-directional pin for

programming.

CLK Clock input. Used to increment the internal address and bit counter for reading and

programming.

PAGE _E N Input used to enable page download mode. When PAGE_EN is high the configuration

download address space is partitioned into 4 equal pages. This gives users the ability to
easily store and retrieve multiple configuration bitstreams from a single configuration
device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be
held low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no
effect.

PAGESEL[1:0] Page select inputs. Used to determine which of the 4 memory pages are targeted during

a serial configuration download. The address space for each of the pages is shown in
Table 2. When SER_EN is Low (ISP mode) these pins have no effect.

Table 2. Address Space

Paging Decodes AT17F040 (4 Mbits) AT17F080 (8 Mbits)

PAGESEL = 00, PAGE_EN = 1 00000 – 0FFFFh 00000 – 1FFFFh

PAGESEL = 01, PAGE_EN = 1 10000 – 1FFFFh 20000 – 3FFFFh

PAGESEL = 10, PAGE_EN = 1 20000 – 2FFFFh 40000 – 5FFFFh

PAGESEL = 11, PAGE_EN = 1 30000 – 3FFFFh 60000 – 7FFFFh

PAGESEL = XX, PAGE_EN = 0 00000 – 3FFFFh 00000 – 7FFFFh

3039C–CNFG–11/02

5

RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low

level on RESET
Low) enables the data output driver.

/OE resets both the address and bit counters. A High level (with CE

CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the

address counter and enables the data output driver. A High level on CE
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the 2-wire Serial Programming
mode (SER_EN

Low).

disables both

GND Ground pin. A 0.2 µF decoupling capacitor between V

and GND is recommended.

CC

CEO Chip Enable Output (active Low). This output goes Low when the address counter has

reached its maximum value. If the PAGE_EN input is set High, the maximum value is
the highest address in the selected partition. The PAGESEL[1:0] inputs are used to
make the 4 partition selections. If the PAGE_EN input is set Low, the device is not parti­tioned and the address maxvalue is the highest address in the device, see Table 2 on
page 5. In a daisy chain of AT17F Series devices, the CEO
connected to the CE
is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay
High until the entire EEPROM is read again.

input of the next device in the chain. It will stay Low as long as CE

pin of one device must be

A2 Device selection input, A2. This is used to enable (or select) the device during program-

ming (i.e., when SER_EN

is Low). A2 has an internal pull-down resistor.

READY Open collector reset state indicator. Driven Low during power-up reset, released when

power-up is complete. (recommended 4.7 k

W pull-up on this pin if used).

SER_EN Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN
should be tied to VCC.

V

CC

+3.3V (±10%).

6

AT17F040/080

3039C–CNFG–11/02