Rainbow Electronics APR6016 User Manual

APLUS INTEGRATED CIRCUITS INC.

APR6016

Voice Recording & Playback Device

16 Minute Duration

Features

•Multi-level analog storage

-High quality audio recording and playback

•Dual mode storage of analog and/or digital data

-Eliminates the need for separate digital memory

•Advanced, non-volatile Flash memory technology

-No battery backup required

•SPI interface

-Allows any commercial microcontroller to control the device

•Programmable Sampling Clock

-Allows user to choose quality and duration levels

•Single 3V power supply

•Low power consumption

-Playback operating current: 15 mA typical

-Standby current: 1 uA maximum

-Automatic power-down

•Multiple package options available

-CSP, PDIP, Bare Die

•On-board clock prescaler

-Eliminates the need for external clock dividers

•Automatic squelch circuit Reduces background noise during quiet passages

-

General Description

Figure 1 APR6016 Pinout Diagrams

The APR6016 offers non-volatile storage of voice and/or data in advanced Multi-Level Flash memory. Up to 16 minutes of audio recordin imum of 30K bits of di devices can be cascaded for lon

g and playback can be accommodated. A max-

gital data can be stored.

APR6016

ger duration recording or greater digital storage. Device control is accomplished throu

gh an industry standard SPI interface that allows a microcontroller to mana This flexible arran messa

ging options. The APR6016 is ideal for use in cellular and cordless phones, telephone answerin di

gital assistants, personal voice recorders, and voice pag-

ers.

APLUS Integrated

lity

by usin

i mplemented in an advanced non-volatile Flash memory

logy

g a proprietary analog multi-level storage te

process. Each memory cell can typically store 256 volta levels. This allows the si

gnals in their natural form, eliminating the need for en

ding

and compression which can introduce distortion.

2002/5/10 Page 1

ge message recording and playback.

gement allows for the widest variety of

g devices, personal

achieves this high level of storage capabi-

chno

ge

APR6008 voice

to

reproduce audio

co-

/CS

DI

DO

VSSD

NC NC NC

ANAOUT-

ANAOUT+

NC

l -

/RESET

VSSA

AUDOUT

SQLCAP

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 pin DIP

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SCLK VCCD EXTCLK /INT SAC VSSA NC /BUSY NC NC VCCA ANAIN+ ANAIN/SQLOUT

Preliminary

g

y

g

q

g

j

g

y

g

q

g

g g

g

APR6016 Data Sheet

Functional Description

The EXTCLK pin allows the use of an external samplin clock. This input can accept a wide range of frequencies dependin that follows the clock. Alternativel nal oscillator can be used to suppl Mux followin si

nal if a clock is present, otherwise the internal oscillator source is chosen. Detailed information on how to pro divider and internal oscillator can be found in the explanation of the

Command Description

the appropriate sample clock fre

Sampling Rate & Voice Quality

The audio si should be fed into the differential inputs ANAIN-, and ANAIN+. After pre-amplification the si anti-aliasin its response based on the sample rate bein nal anti-aliasin

After passin the sample and hold circuit which works in con the Analo flash memor

on the divider ratio programmed into the divider

, the programmable inter-

the sampling clock. The

both signals automatically selects the EXTCLK

PWRUP

command, which appears in the

section. Guidance on how to choose

uency can be found in the

section.

nal containing the content you wish to record

nal is routed into the

filter. The anti-aliasing filter automatically adapts

used. No exter-

filter is therefore required.

through the anti-alias filter, the signal is fed into

Write Circuit to store each analog sample in a

cell.

OpCode

unction with

ram the

When a read operation is desired the Analog Read Circuit extracts the analo the si

nal to the Internal Low Pass Filter. The low pass filter converts the individual samples into a continuous output. The output si ferential output driver. The differential output driver feeds the ANAOUT+ and ANAOUT- pins. Both differential output pins swin

The s si control si reducin mation, refer to the

After passin

oes to the output amplifier. The output amplifier drives a sinle ended output on the AUDOUT pin. The single ended out-

put swin

All SPI control and hand shakin Master Control Circuit. This circuit decodes all the SPI si and the status re the APR6016.

nal then goes to the squelch control circuit and dif-

around a 1.23V potential.

uelch control circuit automatically reduces the output

nal by 6 dB during quiet passages. A copy of the squelch

nal is present on the /SQLOUT pin to facilitate

ain in the external amplifier as well. For more infor-

s around a 1.23V potential.

enerates all the internal control signals. It also contains

data from the memory array and feeds

Squelch

through the squelch circuit the output signal

ister used for examining the current status of

section.

signals are routed to the

nals

Figure 2 APR6016 Block Diagram

/RESET

/BUSY

SAC

/INT

DO

DI

/CS

SCLK

EXTCLK

Row Address

Master Control Circuit

3.84 Mcell Memory Array

Row Decoder

Column Address

Programmable Internal

Oscillator

Programmable Divider

Single Analog Memory Cell

Column Decoder

Analog input/output to Memory array

Mux

Low Pass

Write Circuit

Read Circuit

Low Pass

Squelch

Pre-

Amp

ANAIN+

ANAIN-

ANAOUT+

ANAOUT-

AUDOUT

SQLCAP /SQLOUT

Page 2 Voice Recording & Playback Device

Revision 1.0

Preliminary

y

g

y

)

y

g

y

g

y

g

(

)

g

ying

g

y

g

y

g

APR6016 Data Sheet

Memory Organization

The APR6016 memory array is organized to allow the greatest flexibilit The smallest addressable memor The APR6016 contains 1280 sectors.

in message management and digital storage.

unit is called a “sector”.

Figure 3 Memory Map.

SAC Trigger Point

Sector 0

Sector 1

Sector 1279

Sectors 0 through 1279 can be used for analog storage. Durin

audio recording one memory cell is used per sample clock c bit is programed into the memory. This prevents playback of silence when partial sectors are used. Unused memor exists between the EOD bit and the end of the sector can not be used.

Sectors 0 throu stora store data but have not been tested, and are thus not teed to provide 100% error correction or forward check-before-store methods. Once a write c chosen sector is lost.

Mixin not possible.

cle. When recording is stopped an end of data (EOD

e. Other sectors, with the exception of sector 1279, can

audio signals and digital data within the same sector is

Note: There are a total of 15bits reserved for addressing. The APR6016 only requires 11 bits. The additional 4 bits are used for larger device within the APR60XX family.

Can Not be Used for Digital Data

that

h 9 are tested and guaranteed for digital

uaran-

ood bits. This can be managed with

cle is initiated all previously written data in the

SPI Interface

All memory management is handled by an external host processor. The host processor communicates with the APR6016 throu

h a simple Serial Peripheral Interface (SPI) Port. The SPI port can run on as little as three wires or as man seven dependin section will describe how to mana APR6016's SPI Port and associated OpCode commands. This topic is broken down into the followin

• Sendin

• OpCode Command Description

• Receivin

• Current Device Status

• Reading the Silicon Identification (SID)

•Writin

• Readin

• Recordin

•Pla

• Handshakin

Sending Commands to the Device

This section describes the process of sendin the APR6016. All Opcodes are sent in the same wa exception of the The in the that follow. The minimum SPI confi commands uses the DI, /CS, and SCLK pins. The device will accept inputs on the DI pin whenever the /CS pin is low. OpCode commands are clocked in on the risin SPI clock. Fi OpCode commands into the device. Figure 5 is a description of the OpCode stream.

You must wait for a command to finish executin in /BUSY pin. You can substitute monitorin inserting a fixed delay between commands. The required dela shows the timin mands. Table 1 describes which

Digital Data

Back Audio Data

DIG_WRITE and DIG_READ

Writing Digital Data

a new command. This is accomplished by monitoring the

is specified as

on the amount of control necessary. This

e memory using the

sections:

Commands to the Device

Device Information

CDS

Digital Data

Audio Data

Signals

OpCodes to

DIG_WRITE

and

ure 4 shows the timing diagram for shiftin

T

next1,Tnext2,Tnext3

diagram for sending consecutive com-

DIG_READ

and

commands

are

Reading Digital Data

uration needed to send

edge of the

before send-

of the busy pin b

or T

next4

specification to use.

T

. Figure 6

as

with the

described

sections

.

Voice Recording & Playback Device Page 3 Revision 1.0

Preliminary

APR6016 Data Sheet

Figure 4 Sending SPI Commands

/CS

SCLK

~

T

hiSCLK

T

, T

next1

next2

~

next3

~

next4

T

fCS

DI

Figure 5 OpCode Format

Op4 Op3 Op1 Op0 A14 A13 A12 A11 A10 A9 A8 A7 A6Op2

Op4

First bit shifted in

Op3

Op2 Op1

T

suDI

T

pSCLK

{

OpCode Command OpCode Parameter

Figure 6 Opcode Stream Timing

A0

T

rCS

~

T

loSCLK

~

T

A5 A4 A3 A2 A1

A1A2

hDI

Last bit shifted in

{

SCLK

/CS

DI

Page 4 Voice Recording & Playback Device

Current Com mand Next Command

T

next1,Tnext2,Tnext3,Tnext4

Revision 1.0

Preliminary

g

y

APR6016 Data Sheet

Table 1 Sequential Command Timing

Current Command Next command Timing Symbol

NOP

Any Command T

SID PWRUP

Any Command T

STOP_PWDN PWRUP

SET_REC

STOP, STOP_PWDN, SET_REC, REC,NOP REC SET_PLAY

STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP PLAY SET_FWD

SET_FWD, FWD, STOP, STOP_PWDN FWD DIG_WRITE DIG_READ DIG_ERASE STOP

Any Digital Command,

Note: For partial DIG_READ T

rise of /CS, not from the rise of /CS

Any Command T

STOP, STOP_PWDN

is measured from the extra clock low that follows the 8K sampling rate: 376m SEC

next3

OpCode Command Description

Designers have access to a total of 14 OpCodes. These OpCodes are listed in Table 2. The name of the Opcode appears in the left hand column. The followin represent the actual binar

information contained in the 20 bit

data stream. Some commands have limits on which com-

two columns

next1 5u SEC

next2 5m SEC

T

next2 5m SEC

Within SAC Low Time

T

next3

4K sampling rate: 752m SEC

next4 470m SEC

mand can follow them. These limits are shown in the “

able Follow on Commands

” column. The last column

Allow-

summarizes each command.

Combinations of OpCodes can be used to accommodate almost an

memory management scheme.

Table 2 APR6016 Operational Codes

Instruction

Name

NOP

SID

SET_FWD

FWD

PWRUP

STOP

STOP_PWDN

Voice Recording & Playback Device Page 5 Revision 1.0

OpCode

(5 bits) Opcode Parameters (15bits)

[Op4 - Op0]

[00000] [Don’t Care] All Commands No Operation [00001] [Don’t care] All Commands Causes the silicon ID to be read. [00010] Sector Address

[00011] [Don’t care] SET_FWD,

[00100] [A14-A10]: all zeros

[00110] [Don’t care] All Commands Stops the current operation.

[00111] [Don’t care] PWRUP Stops the current operation. Causes the

[Address MSB - Address LSB]

[Address 14 - Address 0]

[A14 - A0]

[A9-A2]: EXTCLK divider ratio

[A1-A0]: Sample Rate Frequency

Allowable Follow

on Commands Summary

SET_FWD,

FWD, STOP,

STOP_PWDN

FWD, STOP,

STOP_PWDN

All Commands Resets the device to initial conditions.

Starts a fast forward operation from the sector address specified.

Starts a fast forward operation from the current sector address.

Sets the sample frequency and divider ratios.

device to enter power down mode.

Preliminary

g

q

y

g

q

y

q

g

y

q

APR6016 Data Sheet

Instruction

Name

SET_REC

REC

DIG_ERASE

DIG_WRITE

DIG_READ

SET_PLAY

PLAY

OpCode

(5 bits) Opcode Parameters (15bits)

[Op4 - Op0]

[01000] Sector Address

[01001] [Don’t care] STOP,

[01010] Sector Address

[01011] [A14 - A0][XXXX][D0 - D3004][XXXX] All Commands This command writes data bits D0 - D3003

[01111] Sector A d dress

[01100] Sector Address

[01101] [Don’t care] STOP,

[Address MSB - Address LSB]

[Address 14 - Address 0]

[A14 - A0]

Allowable Follow

on Commands Summary

STOP,

STOP_PWDN,

SET_REC,

REC,NOP

STOP_PWDN,

SET_REC,

REC,NOP

All Commands Erases all data contained in specified sec-

All Commands This command reads data bits D0 - D3003

STOP,

STOP_PWDN,

SET_FWD, FWD,

SET_PLAY,PLAY,

NOP

STOP_PWDN,

SET_FWD, FWD,

SET_PLAY,PLAY,

NOP

Starts a record operation from the sector address specified.

Starts a record operation from the current sector address.

tor. You must not erase a sector before recording voice signals into it. You must erase a sector before storing digital data in it.

starting at the specified address. All 3004 bits must be written.

starting at the specified address.

Starts a play operation from the sector address specified.

Starts a play operation from the current sector address.

NOP

The most often used when readin more information on readin

Device Status

THE of its silicon ID re

ing the SID

The from the be

command performs no operation in the device. It is

the current device status. For

device status see the

section.

SID

operation instructs the device to return the contents

ister. For more information see the

section.

SET_FWD

command instructs the device to fast forward

inning of the sector specified in the OpCode

Current

Read-

parameter field. The device will fast forward until either an EOD bit, or the end of the sector is reached. If no EOD bit or forthcomin

command has been received when the end of the sector is reached, the device will loop back to the be nin

of the same sector and begin the same process again. If

an EOD bit is found the device will stop and

enerate an interrupt on the /INT pin. The output amplifiers are muted durin

this operation.

FWD

The

command instructs the device to fast forward from the start of the current sector to the next EOD marker. If no EOD marker is found within the current sector the device will increment to the next se

Page 6 Voice Recording & Playback Device

uential sector and continue looking.

The device will continue to fast forward in this manner until either an EOD is reached, a new command is sent, or the end of the memor the device will stop and The output amplifiers are muted durin

PWRUP

The mode and set the internal clock fre

array is reached. When an EOD is reached

enerate an interrupt on the /INT pin.

this operation.

command causes the device to enter power up

uency and EXTCLK divider ratio. The PWRUP command must be used to force the device into power up mode before an

commands can be executed. To select an Internal oscillator fre [A1 - A0] bits accordin

in-

A1 A0 Sample rate

to the following binary values:

0 0 6.4 kHz 0 1 4.0 kHz 1 0 8.0 kHz 1 1 5.3 kHz

If

ou are using an external sample clock signal you must

also set the EXTCLK divider ratio. This divider ratio is e

uency set the

ual

Revision 1.0

Preliminary

y

q

y)

g

q

g

y

g

y

g

y

g

y

g

y

g

y

q

y

APR6016 Data Sheet

to N:1 where N is an integer between 1 and 256, excluding 2. The N value should be selected to satisf tion as closel

EXTCLK fre

Example:

Suppose that 8.0 KHz samplin the fre

N

Roundin

The Op Code Parameter bit stream, composed of bits [A9 - A2][A1 - A0], therefore becomes binar [00001000][10].

STOP

The operation.

STOP_PWDN

The current command and enter power down mode. Durin down the device consumes si PWRUP command must be used to force the device into power up mode before an

SET_REC

The recordin continue to record until the end of the current sector is reached. If no forthcomin when the end of the sector is reached the device will loop back to the be previousl

SET_REC

mand immediatel that no audio information is lost. For more information see the section entitled

REC

The the current sector. If no new command is received before the device reaches the end of the sector the device will automaticall

increment to the next sequential sector and continue recordin until the memor command is received. For more information see the section entitled

DIG_ERASE

The sector specified. Erase should not be done before recordin voice signals into a sector. Erase must be done before storin digital data in a sector.

DIG_WRITE

The the specified sector. All 3K bits must be written, no partial usa

e of the sector is possible. The memory acts as a FIFO, the first data bit shifted in will be the first data bit shifted out. A sector must be erased usin

BEFORE

tion on storin

Digital Data

as possible:

= (N) * (128) * (selected sampling frequenc

uency of the signal present on EXTCLK = 8MHz.

8000000

---------- ------------- --128 8000()

up, N = 8

Command causes the device to stop the current

at the sector address specified. The device will

recorded material. If the next command is another

REC

or

7.8125==

command causes the device to stop the

nificantly less power. The

commands can be executed.

command instructs the device to begin

command has been received

inning of the same sector and overwrite the

command the device will execute the com following the end of the current sector so

Recording Audio Data

command instructs the device to begin recording in

. The device will continue to record in this manner

is exhausted or a

Recording Audio Data

command erases all data contained in the

command stores 3K bits of digital data in

data can be written to the sector. For more informa-

digital data, see the section entitled

.

the

the following equa-

is desired. Assume that

power

.

STOP

DIG_ERASE

STOP_PWDN

or

command

Writing

DIG_READ

The di

ital data that was previously written to the specified sector. The first bit shifted out is the first bit that was written. The last bit shifted out is the last bit that was written. For more information on readin

command instructs the device to retrieve

digital data see the section entitled

Read-

ing Digital Data.

SET_PLAY

The back at the specified sector. If no forthcomin received, or EOD bit encountered, before the end of the sector is reached the device will loop back to the be same sector and continue pla the audio output. If the next command is another

PLAY

or immediatel

ap in playback is present. For more information see the sec-

tion entitled

PLAY

The the current sector. If no forthcomin EOD bit encountered, before the device reaches the end of the sector the device will automaticall se

uential sector and continue playing. The device will con-

tinue to pla

STOP

a information see the section entitled

or

command instructs the device to begin play-

command is

inning of the

back with no noticeable gap in

SET_PLAY

command the device will execute the command

following the end of the current sector so that no

Playing Back Audio Data.

command instructs the device to begin playback at

in this manner until the memory is exhausted or

STOP_PWDN

command is received. For more

command is received, or

increment to the next

Playing Back Audio Data.

Voice Recording & Playback Device Page 7 Revision 1.0

Preliminary

g

y

g

y

g

APR6016 Data Sheet

Receiving Device Information

The device communicates data to the user by shifting out data on the DO pin. The device will shift out data accordin the timin

Figure 7 Data Out Timing

parameters given in figure 7. The device can shift

/CS

SCLK

DI

DO

Op4

Op3

D0

Op2 Op1

D1 D2 D18 D17 D19 D16

D3

to

~

out three different t con ID, and user stored di ID are described in the next two sections. Retrieval of user data is described in the

A3

D15

A2

pes of data streams: Device status, Sili-

ital data. Device status and silicon

Reading Digital Data

A1

A0

section.

T

fcsDO

Current Device Status (CDS)

As described in the previous section, three different types of data streams are shifted out on the DO pin as data is shifted in on the DI pin. One of these streams is the current device status. The CDS will be shifted out unless the previous command is SID command. Fi CDS bit stream. The first bit shifted out, D0, is the Overflow fla

. The Overflow flag is set to a binary 1 if an attempt was made to record be fla

is set to a 0 if an overflow has not occurred. This flag is

Figure 8 Format for CDS Bit Stream

D19

Sector Address MSBSector Addr

ond the available memory. The Overflow

~

T

fSCLK

ure 8 shows the format of the

}

~

Sector Address

ess LSB

T

hzD0

cleared after it has been read. The D1 bit is the End of Data

. The EOD flag is set when the device stops playing, or

fla fast forwardin fla

is cleared after it has been read. The D2 bit is the Illegal

Address fla

al address is sent to the device. The D3 bit is the Lbat flag. This fla below specification. The D4 bit is not used and should be i

nored. The last fifteen bits represent the address of the cur-

rent or last active sector.

as a result of an EOD bit in memory. The EOD

. The Illegal Address flag is set whenever an ille-

is set when the device senses a supply voltage

First bit shifted outLast bit shifted out

D0 D1 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D2

OVF

EOD

al Address

Ille

Lbat

Page 8 Voice Recording & Playback Device

Revision 1.0

Preliminary

(

y

g

y

g

y

(

ying

y

g

y

g

y

g

y

y (

y)

APR6016 Data Sheet

Reading the SID

Each device in the APR60XX series family contains an embedded Silicon Identification b

the host processor to identify which family / family member

is bein

Figure 9 SID Timing

used. Reading the device SID requires issuing two

SCLK

/CS

DI

DO

SID Command Next Command

CDS Output Data

SID). The SID can be read

OpCode commands; a SID command followed b command, usuall the SID data out on the DO pin as the command that follows the SID command is clocked in. Fi describes the process necessar

a NOP command. The device will clock

ure 9 is a diagram that

for reading SID information.

SID Output Data

any other

The SID information follows the format given in Figure 10. The first bit shifted out, D0, is the Overflow bit. The Overflow bit is set to a binar be

ond the available memory. The Overflow bit is set to a 0 if an overflow has not occurred. This bit is cleared after it has been read. The D1 bit is the End Of Data bit is set when the device stops pla a result of EOD bit in memor has been read. The D2 bit is the Ille

al Address Bit is set whenever an illegal address is sent to

Figure 10 SID Bit Stream

~

D19

}

Ignore These Bits

1 if an attempt was made to record

EOD) bit. The EOD

or fast forwarding as

. The EOD bit is cleared after it

al Address Bit. The Ille-

~

}

Device

Code

00

0

}

APR6016 Device Code (Binar

1

the device. The D3 bit is the Lbat bit. This bit is set when the device senses a suppl lowin

five bits represent the product family. The APR60XX product famil The next four bits represent the device code. The APR6016 device code is binar seven bits are random data and should be i

code is binary 01000 as shown in Figure 10.

}

Product

Famil

1

000

}

APR60XX Series Famil

Binar

voltage below specification. The fol-

0010 as shown in Figure 10 The last

nored.

First bit shifted outLast bit shifted out

0

Lbat

D2

Ille

D0D1D3D4D5D6D7D8D9D10D11D12D13D14

OVF

EOD

al Address

Voice Recording & Playback Device Page 9 Revision 1.0

Preliminary

g

y

g

y by

y

g

y

g

y

APR6016 Data Sheet

Writing Digital Data

Digital data is written into the device using the command. No mixing of analog data and digital data within a sector is possible. Sectors 0 throu anteed for di

ital storage. Other sectors, with the exception of

h 9 are tested and guar-

sector 1279, can store data but have not been tested, and are thus not be mana store methods. Issuin 1279 will cause data throu

A sector must be erased, usin before di necessar

uaranteed to provide 100% good bits. This can

ed with error correction or forward check-before-

DIG_ERASE

a

command on sector

hout all sectors to be lost.

DIG_ERASE

the ital data can be written to it. This requirement is whether analog data or digital data was previousl

stored in the sector. A sector should not be erased more than once between analo

or digital write operations. Executin multiple erase operations on a sector will permanently dama

e the sector. A sector can be reallocated to either analo

storage or digital storage at any time.

The process of storin

DIG_WRITE

command. The lowed immediatel stored in the arra

digital data begins by sending a

DIG_WRITE

four buffer bits. These bits will not be

and must be considered don’t care bits.

DIG_WRITE

command,

command is fol-

Figure 11 Writing Digital Data

Immediatel that

following the four buffer bits should be the data

ou wish to store. All 3004 bits must be stored. Four additional buffer bits must be clocked into the device followin

the stored data. These bits will not be stored in the arra and must be considered don’t care bits. Ending a digital write command earl

will permanently damage the sector.

The DO pin will clock out the normal 20 bit CDS followed b five don’t care bits, a copy of the 3004 data bits, and finall three don’t care bits.

ure 11 shows a timing diagram which describes the digital

Fi stora

e process. All timing with the exception of T

pSCLK

should adhere to the specifications given in Figure 4 and Figure 7. The T

specification is replaced by the DT

pSCLK

when storing digital data. The /BUSY pin indicates when a

DIG_WRITE

is taking place.

Note: The DIG_ERASE command should not be used before storing analog data. The device will perform its own internal erase before analog storage.

Figure 11 does not show the DIG_ERASE command which must be executed on a sector before digital data can be stored.

SCLK

/CS

D I

DO

/BUSY

DIG_WRITECOMMAND

CDS

X

XXX

Total 3032 clock c

X

cles

3004 bits of data to be stored

Four Don’t Care Bits

Copy of the input data (delayed one clock cycle)

X

XXX

X

Page 10 Voice Recording & Playback Device

Revision 1.0

Preliminary

y

g

y

g

y

g

y

APR6016 Data Sheet

Reading Digital Data

Digital data is read from the device using the command. To read data you must send a mand immediatel same /CS c sector will be

followed by 3012 don’t care bits during the

cle. The data previously stored in the specified

in to appear on the DO pin after the current device status or SID and four buffer bits. The next 3004 bits are the previousl

stored data. The first bit shifted out is the first bit that was written. The last bit shifted out is the last bit that was written. There are four random don’t care bits followin

the 3004 bits of user data.

DIG_READ

com-

Figure 12 Reading Digital Data

SCLK

Total 3032 clock cycles

/CS

DI

DIG_READ COMMAND

An incomplete read of the sector is allowed. An incomplete read is defined a a read with less than 3032 clock c incomplete read c the /CS si

ure 12 shows a timing diagram which describes the entire

Fi

nal returns high.

process for a complete sector read. All timin tion of T Fi b

pSCLK

ure 4 and Figure 7. The T

the DT

pSCLK

indicates when a

3012 don’t Care Bits

cles require one extra SCLK cycle after

with the excep-

should adhere to the specifications given in

specification is replaced

pSCLK

when reading digital data. The /BUSY pin

DIG_READ

is taking place.

cles. All

DO

/BUSY

SID or CDS

X

XXX

3004 bits of previousl

stored data

X

XXX

Voice Recording & Playback Device Page 11 Revision 1.0

Preliminary

g

y

g

y

g

q

y

g

y

g

y j

g

APR6016 Data Sheet

Recording Audio Data

When a be ANAIN- to the specified sector. After half the sector is used the SAC pin will drop low to indicate that a new command can be accepted. The device will accept commands as lon the SAC pin remains low. An SAC returns hi next SAC c

Fi se

SET_REC

or

SET_REC

in sampling and storing the data present on ANAIN+ and

cle.

ure 13 shows a typical timing diagram and OpCode

uence for a recording operation. In this example the

command begins recording at the specified mem-

location after T

Figure 13 Typical Recording Sequence

SCLK

/CS

REC

or

h will be queued up and executed during the

arec

command is issued the device will

as

command received after the

time has passed. Some time later the

low

oing edge on the SAC pin alerts the host processor that the first sector is nearl issuing a The recordin tor. When the first sector is full the device automaticall to the next sector and returns the SAC si to indicate that the second sector is now bein point the host processor decides to issue a durin command and terminates recording after TS pin indicates when actual recordin

REC

command before the SAC pin returns high.

REC

command instructs the APR6016 to continue

in the sector immediately following the current sec-

the next SAC cycle. The device follows the

full. The host processor responds b

nal to a high state

used. At this

STOP

command

.The /BUSY

is taking place.

arec

umps

STOP

DI

SAC

ANAIN+ ANAIN-

/BUSY

SET_REC

T

arec

REC

STOP

TS

arec

Page 12 Voice Recording & Playback Device

Revision 1.0

Playing Back Audio Data

g

y

g

y

g

q

g

y

g

y

g

q

y

g

y

g

y

g

When a will be duce a resultant output on the AUDOUT, ANAOUT-, and ANAOUT+ pins. After half the sector is used the SAC pin will drop low to indicate that a new command can be accepted. The device will accept commands as lon remains low. An hi c

Fi se mand be

SET_PLAY

in sampling the data in the specified sector and pro-

h will be queued up and executed during the next SAC

cle.

ure 14 shows a typical timing diagram and OpCode

uence for a playback operation. The

ins playback at the specified memory location after

PLAY

or

command received after the SAC returns

command is issued the device

as the SAC pin

SET_PLAY

com-

Figure 14 Typical Playback Sequence

SCLK

/CS

Preliminary

APR6016 Data Sheet

T

time has passed. Some time later the low going edge

aplay

on the SAC pin alerts the host processor that half of the first sector has been pla b

issuing a

PLAY

command instructs the APR6016 to continue playback of the sector immediatel the first sector has been pla next sector and returns the SAC si cate that the second sector is now bein the host processor decides to issue a the next available SAC low time. The device follows the

STOP

/BUSY pin indicates when actual pla

PLAY

command and terminates playback after TS

ed back. The host processor responds

command during the SAC low time. The

following the current sector. When

ed back the device jumps to the

nal to a high state to indi-

played. At this point

STOP

command durin

. The

back is taking place.

aplay

DI

SAC

ANAOUT+ ANAOUTANAOUT

/BUSY

Note: Command timing is not to scale

SET_PLAY

T

aplay

PLAY

Handshaking signals

Several signals are included in the device that allow for handshakin si scheme used.

The /INT si cessor when attention is re normall An interrupt is

. These signals can simplify message management

nificantly depending on the message management

nal can be used to generate interrupts to the pro-

uired by the APR6016 This pin is

high and goes low when an interrupt is requested.

enerated whenever a EOD or Overflow

STOP

TS

aplay

occurs.

The SAC si nearin a record, pla normall rentl

active segment has been played or recorded. The signal returns to a hi pla

ed or recorded. The microprocessor should sense the

low ed

nal is used to determine when the device is

the end of the current memory segment during either

or forward operation. The SAC signal is in a

high state. The signal goes low after half the cur-

h state after the entire segment has been

e of the SAC signal as an indicator that the next seg-

Voice Recording & Playback Device Page 13 Revision 1.0

Preliminary

g

y

g

y

g

y

q

g

q

g

q

g

y

g

y

g

y

g

y

g

y

g

y

g

q

g

y

q

y

g

y

g

q

g

q

y

g

APR6016 Data Sheet

ment needs to be selected, and do so before the SAC signal returns hi current se pla recordin

The /BUSY pin indicates when the device is performin a pla tion. The host microprocessor can monitor the bus confirm the status of these commands. The /BUSY pin is normall time is ified b

h. Failing to specify the next command before the

ment is exhausted (either during recording or

back) will result in a noticeable gap during playback or

.

either

, record, DIG_WRITE, DIG_READ or fast forward func-

pin to

high and goes low while the device is busy. The low

overned by the length of recording or playback spec-

the user.

Sampling Rate and Voice Quality

The Nyquist Sampling Theorem requires that the highest fre-

uency component a sampling system can accommodate without the introduction of aliasin samplin input, based on the selected samplin re

Hi hence voice same amount of recordin dates samplin

Lower samplin increase the duration capabilities of the device, but also reduce recordin rates as low as 4 kHz.

Desi controlling the sampling frequency. Sampling frequency can be controlled b can chan internal oscillator is used or an external clock is used.

frequency. The APR6016 automatically filters its

uirement.

her sampling rates increase recording bandwidth, and

uality, but also use more memory cells for the

rates as high as 8kHz.

rates use less memory cells and effectivel

bandwidth. The APR6016 allows samplin

ners can thus control the quality/duration trade-off b

using the PWRUP command. This command

e sampling frequency regardless of whether the

errors is equal to half the

frequency, to meet this

time. The APR6016 ccommo-

Storage Technology

The APR6016 stores voice signals by sampling incomin voice data and storing the sampled signals directly into FLASH memor ran

es from 1 to 256 levels. These 256 discrete voltage levels are the e values. Durin memor amplified before being fed to an external speaker amplifier.

, smoothed to form a continuous signal and finall

cells. Each FLASH cell can support voltage

uivalent of eight (28=256) bit binary encoded

playback the stored signals are retrieved from

Squelch

The APR6016 is equipped with an internal squelch feature. The S

uelch circuit automatically attenuates the output signal

b

6 dB during quiet passages in the playback material. Mut-

in

the output signal during quiet passages helps eliminate

back

round noise. Background noise may enter the system in a number of wa natural noise present in some power amplifier desi induced throu

The response time of the s time constant of the capacitor connected to the SQLCAP pin. The recommended value of this capacitor is 1.0 uF. The s

uelch feature can be disabled by connecting the SQLCAP

pin to VCC.

The active low output /SQLOUT nal s

uelch activates. This signal can be used to squelch the output power amplifier. S results in further reduction of noise; especiall power amplifier is runnin

s including: present in the original signal,

ns, or

h a poorly filtered power supply.

uelch circuit is controlled by the

oes low whenever the inter-

uelching the output amplifier

when the

at high gain & loud volumes.

The APR6016 derives its samplin sources: internal or external. If a clockin the EXTCLK input the device will automaticall as the samplin EXTCLK input the device automaticall nal clock source. When the EXTCLK pin is not used it should be tied to GND.

An internal clock divider is provided so that external clock si nals can be divided down to a desired samplin allows hi the EXTCLK pin. Usin allowing use of a clock already present in the system, as opposed to havin custom clock. Details for pro described in the SPI interface section under the PWRUP para

raph.

The default power up condition for the APR6016 is to use the internal oscillator at a samplin

Page 14 Voice Recording & Playback Device

clock source. If no input is present on the

h frequency signals of up to 10 MHz to be fed into

this feature simplifies designs b

to generate or externally divide down a

clock from one of two

signal is present on

use this signal

defaults to the inter-

-

rate. This

raming the clock divider are

frequency of 6.4 kHz.

Revision 1.0

Sample Application

g

y

g

y

µ

y

Figure 15 shows a sample application utilizing a generic microcontroller and SPI interface for messa

e management.

APR6016 Data Sheet

speaker. Several vendors suppl ers that can be used for this purpose.

integrated speaker amplifi-

Preliminary

The microcontroller uses three pla

, record and skip buttons. Five general purpose I/O sig-

eneral purpose inputs for the

nals are utilized in the SPI interface. The /RESET and /BUSY si

nal are not used in this design.

The output si

nal must be amplified in order to drive a

Figure 15 Sample Schematic using DIP package

Vcc

Generic

I/O _1

I/O_2

I/O_3

I/O_4

I/O_5

Microcontroller

F

0.1

I/O _6

/IR Q

I/O _7 I/O _8

/CS

DI

DO

VSSD

NC NC NC

ANAOUT-

ANAOUT+

NC

/RESET

VSSA

AUDOUT

SQLCAP

1 2 3 4 5 6 7 8 9 10 11 12 13 14

All resistors 2.2 K

Pla

Record

Skip

A microphone amplifier and AGC are recommended. Both blocks are optional. Several vendors suppl

integrated micro-

phone/AGC amplifiers that can be used for this purpose.

Note that the AGC circuit can be simplified by using the SQLCAP signal as a peak detector signal.

Vcc

2.2K

28 27 26 25 24 23 22 21 20 19

APR6016 DIP

18 17 16 15

2.2K

SCLK VCCD EXTCLK /INT SAC VSSA NC /BUSY NC NC VCCA ANAIN+ ANAIN/SQLOUT

Vcc

AGC Block

Vcc

Mic Pre-Amp

Mic

Vcc

Speaker Am plifier

100K

1.0 uF

Speaker

Voice Recording & Playback Device Page 15 Revision 1.0

Preliminary

APR6016 Data Sheet

Pin Descriptions

Table three shows pin descriptions for the APR6016 device. All pins are listed in numerical order with the exception of

Table 3 APR6016 28 Pin Number & Description

Pin Name

SAC 24 27

/INT 25 28

EXTCLK 26 29

SCLK 28 33

/CS 1 2

DI 2 3

DO 3 4

ANAOUT- 8 9

ANAOUT+ 9 10

/RESET 11 11

AUDOUT 13 15

SQLCAP 14 16

/SQLOUT 15 17

ANAIN- 16 18

Pin No.

28 pin

DIP

Pad No. (Die)

Reference Figure

18

Sector Address Control Output: Th

device is nearing the end of the current segment.

Interrupt Output: T

device reaches the end of a message or the device overflows. When connected to the interrupt input of the host microcontroller this output can be used to implement powerful message management options.

External Clock Input: T

sample clock instead of using the internal sampling clock. This pin should be connected to VSSA when not in use.

SPI Clock Input: D

ing edge of this clock. Data is clocked out of the part through the DO pin on the falling edge.

Chip Select Input: T

slave on the SPI interface. When this pin is high the device tri-states the DO pin and ignores data on the DI pin.

Data Input:

Data is clocked on the rising edge of the SCLK input.

Data Output: D

Negative Audio Output:

recorded messages. This output is usually fed to the negative input of a differential input power amplifier. The power amplifier drives an external speaker.

Positive Audio Output:

recorded messages. This output is usually fed to the positive input of a differential input power amplifier. The power amplifier drives an external speaker.

Reset Input: T

restores the device to its power up defaults.

Single Ended Audio Output: T

recorded messages. This output is usually fed to the input of a power amplifier for driving an external speaker.

Squelch Capacitor I/O:

Connect this pin to GND through a 1.0 uf capacitor to enable the squelch feature. The capacitor’s time constant will affect how quickly the squelch circuitry reacts.

Connect this pin to VCCA to disable the squelch feature.

Squelch Output:

squelch circuitry has activated. This signal can be used to automatically squelch the external power amplifier. Squelching the external power amplifier can result in an even greater reduction of background noise.

Inverting Analog Input: T

the user wishes to record. When the device is used in a differential input configuration this pin should receive a 16 mV peak to peak input coupled through a

0.1uF capacitor. When the device is used in a single ended input configuration this input should be tied to VSSA through a 0.1 uF capacitor.

VCC, VSS and NC pins which are listed at the end of the table.

Functionality

is active low output indicates when the

his active low open drain output goes low whenever the

his input can be used to feed the device an external

ata is clocked into the device through the DI pin upon the ris-

his active low input selects the device as the currently active

The DI input pin receives the digital data input from the SPI bus.

ata is available after the falling edge of the SCLK input.

This is the negative audio output for playback of pre-

This is the positive audio output for playback of pre-

his active low input clears all internal address registers and

his is the audio output for playback of pre-

This pin controls the attack time of the squelch circuitry.

This active low open drain output indicates when the internal

his input is the inverting input for the analog signal that

Page 16 Voice Recording & Playback Device

Revision 1.0

Preliminary

g

y

APR6016 Data Sheet

Pin Name Pin No.

28 pin TSOP

ANAIN+ 17 19

/BUSY 21 23

VCCD 27 30, 31, 32

VCCA 18 20, 21

VSSA 12,23 12, 13, 14, 24,

VSSD 4 5, 6

NC 5, 6, 7,

Pin No.

28 pin

DIP

10, 19,

20, 22

Pad No. (Die)

Reference Figure

18

25, 26

1, 7, 8, 22

Functionality

Non-Inverting Analog Input: T

signal that the user wishes to record. When the device is used in a differential input configuration this pin should receive a 16 mV peak to peak input coupled through a 0.1 uF capacitor. When the device is used in a single ended input configuration this pin should receive a 32 mV peak to peak input coupled through a

0.1 uF capacitor.

Busy Output: T

DIG_WRITE, DIG_READ or fast forward operation. The pin is tri-stated otherwise. This pin can be connected to an LED to indicate playback/record operation to the user. This pin can also be connected to an external microcontroller as an indication of the status of playback, record, forward, or digital operation.

Digital Power Supply: T

cuitry. This pin should be connected to the 3.0 V power plane through a via. This pin should also be connected to a 0.1 uF bypass cap as close to the pin as possible.

Analog Power Supply: T

circuitry. This pin should be connected to the 3.0 V power plane through a via. This pin should also be connected to a 0.1 uF bypass cap as close to the pin as possible.

Analog Ground:

via. The connection should be made as close to the pin as possible.

Digital Ground: Th

The connection should be made as close to the pin as possible.

No Connect:

nection of these pins to any signal, GND or VCC may result in incorrect device behavior or cause damage to the device.

his active low output is low during either a record, playback,

These pins should be connected to the ground plane through a

is pin should be connected to the ground plane through a via.

These pins should not be connected to anything on the board. Con-

his input is the non-inverting input for the analog

his connection supplies power for all on-chip digital cir-

his connection supplies power for all on-chip analog

Electrical Characteristics

The following tables list Absolute Maximum Ratings, Recom-

Absolute Maximum Ratings

Stresses greater than those listed in Table 4 may cause permanent dama sent a stress ratin an

other conditions above those specified in the recom-

e to the device. These specifications repre-

only. Operation of the device at these or

Table 4 Absolute Maximum Ratings.

Item Symbol Condition Min Max Unit

Power Supply voltage

Input Voltage

Storage Temperature

Temperature Under Bias

Lead Temperature

T

V

T

CC

IN

STG

BS

LD

TA = 25 C

Device VCC = 3.0 V -0.3 5.5 V

mended DC Characteristics, and recommended AC Characteristics for the APR6016 device.

mended DC Characteristics or recommended AC Characteristics of this specification is not implied. Maximum conditions for extended periods ma

- -65 150

- -65 125

<10s 300

affect reliability.

-0.3 7.0 V

o

C

o

C

o

C

Voice Recording & Playback Device Page 17 Revision 1.0

Preliminary

APR6016 Data Sheet

Table 5 DC Characteristics

Item Symbol Condition Min Typ Max Unit

Operating Voltage

Operating Temperature

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Leakage Current

Output Tristate Leakage Current I

Operating Current Consumption I

Standby Current Consumption

VCCA VCCD

T

A

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

OZ

CC

I

CCS

2.9 3.0 3.3 V

0 +70

VCC = 2.9V 2.4 3 5.5 V

VCC = 3.3V VSS - 0.3V 0 .4 V

VCC = 2.7V

=-1.6mA

I

OH

VCC = 2.7V

I

=1.0mA

OL

VCC = 3.3V uA

V

IH=VCC

VCC = 3.3V uA

V

IL=VSS

VCC = 3.3V

V

OUT=VCC uA

VCCD - 0.5V V

0.4 V

0.3 1

0-1

+1

or

V

OUT=Vss

VCC = 3.3V

Recording

Playback

Idle

VCC = 3.3V uA

25 15

2.5

mA mA mA

1

After 20 sec.

o

C

Table 6 AC Characteristics

Item Symbol Condition Min Typ Max Unit

ANAIN+ or ANAIN- input voltage

ANAIN+ input resistance

ANAIN+/ANAIN- Gain

ANAOUT Output Voltage

Total Harmonic Distortion

VCC ready to fall /CS

/RESET low time

Rise /RESET to fall /CS

/CS fall to clock edge

SPI Data set-up time

Period SPI clock

SPI data hold time

SPI clock low time

V

MI

R

ANAIN K Ohm

G

ANAIN

V

ANOUT

THD @ 1kHz & 45mV

T

pwrup

T

loRST ms

T

Rdone ms

T

fcs

T

suDI

T

pSCLK

T

hDI

T

loSCLK

90% of VCC min. specification 10 ms

input 0.5 1 %

P-P

1

500 ns

200 ns

1000 ns

200 ns

400 ns

45 50 mV

3

22 23 dB

560 700 m

P-P

VP-P

Page 18 Voice Recording & Playback Device

Revision 1.0

Item Symbol Condition Min Typ Max Unit

SPI clock high time

Clock to rising edge of /CS

Fall of /CS to DO output

Fall of SCLK to data out valid

Rise of /CS to DO high Z

Period SPI clock for DIG_READ, write

First SET_REC command to start recording

Rise of SAC after STOP Command to end of recording

First SET_PLAY command to audio output

STOP after SET_PLAY or PLAY to end of audio output

SAC period

SAC low time

See Figure 6 and Table 1

Preliminary

APR6016 Data Sheet

T

hiSCLK

T

rCS

T

fcsDO

T

fSCLK

T

hzDO

DT

pSCLK

Tarec @4kHz Internal sample clock

TSarec @4kHz Internal sample clock

Taplay @4kHz Internal sample clock

TSaplay @4kHz Internal sample clock

T

pSAC

T

loSAC

T

next1

T

next2 mS

T

next3

@4kHz Internal sample clock @8kHz Internal sample clock

External sample clock

@8kHz Internal sample clock

External sample clock

@8kHz Internal sample clock

External sample clock

@8kHz Internal sample clock

External sample clock

@8kHz Internal sample clock

External sample clock

REC, PLAY @4kHz

REC, PLAY @8kHz

REC, PLAY EXTCLK

FWD @4kHz FWD @8kHz

FWD @ EXTCLK

REC, PLAY @4kHz

REC, PLAY @8kHz

REC, PLAY EXTCLK

FWD @4kHz FWD @8kHz

FWD @ EXTCLK

@4kHz Internal sample clock @8kHz Internal sample clock

External sample clock

400 ns

200 ns

1000 ns

500 ns

500 uS 250 uS

Equation 1

376 188

Equation 2

658 329

Equation 2

658 329

Equation 9

376 188

Equation 2

752 376

Equation 3

2 1

Equation 4

94 47

Equation 5

0.25

0.125

Equation 6

5 uS

5

752 376

Equation 3

S

ms ms

S

ms ms

S

ms ms

S

ms ms

S

ms ms

S

ms ms

S

ms ms

S

Voice Recording & Playback Device Page 19 Revision 1.0

Preliminary

APR6016 Data Sheet

Item Symbol Condition Min Typ Max Unit

See Figure 6 and Table 1

Notes:

ExternalClockPeriod

---------- ------------ ------------- ------------- ---------

Equation1

Equation2

Equation3

Equation4

Equation5

Equation6

Equation7

Equation8

Equation9

=

2 PrescalerValue()

1504 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- -------- -----

=

3008 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- -------- -----

=

8 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- ----

=

376 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- -------- --

=

ExternalClockPeriod

---------- ------------ ------------- ------------- ---------

=

1880 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- -------- -----

=

5 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- ----

=

2632 ExternalClockPeriod()

---------- ------------ ------------- ------------- ------------- -------- -----

=

PrescalerValue

T

next4

Previous command =

SET_REC, REC,

SET_PLAY, PLAY

@4kHz Internal sample clock @8kHz Internal sample clock

External sample clock

Previous command =

SET_FWD, FWD

@4kHz Internal sample clock @8kHz Internal sample clock

External sample clock

Previous command =

All Others @4kHz Internal sample clock @8kHz Internal sample clock

External sample clock

470 235

Equation 7

1.25

0.625

Equation 8

5 uS 5 uS

5 uS

ms ms

S

ms ms

Page 20 Voice Recording & Playback Device

Revision 1.0

Preliminary

APR6016 Data Sheet

Figure 17 28 pin dual inline package (DIP)

Q

1

D

PIN NO. 1

SEE NOTE 9

C

L

OPTIONAL EJECTOR PIN

INDENTION SHOWN FOR

CONVENTIONAL MOLD

P

ONLY

Q

2

A

6°-16° 4 PLCS.

E

1

BASE PLANE

SEATING PLANE

A

1

S

Y

M

B

A A

B B

C D E E

e e L

a a

N P

Q Q

S

INCHES MILLIMETERS

O

L

MIN. NOM. MAX. MIN. NOM. MAX.

.190

1

.015

.018

.015

1

1.445

.055 .008

.060 .010

1.450

.600

1

A

.530

.100 BSC .600 BSC

.540

.125 .135

o

0

28

.685

1

.065

.070

2

.070

.150 .075 .080

.022 .065 .012

1.455 .625 .550

.075

0.38

1.40

0.20

36.70

15.24

13.46

15.24 BSC

3.18

o

15

o

0

17.40

1.65

1.78 1.91 2.03

0.46

1.52

0.25

36.83

13.72 13.97

2.54 BSC

28

1.78 1.91

3.18

B

1

4.83

0.56

1.65

0.30

36.96

15.88

3.43 15

a

e

B

1

L

C

e

A

NOTES:

N

1. REFER TO APPLICABLE SYMBOL LIST.

O

T

E

2. DIMENSIONING AND TOLERANCE PER ANSI Y14.5-1982.

3. APPLIES TO SPREAD LEADS PRIOR TO INSTALLATION.

4. N IS THE MAXIMUM QUANTITY OF LEAD POSITIONS

5. DIMENSION D & E ARE TO BE MEASURED AT MAXIMUM MATERIAL CONDITION BUT DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 INCH/0.254

5

mm.

6. CONTROLLING DIMENSION: INCH

5

7. DIMENSION A, A1 & L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GUAGE GS-3.

8. THIS PACKAGE CONFORMS TO JEDEC REFERENCE MS-

3

o

4

011, VARIATION AB.

9. IT IS AN OPTION TO SHOW PIN 1 IDENTIFIER.

Page 21 Voice Recording & Playback Device

Revision 1.0

Figure 18 Bond Pad Layout and Coordinates

µ

g

Origin

0

8

9

A

N

A

O

10 /RESET

11 VSSA

12 VSSA

13 VSSA

14 AUDOUT

U

T

T+

-

X Coordinate

APR6016 Data Sheet

7

6

C

N

Preliminary

VSSD 5

VSSD 4

DO 3

DI 2

/CS 1

15 SQLCAP

Y Coordinate

16 /SQLOUT

17 ANAIN-

18 ANAIN+

19 VCCA 20 VCCA

1

2

Y

S

U

C

B

N

/

2

Table 7 Coordinate Information

Pad

Number Pad Name

1 /CS 8008 1460

2 DI 8008 1173

3 DO 8008 865

4 VSSD 8008 620

5 VSSD 8008 393

6 NC 7654 119

7 NC 7271 119

8 ANAOUT- 570 119

9 ANAOUT+ 299 119

10 /RESET 119 384

11 VSSA 119 665

12 VSSA 119 837

13 VSSA 119 1124

14 AUDOUT 119 1454

15 SQLCAP 119 1894

16 /SQLOUT 119 2528

17 ANAIN- 119 2805

18 ANAIN+ 119 3076

19 VDDA 119 3407

20 VDDA 119 3637

21 NC 258 4116

X

CoordinateY Coordinate

V

S

Pad

Number Pad Name

S

A

2

3

S

A

2

4

5

X

Coordinate

S

A

C

22 /BUSY 558 4116

23 VSSA 7172 4116

24 VSSA 7345 4116

25 VSSA 7517 4116

26 SAC 7765 4116

27 NC 8008 3806

28 NC 8008 3506

29 /INT 8008 3114

30 EXTCLK 8008 2808

31 VCCD 8008 2433

32 VCCD 8008 2200

33 VCCD 8008 2029

34 SCLK 8008 1802

DIE SIZE 8230 PAD SIZE:100

x 4360

x 100

DIE THICKNESS: Approximately 25 mils

NOTE:

1. Substrate should be connected to GND.

2. Coordinates

iven in Table 7 are for pad centers.

SCLK 34

VCCD 33

VCCD 32

VCCD 31

EXTCLK 30

/INT 29

2

6

Coordinate

NC 28

NC 27

Y

Voice Recording & Playback Device Page 22 Revision 1.0

•POWER APPLICATION CIRCUIT DIAGRAM

•APPLICATION CIRCUIT DIAGRAM

Page 23 Voice Recording & Playback Device

Rainbow Electronics APR6016 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual