• 16ms (@ 8KHz sampling rate) Debounce Time in Key Trigger Mode.
• 65us (@ 8KHz sampling rate) Debounce Time in CPU Parallel Trigger Mode.
• RST pin set to HIGH to stop playback at once.
• Two user programmable outputs for STOP pulse, BUSY signal and flashing LED.
• Built-in oscillator to control sampling frequency with an external resistor.
• 2.6V – 5.0V; Wide range single power supply and < 5uA low stand-by current.
• PWM Vout1 and Vout2 drive speaker directly.
• D/A COUT to drive speaker through an external BJT.
• Development System support voice compilation and options selection.
DESCRIPTION
aP8921A/10A series high performance Voice OTP is fabricated with Standard CMOS process with
embedded 512K/256K bits EPROM. It can store up to 21/10sec voice message with 4-bit
ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable
option. Two trigger modes, simple Key trigger mode and Parallel CPU trigger mode facilitate
different user interface. User selectable triggering and output signal options provide maximum
flexibility to various applications. Built-in resistor controlled oscillator, 8-bit current mode D/A
output and PWM direct speaker driving output minimize the number of external components. PC
controlled programmer and developing software are available.
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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1 2 3 4 5 6 7 8 16
9
OUT1
VOUT1
VOUT2
VSS
OUT2
V33
COUT
OSC
VPP
VDD
S1
S2
S3 S4 SBT
RST
PIN CONFIGURATIONS
15
14
13
12
11
10
PIN NAMES
PIN
Playback
Mode
1 OUT1 OEB Programmable output (I/O pin)
2 VOUT1 - PWM output to drive speaker directly
3 VOUT2 - PWM output to drive speaker directly
4 VSS VSS Power Ground
5 OUT2 IO Programmable output (I/O pin)
6 V33 V33 Power Supply for OTP programming
7 COUT - D/A current output
8 OSC ACLK Oscillator input
9 VPP VPP Supply voltage for OTP programming
10 S1 S1 Trigger pin (input with internal pull-down)
11 S2 S2 Trigger pin (input with internal pull-down)
OTP Program
Description
Mode
12 VDD VDD 2.6 – 5.0V Positive Power Supply
13 S3 S3 Trigger (input with internal pull-down)
14 S4 S4 Trigger (input with internal pull-down)
15 SBT PGM Trigger pin (input with internal pull-down)
16 RST DCLK Reset pin (input with internal pull-down)
Ver 2.0 Dec 6, 2006
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PIN DESCRIPTIONS
S1 ~ S4
Input Trigger Pins:
- S1 to S4 is used to trigger the 12 Voice Groups in both Key and CPU Parallel Trigger Mode.
- In OTP Programming Mode, S1 to S4 are used as program enable pins.
SBT
Input Trigger Pin:
- In Key Trigger Mode, this pin is trigger pin to trigger the playback of Voice Groups one by one
sequentially.
- In CPU Parallel Command Mode, this pin is used as address strobe to latch the input from S1 to
S4 and starts the voice playback.
- In OTP Programming Mode, this pin is used as PGM signal.
VDD and V33
Power Supply Pin for normal and programming operation
VSS
Power Ground Pin
VOUT1 and VOUT2
Digital PWM output pins which can drive speaker and buzzer directly for voice playback.
OSC
During voice playback, an external resistor is connected between this pin and the VDD pin to set
the sampling frequency. In OTP Programming Mode, this is the ACLK input signal.
VPP
No connection during voice playback. In OTP Programming Mode, this pin is connected to a
separate 6.5V power supply.
OUT1 and OUT2
- In Key Trigger Mode and CPU Parallel Command Mode, these pins are user programmable pins
for the STOP pulse, BUSY and LED signals.
- During OTP programming, OUT1 serves as OEB while OUT2 serves as data IO.
COUT
Analog 8-bit current mode D/A output for voice playback
RST
Chip reset in playback mode or DCLK pin in OTP programming mode.
Ver 2.0 Dec 6, 2006
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VOICE SECTION COMBINATIONS
Voice files created by the PC base developing system are stored in the built-in EPROM of the
aP8921A/10A chip as a number of fixed length Voice Blocks. Voice Blocks are then selected and
grouped into Voice Groups for playback. Up to 12 Voice Groups are allowed. A Voice Block
Table is used to store the information of combinations of Voice Blocks and then group them
together to form Voice Group.
Chip aP8921A aP8910A
Memory size 512K bits 256K bits
Max no. of Voice Block 126 126
No. of bytes per Voice Block 512 256
Max. no. of Voice Group 12 12
No. of Voice Table entries 960 960
Voice Length (@ 6KHz 4-bit ADPCM) 21 sec 10 sec
Example of Voice Block Combination
Assume here we have three voice files, they are “How are You?”, Sound Effect and Music. Each
of the voice file is divided into a number of fixed length Voice Block and stored into the memory.
Voice File 1 - “How are You?” is stored in Voice Block B0 to B12.
Voice File 2 - Sound Effect is stored in Voice Block B13 to B15.
Voice File 3 - Music is Voice Block B16 to B40.
Voice Blocks are grouped together using Voice Table to form Voice Group for playback:
Group no. Voice Group contents Voice Table Entries
Group 1 “How are You?”B0 … B12
Group 2 Sound Effect + “How are You?”B13 … B15 + B0 … B12
Group 3 “How are You?” + Music B0 … B12 + B16 … B40
Group 4 Music B16 … B40
Voice Data Compression
Voice File data is stored in the on-chip EPROM as either 4-bit ADPCM or 8-bit PCM format.
Voice data stored as 4-bit ADPCM provides 2:1 data compression which can save 50% of memory
space. On the other hand, voice data are stored as 8-bit PCM format means no data compression is
employed but voice playback quality will be better.
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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Programmable Options
In both Key Trigger Mode and CPU Parallel Trigger Mode, user can select different trigger
functions and output signals to be sent out from the pins OUT1 and OUT2.
Options affect all Voice Group playback are called Whole Chip Options. Options only affect the
playback of individual Voice Group are called Group Options.
Whole Chip Options
• Key or CPU Parallel Trigger Mode.
• Ramp-up-down enable or disable:
When COUT is used for playback, Ramp-up-down should be enabled. This function
eliminates the ‘POP’ noise at the beginning and end of voice playback.
When VOUT1 and VOUT2 are used to drive speaker directly, Ramp-up-down should be
disabled.
Note: Stop plus must be set to enable in order to have STOP plus to come out.
aP8910A aP8921A
OUT1 OUT2 OUT1 OUT2
Fig. 3 Output waveforms
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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Group Options
User selectable options that affect each individual group are called Group Options. They are:
• Edge or Level trigger
• Unholdable or Holdable trigger
• Re-triggerable or non-retriggerable
• Stop pulse disable or enable
Fig. 4 to Fig. 9 show the voice playback with different combination of triggering mode and the
relationship between outputs and voice playback.
Fig. 4 Level, Unholdable, Non-retriggerable
Fig. 5 Level Holdable
Fig. 6 SBT sequential trigger with Level Holdable and Unholdable
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Fig. 7 Edge, Unholdable, Non-retrigger
Fig. 8 Edge, Holdable
Fig. 9 SBT sequential trigger with Edge Holdable and Unholdable
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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Overlap trigger is supported with Level/Unholdable trigger options:
Fig. 10 Overlap trigger
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Integrated Circuits Inc. aP8921A/10A
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TRIGGER MODES
Two trigger modes, the KEY and CPU modes, are available for aP8921A/10A series which are
determined by setting the EPORM programmable options during voice data compilation.
For both trigger modes, up to 12 Voice Groups are being played back according to the following
setting of trigger pins S1 to S4.
Voice Group S1 S2 S3 S4
1 HIGH NC NC NC
2 NC HIGH NC NC
3 NC NC HIGH NC
4 NC NC NC HIGH
5 HIGH HIGH NC NC
6 NC HIGH HIGH NC
7 NC NC HIGH HIGH
8 HIGH NC NC HIGH
9 HIGH HIGH HIGH NC
10 NC HIGH HIGH HIGH
11 HIGH NC HIGH HIGH
12 HIGH HIGH NC HIGH
Note: Where NC (open or no connection) should be replaced by a logic input LOW in CPU
Parallel Trigger Mode.
Key Trigger Mode
With this trigger mode, up to 12 Voice Groups are triggered by setting S1 to S4 to HIHG or NC in
different combinations. Each Voice Group can have its only independent trigger options (See Fig.
4, 5, 7 and 8 for trigger options definition).
Voice Groups can also be triggered sequentially by setting SBT pin to HIGH.
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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CPU Parallel Trigger Mode
In this mode, S1 to S4 are set to HIGH or LOW according to the table above and followed by
setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered.
Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode.
Fig. 11 CPU Parallel Trigger Mode
Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. In stead, it
acts as a Strobe input to clock-in the data input from S1 to S4 into the chip.
Voice Groups address is determined by the Voice Group Trigger Table. For example:
S1..S4 = 1000 for Voice Group #1
S1..S4 = 0100 for Voice Group #2
• • •
S1..S4= 1100 for Voice Group #5
• • •
S1..S4 = 1110 for Voice Group #9
• • •
S1..S4 = 1101 for Voice Group #12
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Unit
VDD - VSS
VIN V
V
V
OUT
SS
T (Operating):
DIP
SOP
T (Junction) -40 ~ +125
T (Storage) -55 ~ +125
-0.5 ~ +6 V
- 0.3<VIN<V
DD/33
SS <VOUT<VDD/33
-10 ~ +70
-40 ~ +85
+ 0.3
V
V
℃
℃
℃
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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DC CHARACTERISTICS ( T
= 0 to 70℃, VDD = 4.5V, VSS = 0V )
A
Symbol Parameter Min. Typ. Max.
VDD
ISB
IOP
VIH
VIL
IOL
IOH
Operating Voltage 2.6 4.5 5.0 V
Standby current
Operating current
1 5
"H" Input Voltage 2.5 3.0 3.5 V
"L" Input Voltage -0.3 0 0.5 V
V
low O/P Current
OUT
V
high O/P Current
OUT
110
-110
Unit Condition
μA
15 mA I/O open
mA
mA
I/O open
VDD=3.0V
VDD=3.0V
Vout=0.3V, VDD=5.0V
Vout=2.5V, VDD=5.0V
ICO
IOH
IOL
∆F/F
C
O/P Current
OUT
O/P high Current
O/P low Current
Frequency Stability -5
-3
-8
8
+5
mA
mA
mA
%
V
COUT
=1.0V
VOH=2.5V, VDD=5.0V
VOL=0.3V, VDD=5.0V
Fosc(5.0V) – Fosc(4.0V)
Fosc(4.5V)
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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S1~S
4
TIMING WAVEFORMS
KEY Trigger Mode
S1~S4, SBT
COUT
tKD
tSTPD
STOP
BUSY
tBD
tBH
CPU Parallel Mode
Addr.
SBT
tAS
tSBTW
AC CHARACTERISTICS ( T
Symbol Parameter Min. Typ. Max.
tKD
tKD
t
STPD
Key trigger debounce time 16
Key trigger debounce time – retrigger 24
STOP pulse output delay time
tAH
= 0 to 70℃, VDD = 4.5V, VSS = 0V, 8KHz sampling )
A
256
tSTPW
Unit Note
ms 1
ms 1
μs
t
tBD
tBH
tAS
tAH
t
t
STPW
SBTW
LEDC
STOP pulse width
BUSY signal output delay time
BUSY signal output hold time
Address set-up time 100
Address hold time 100
SBT stroke pulse width 65
LED flash frequency
64
100
3
ms 1
100 ns
ns
ns
ns
μs
Hz 2
Notes :
1. This parameter is inversely proportional to the sampling frequency.
2. This parameter is proportional to the sampling frequency.
Note: The data in the above tables are within 3% accuracy and measured at VDD = 4.5V. Oscillator
frequency is subjected to IC lot to lot variation.
FREQUENCY AGAINST VDD STABILITY
aP8921A Freqency Stability (Rosc = 293K Ohm)
10.0%
5.0%
0.0%
-5.0%
-10.0%
△F (%)
-15.0%
-20.0%
-25.0%
-30.0%
5.50 5.00 4.50 4.00 3.503.00 2.60
VDD (V)
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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S1 S2 S3 S4
Speaker
8 ΩSpeaker
TYPICAL APPLICATIONS
4.5~5V
Cin
4.7uF
Rosc
0.1uF
RST
OSC
SBT
VDD
V33
COUT
VOUT1
VOUT2
OUT1
VSS
0.1uF
16 Ω
1KΩ
Cout
1~2uF
8050D
390Ω
Fig. 12 Using 4.5V Battery
Note 1: Two capacitors Cin and Cout must be connected from VDD and V33 pins to VSS to
stabilize the power supply to the chip. When small capacity battery, e.g. AG10, is
used, Cin and Cout may need to be as large as 22uF. However, if Cin and Cout is
too large, the power-up reset generated by 0.1uF at the RST pin may not be function
because it takes longer time for both Cin and Cout to discharge.
Note 2: 16 Ohm speaker will provide lauder and better sound quality when the VOUT speaker
direct drive is used.
Note 3: The value of the 390 Ohm base resistor should be modified according to different Vdd
value, the kind of speaker and NPN transistor.
Note 4: The VPP pin should be leave unconnected for playback.
Ver 2.0 Dec 6, 2006
Integrated Circuits Inc. aP8921A/10A
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BONDING PADS
aP8921A
Fig. 12 Pad Locations
Notes:
1. VPP pad should be not connected during voice playback.
2. Substrate should be connected to the Power GND.
Ver 2.0 Dec 6, 2006
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